C++ dsim_write_mask函数代码示例

void dsim_reg_set_porch(struct decon_lcd *lcd)
{
	u32 val, mask, width, height;

	if (lcd->mode == VIDEO_MODE) {
		val = DSIM_MVPORCH_CMD_ALLOW(DSIM_CMD_ALLOW_VALUE) |
			DSIM_MVPORCH_STABLE_VFP(DSIM_STABLE_VFP_VALUE) |
			DSIM_MVPORCH_VBP(lcd->vbp);
		mask = DSIM_MVPORCH_CMD_ALLOW_MASK | DSIM_MVPORCH_VBP_MASK |
			DSIM_MVPORCH_STABLE_VFP_MASK;
		dsim_write_mask(DSIM_MVPORCH, val, mask);

		val = DSIM_MHPORCH_HFP(lcd->hfp) | DSIM_MHPORCH_HBP(lcd->hbp);
		dsim_write(DSIM_MHPORCH, val);

		val = DSIM_MSYNC_VSA(lcd->vsa) | DSIM_MSYNC_HSA(lcd->hsa);
		mask = DSIM_MSYNC_VSA_MASK | DSIM_MSYNC_HSA_MASK;
		dsim_write_mask(DSIM_MSYNC, val, mask);
	}

	width = GET_W(lcd->hsync_2h_cycle, lcd->xres);
	height = GET_H(lcd->hsync_2h_cycle, lcd->yres);

	val = DSIM_MDRESOL_VRESOL(height) | DSIM_MDRESOL_HRESOL(width);
	mask = DSIM_MDRESOL_VRESOL_MASK | DSIM_MDRESOL_HRESOL_MASK;
	dsim_write_mask(DSIM_MDRESOL, val, mask);
}

void dsim_reg_set_porch(u32 id, struct decon_lcd *lcd)
{
	u32 val, mask, width;

	if (lcd->mode == DECON_VIDEO_MODE) {
		val = DSIM_MVPORCH_CMD_ALLOW(DSIM_CMD_ALLOW_VALUE) |
			DSIM_MVPORCH_STABLE_VFP(DSIM_STABLE_VFP_VALUE) |
			DSIM_MVPORCH_VBP(lcd->vbp);
		mask = DSIM_MVPORCH_CMD_ALLOW_MASK | DSIM_MVPORCH_VBP_MASK |
			DSIM_MVPORCH_STABLE_VFP_MASK;
		dsim_write_mask(id, DSIM_MVPORCH, val, mask);

		val = DSIM_MHPORCH_HFP(lcd->hfp) | DSIM_MHPORCH_HBP(lcd->hbp);
		dsim_write(id, DSIM_MHPORCH, val);

		val = DSIM_MSYNC_VSA(lcd->vsa) | DSIM_MSYNC_HSA(lcd->hsa);
		mask = DSIM_MSYNC_VSA_MASK | DSIM_MSYNC_HSA_MASK;
		dsim_write_mask(id, DSIM_MSYNC, val, mask);
	}

	if (lcd->mic_enabled)
		width = (lcd->xres/3) + (lcd->xres % 4);
	else
		width = lcd->xres;

	/* TODO: will be added SHADOW_EN in EVT1 */
	val = DSIM_MDRESOL_VRESOL(lcd->yres) | DSIM_MDRESOL_HRESOL(width);
	mask = DSIM_MDRESOL_VRESOL_MASK | DSIM_MDRESOL_HRESOL_MASK;
	dsim_write_mask(id, DSIM_MDRESOL, val, mask);
}

void dsim_reg_set_dphy_timing_values(struct dphy_timing_value *t)
{
	u32 val, mask;

	val = DSIM_PHYTIMING_M_TLPXCTL(t->lpx) |
		DSIM_PHYTIMING_M_THSEXITCTL(t->hs_exit);
	dsim_write(DSIM_PHYTIMING, val);

	val = DSIM_PHYTIMING1_M_TCLKPRPRCTL(t->clk_prepare) |
		DSIM_PHYTIMING1_M_TCLKZEROCTL(t->clk_zero) |
		DSIM_PHYTIMING1_M_TCLKPOSTCTL(t->clk_post) |
		DSIM_PHYTIMING1_M_TCLKTRAILCTL(t->clk_trail);
	dsim_write(DSIM_PHYTIMING1, val);

	val = DSIM_PHYTIMING2_M_THSPRPRCTL(t->hs_prepare) |
		DSIM_PHYTIMING2_M_THSZEROCTL(t->hs_zero) |
		DSIM_PHYTIMING2_M_THSTRAILCTL(t->hs_trail);
	dsim_write(DSIM_PHYTIMING2, val);

	val = DSIM_PHYCTRL_B_DPHYCTL(t->b_dphyctl) |
		DSIM_PHYCTRL_B_DPHYCTL_VREG_LP |
		DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP;
	mask = DSIM_PHYCTRL_B_DPHYCTL_MASK |
		DSIM_PHYCTRL_B_DPHYCTL_VREG_LP |
		DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP;
	dsim_write_mask(DSIM_B_DPHYCTRL, val, mask);

	val = DSIM_PHYCTRL_M_DPHYCTL_VREG_HS;
	mask = DSIM_PHYCTRL_M_DPHYCTL_VREG_HS;
	dsim_write_mask(DSIM_M_DPHYCTRL, val, mask);
}

void dsim_reg_dp_dn_swap(u32 id, u32 en)
{
	u32 val = en ? ~0 : 0;
	u32 mask = DSIM_PLLCTRL_DPDN_SWAP_DATA | DSIM_PLLCTRL_DPDN_SWAP_CLK;

	dsim_write_mask(id, DSIM_PLLCTRL, val, mask);
}

void dsim_reg_set_config(u32 mode, u32 data_lane_cnt)
{
	u32 val;
	u32 mask;

	if (mode == VIDEO_MODE) {
		val = DSIM_CONFIG_VIDEO_MODE | DSIM_CONFIG_BURST_MODE |
		DSIM_CONFIG_HFP_DISABLE | DSIM_CONFIG_MFLUSH_VS;
	} else if (mode == COMMAND_MODE) {
		val = DSIM_CONFIG_CLKLANE_STOP_START;   /* In Command mode Clk lane stop disable */
	} else {
		dsim_err("This DDI is not MIPI interface.\n");
		return;
	}

	val |= DSIM_CONFIG_EOT_R03_DISABLE |
		DSIM_CONFIG_NUM_OF_DATA_LANE(data_lane_cnt - 1) |
		DSIM_CONFIG_PIXEL_FORMAT(DSIM_PIXEL_FORMAT_RGB24);

	mask = DSIM_CONFIG_CLKLANE_STOP_START | DSIM_CONFIG_MFLUSH_VS | DSIM_CONFIG_EOT_R03_DISABLE |
		DSIM_CONFIG_BURST_MODE | DSIM_CONFIG_VIDEO_MODE | DSIM_CONFIG_HFP_DISABLE |
		DSIM_CONFIG_PIXEL_FORMAT_MASK | DSIM_CONFIG_NUM_OF_DATA_LANE_MASK;

	dsim_write_mask(DSIM_CONFIG, val, mask);
}

void dsim_reg_set_pkt_go_ready(void)
{
	unsigned long flags;
	spin_lock_irqsave(&pktgo_lock, flags);
	dsim_write_mask(DSIM_MULTI_PKT, ~0, DSIM_PKT_GO_RDY);
	spin_unlock_irqrestore(&pktgo_lock, flags);
}

void dsim_reg_enter_ulps(u32 id, u32 enter)
{
	u32 val = enter ? ~0 : 0;
	u32 mask = DSIM_ESCMODE_TX_ULPS_CLK | DSIM_ESCMODE_TX_ULPS_DATA;

	dsim_write_mask(id, DSIM_ESCMODE, val, mask);
}

void dsim_reg_exit_ulps(u32 id, u32 exit)
{
	u32 val = exit ? ~0 : 0;
	u32 mask = DSIM_ESCMODE_TX_ULPS_CLK_EXIT | DSIM_ESCMODE_TX_ULPS_DATA_EXIT;

	dsim_write_mask(id, DSIM_ESCMODE, val, mask);
}

void dsim_reg_set_esc_clk_prescaler(u32 id, u32 en, u32 p)
{
	u32 val = en ? DSIM_CLKCTRL_ESCCLK_EN : 0;
	u32 mask = DSIM_CLKCTRL_ESCCLK_EN | DSIM_CLKCTRL_ESC_PRESCALER_MASK;

	val |= DSIM_CLKCTRL_ESC_PRESCALER(p);
	dsim_write_mask(id, DSIM_CLKCTRL, val, mask);
}

void dsim_reg_set_pkt_go_enable(bool en)
{
	unsigned long flags;
	u32 val = en ? ~0 : 0;
	spin_lock_irqsave(&pktgo_lock, flags);
	dsim_write_mask(DSIM_MULTI_PKT, val, DSIM_PKT_GO_EN);
	spin_unlock_irqrestore(&pktgo_lock, flags);
}

/*
 * dsim main display configuration for window partial update
 *	- w : width for partial update
 *	- h : height for partial update
 *	- mic_on : MIC_ENABLE (1) / MIC_DISABLE (0)
 */
void dsim_reg_set_win_update_conf(int w, int h, bool mic_on)
{
	u32 val;
	u32 mask;

	if (mic_on)
		w = ((w >> 2) << 1) + (w & 0x3);
	/* Before setting config. disable standby */
	mask = DSIM_MDRESOL_STAND_BY;
	val = 0;
	dsim_write_mask(DSIM_MDRESOL, val, mask);

	val = DSIM_MDRESOL_VRESOL(h) | DSIM_MDRESOL_HRESOL(w) |
		DSIM_MDRESOL_STAND_BY;
	mask = DSIM_MDRESOL_STAND_BY | DSIM_MDRESOL_VRESOL_MASK |
		DSIM_MDRESOL_HRESOL_MASK;
	dsim_write_mask(DSIM_MDRESOL, val, mask);
}

/*
 * dsim main display configuration for window partial update
 *	- w : width for partial update
 *	- h : height for partial update
 *	- mic_on : MIC_ENABLE (1) / MIC_DISABLE (0)
 */
void dsim_reg_set_win_update_conf(int w, int h, struct decon_lcd *lcd)
{
	u32 val;
	u32 mask;

	w = GET_W(lcd->hsync_2h_cycle, w);
	h = GET_H(lcd->hsync_2h_cycle, h);

	/* Before setting config. disable standby */
	mask = DSIM_MDRESOL_STAND_BY;
	val = 0;
	dsim_write_mask(DSIM_MDRESOL, val, mask);

	val = DSIM_MDRESOL_VRESOL(h) | DSIM_MDRESOL_HRESOL(w) |
		DSIM_MDRESOL_STAND_BY;
	mask = DSIM_MDRESOL_STAND_BY | DSIM_MDRESOL_VRESOL_MASK |
		DSIM_MDRESOL_HRESOL_MASK;
	dsim_write_mask(DSIM_MDRESOL, val, mask);
}

void dsim_reg_set_int(u32 id, u32 en)
{
	u32 val = en ? 0 : ~0;
	u32 mask;

	mask = DSIM_INTMSK_SFR_PL_FIFO_EMPTY | DSIM_INTMSK_SFR_PH_FIFO_EMPTY |
		DSIM_INTMSK_FRAME_DONE | DSIM_INTMSK_RX_DATA_DONE |
		DSIM_INTMSK_RX_ECC;

	dsim_write_mask(id, DSIM_INTMSK, val, mask);
}

void dsim_reg_set_dphy_timing_values(struct dphy_timing_value *t)
{
	u32 val, mask;

	val = DSIM_PHYTIMING_M_TLPXCTL(t->lpx) |
		DSIM_PHYTIMING_M_THSEXITCTL(t->hs_exit);
	dsim_write(DSIM_PHYTIMING, val);

	val = DSIM_PHYTIMING1_M_TCLKPRPRCTL(t->clk_prepare) |
		DSIM_PHYTIMING1_M_TCLKZEROCTL(t->clk_zero) |
		DSIM_PHYTIMING1_M_TCLKPOSTCTL(t->clk_post) |
		DSIM_PHYTIMING1_M_TCLKTRAILCTL(t->clk_trail);
	dsim_write(DSIM_PHYTIMING1, val);

	val = DSIM_PHYTIMING2_M_THSPRPRCTL(t->hs_prepare) |
		DSIM_PHYTIMING2_M_THSZEROCTL(t->hs_zero) |
		DSIM_PHYTIMING2_M_THSTRAILCTL(t->hs_trail);
	dsim_write(DSIM_PHYTIMING2, val);

	val = DSIM_PHYCTRL_B_DPHYCTL(t->b_dphyctl) |
		DSIM_PHYCTRL_B_DPHYCTL_VREG_LP;
	mask = DSIM_PHYCTRL_B_DPHYCTL_MASK | DSIM_PHYCTRL_B_DPHYCTL_VREG_LP;
#if defined(CONFIG_DECON_LCD_EA8064G) && !defined(CONFIG_SEC_FACTORY)	/* Should be removed */
	val |= DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP;
	mask |= DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP;
#endif
	dsim_write_mask(DSIM_B_DPHYCTRL, val, mask);

	val = DSIM_PHYCTRL_M_DPHYCTL_VREG_HS;
	mask = DSIM_PHYCTRL_M_DPHYCTL_VREG_HS;
	dsim_write_mask(DSIM_M_DPHYCTRL, val, mask);

	val = DSIM_M_PLLCTRL_SET1(t->m_pllctl) |
		DSIM_M_PLLCTRL_SET3(DSIM_M_PLLCTRL_VALUE3) |
		DSIM_M_PLLCTRL_SET2;
	mask = DSIM_M_PLLCTRL_SET1_MASK |
		DSIM_M_PLLCTRL_SET3_MASK |
		DSIM_M_PLLCTRL_SET2;
	dsim_write_mask(DSIM_M_PLLCTRL, val, mask);
}

void dsim_reg_set_porch(u32 id, struct decon_lcd *lcd)
{
	u32 val, mask, width;

	if (lcd->mode == DECON_VIDEO_MODE) {
		val = DSIM_MVPORCH_CMD_ALLOW(DSIM_CMD_ALLOW_VALUE) |
			DSIM_MVPORCH_STABLE_VFP(DSIM_STABLE_VFP_VALUE) |
			DSIM_MVPORCH_VBP(lcd->vbp);
		mask = DSIM_MVPORCH_CMD_ALLOW_MASK | DSIM_MVPORCH_VBP_MASK |
			DSIM_MVPORCH_STABLE_VFP_MASK;
		dsim_write_mask(id, DSIM_MVPORCH, val, mask);

		val = DSIM_MHPORCH_HFP(lcd->hfp) | DSIM_MHPORCH_HBP(lcd->hbp);
		dsim_write(id, DSIM_MHPORCH, val);

		val = DSIM_MSYNC_VSA(lcd->vsa) | DSIM_MSYNC_HSA(lcd->hsa);
		mask = DSIM_MSYNC_VSA_MASK | DSIM_MSYNC_HSA_MASK;
		dsim_write_mask(id, DSIM_MSYNC, val, mask);
	}

	if (lcd->mic_enabled)
		width = (lcd->xres >> 1) + (lcd->xres % 4);
	else