C++ div_u64_rem函数代码示例

static struct ppa_addr linear_to_generic_addr(struct nvm_dev *dev,
							struct ppa_addr r)
{
	struct ppa_addr l;
	int secs, pgs, blks, luns;
	sector_t ppa = r.ppa;

	l.ppa = 0;

	div_u64_rem(ppa, dev->sec_per_pg, &secs);
	l.g.sec = secs;

	sector_div(ppa, dev->sec_per_pg);
	div_u64_rem(ppa, dev->pgs_per_blk, &pgs);
	l.g.pg = pgs;

	sector_div(ppa, dev->pgs_per_blk);
	div_u64_rem(ppa, dev->blks_per_lun, &blks);
	l.g.blk = blks;

	sector_div(ppa, dev->blks_per_lun);
	div_u64_rem(ppa, dev->luns_per_chnl, &luns);
	l.g.lun = luns;

	sector_div(ppa, dev->luns_per_chnl);
	l.g.ch = ppa;

	return l;
}

unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start,
			 lbaint_t blkcnt)
{
	int dev_num = block_dev->devnum;
	int err = 0;
	u32 start_rem, blkcnt_rem;
	struct mmc *mmc = find_mmc_device(dev_num);
	lbaint_t blk = 0, blk_r = 0;
	int timeout = 1000;

	if (!mmc)
		return -1;

	err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num,
				       block_dev->hwpart);
	if (err < 0)
		return -1;

	/*
	 * We want to see if the requested start or total block count are
	 * unaligned.  We discard the whole numbers and only care about the
	 * remainder.
	 */
	err = div_u64_rem(start, mmc->erase_grp_size, &start_rem);
	err = div_u64_rem(blkcnt, mmc->erase_grp_size, &blkcnt_rem);
	if (start_rem || blkcnt_rem)
		printf("\n\nCaution! Your devices Erase group is 0x%x\n"
		       "The erase range would be change to "
		       "0x" LBAF "~0x" LBAF "\n\n",
		       mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1),
		       ((start + blkcnt + mmc->erase_grp_size)
		       & ~(mmc->erase_grp_size - 1)) - 1);

	while (blk < blkcnt) {
		blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?
			mmc->erase_grp_size : (blkcnt - blk);
		err = mmc_erase_t(mmc, start + blk, blk_r);
		if (err)
			break;

		blk += blk_r;

		/* Waiting for the ready status */
		if (mmc_send_status(mmc, timeout))
			return 0;
	}

	return blk;
}

static inline int sst_calc_tstamp(struct intel_sst_drv *ctx,
		struct pcm_stream_info *info,
		struct snd_pcm_substream *substream,
		struct snd_sst_tstamp *fw_tstamp)
{
	size_t delay_bytes, delay_frames;
	size_t buffer_sz;
	u32 pointer_bytes, pointer_samples;

	dev_dbg(ctx->dev, "mrfld ring_buffer_counter %llu in bytes\n",
			fw_tstamp->ring_buffer_counter);
	dev_dbg(ctx->dev, "mrfld hardware_counter %llu in bytes\n",
			 fw_tstamp->hardware_counter);
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		delay_bytes = (size_t) (fw_tstamp->ring_buffer_counter -
					fw_tstamp->hardware_counter);
	else
		delay_bytes = (size_t) (fw_tstamp->hardware_counter -
					fw_tstamp->ring_buffer_counter);
	delay_frames = bytes_to_frames(substream->runtime, delay_bytes);
	buffer_sz = snd_pcm_lib_buffer_bytes(substream);
	div_u64_rem(fw_tstamp->ring_buffer_counter, buffer_sz, &pointer_bytes);
	pointer_samples = bytes_to_samples(substream->runtime, pointer_bytes);

	dev_dbg(ctx->dev, "pcm delay %zu in bytes\n", delay_bytes);

	info->buffer_ptr = pointer_samples / substream->runtime->channels;

	info->pcm_delay = delay_frames / substream->runtime->channels;
	dev_dbg(ctx->dev, "buffer ptr %llu pcm_delay rep: %llu\n",
			info->buffer_ptr, info->pcm_delay);
	return 0;
}

static ssize_t show_pw20_wait_time(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	u32 value;
	u64 tb_cycle = 1;
	u64 time;

	unsigned int cpu = dev->id;

	if (!pw20_wt) {
		smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
		value = (value & PWRMGTCR0_PW20_ENT) >>
					PWRMGTCR0_PW20_ENT_SHIFT;

		tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
		/* convert ms to ns */
		if (tb_ticks_per_usec > 1000) {
			time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
		} else {
			u32 rem_us;

			time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
						&rem_us);
			time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
		}
	} else {

static void do_test_sync_cmpxchg(void)
{
       int ret;
       unsigned long flags;
       unsigned int i;
       cycles_t time1, time2, time;
       u32 rem;

       local_irq_save(flags);
       preempt_disable();
       time1 = get_cycles();
       for (i = 0; i < NR_LOOPS; i++) {
#ifdef CONFIG_X86_32
       ret = sync_cmpxchg(&test_val, 0, 0);
#else
       ret = cmpxchg(&test_val, 0, 0);
#endif
       }
       time2 = get_cycles();
       local_irq_restore(flags);
       preempt_enable();
       time = time2 - time1;

       printk(KERN_ALERT "test results: time for locked cmpxchg\n");
       printk(KERN_ALERT "number of loops: %d\n", NR_LOOPS);
       printk(KERN_ALERT "total time: %llu\n", time);
       time = div_u64_rem(time, NR_LOOPS, &rem);
       printk(KERN_ALERT "-> locked cmpxchg takes %llu cycles\n", time);
       printk(KERN_ALERT "test end\n");
}

static void do_testbaseline(void)
{
       unsigned long flags;
       unsigned int i;
       cycles_t time1, time2, time;
       u32 rem;

       local_irq_save(flags);
       preempt_disable();
       time1 = get_cycles();
       for (i = 0; i < NR_LOOPS; i++) {
       asm volatile ("");
       }
       time2 = get_cycles();
       local_irq_restore(flags);
       preempt_enable();
       time = time2 - time1;

       printk(KERN_ALERT "test results: time for baseline\n");
       printk(KERN_ALERT "number of loops: %d\n", NR_LOOPS);
       printk(KERN_ALERT "total time: %llu\n", time);
       time = div_u64_rem(time, NR_LOOPS, &rem);
       printk(KERN_ALERT "-> baseline takes %llu cycles\n", time);
       printk(KERN_ALERT "test end\n");
}

static bool bl_map_stripe(struct pnfs_block_dev *dev, u64 offset,
		struct pnfs_block_dev_map *map)
{
	struct pnfs_block_dev *child;
	u64 chunk;
	u32 chunk_idx;
	u64 disk_offset;

	chunk = div_u64(offset, dev->chunk_size);
	div_u64_rem(chunk, dev->nr_children, &chunk_idx);

	if (chunk_idx > dev->nr_children) {
		dprintk("%s: invalid chunk idx %d (%lld/%lld)\n",
			__func__, chunk_idx, offset, dev->chunk_size);
		/* error, should not happen */
		return false;
	}

	/* truncate offset to the beginning of the stripe */
	offset = chunk * dev->chunk_size;

	/* disk offset of the stripe */
	disk_offset = div_u64(offset, dev->nr_children);

	child = &dev->children[chunk_idx];
	child->map(child, disk_offset, map);

	map->start += offset;
	map->disk_offset += disk_offset;
	map->len = dev->chunk_size;
	return true;
}

static void do_test_inc(void)
{
       int ret;
       unsigned long flags;
       unsigned int i;
       cycles_t time1, time2, time;
       u32 rem;
       local_t loc_val;

       local_irq_save(flags);
       preempt_disable();
       time1 = get_cycles();
       for (i = 0; i < NR_LOOPS; i++) {
       ret = local_add_return(10, &loc_val);
       }
       time2 = get_cycles();
       local_irq_restore(flags);
       preempt_enable();
       time = time2 - time1;

       printk(KERN_ALERT "test results: time for non locked add return\n");
       printk(KERN_ALERT "number of loops: %d\n", NR_LOOPS);
       printk(KERN_ALERT "total time: %llu\n", time);
       time = div_u64_rem(time, NR_LOOPS, &rem);
       printk(KERN_ALERT "-> non locked add return takes %llu cycles\n", time);
       printk(KERN_ALERT "test end\n");
}

/**
 * ixgbe_ptp_enable_sdp
 * @hw - the hardware private structure
 * @shift - the clock shift for calculating nanoseconds
 *
 * this function enables the clock out feature on the sdp0 for the
 * X540 device. It will create a 1second periodic output that can be
 * used as the PPS (via an interrupt).
 *
 * It calculates when the systime will be on an exact second, and then
 * aligns the start of the PPS signal to that value. The shift is
 * necessary because it can change based on the link speed.
 */
static void ixgbe_ptp_enable_sdp(struct ixgbe_hw *hw, int shift)
{
	u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh;
	u64 clock_edge = 0;
	u32 rem;

	switch (hw->mac.type) {
	case ixgbe_mac_X540:
		esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);

		/*
		 * enable the SDP0 pin as output, and connected to the native
		 * function for Timesync (ClockOut)
		 */
		esdp |= (IXGBE_ESDP_SDP0_DIR |
			 IXGBE_ESDP_SDP0_NATIVE);

		/*
		 * enable the Clock Out feature on SDP0, and allow interrupts
		 * to occur when the pin changes
		 */
		tsauxc = (IXGBE_TSAUXC_EN_CLK |
			  IXGBE_TSAUXC_SYNCLK |
			  IXGBE_TSAUXC_SDP0_INT);

		/* clock period (or pulse length) */
		clktiml = (u32)(NSECS_PER_SEC << shift);
		clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);

		clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
		clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;

		/*
		 * account for the fact that we can't do u64 division
		 * with remainder, by converting the clock values into
		 * nanoseconds first
		 */
		clock_edge >>= shift;
		div_u64_rem(clock_edge, NSECS_PER_SEC, &rem);
		clock_edge += (NSECS_PER_SEC - rem);
		clock_edge <<= shift;

		/* specify the initial clock start time */
		trgttiml = (u32)clock_edge;
		trgttimh = (u32)(clock_edge >> 32);

		IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
		IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
		IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
		IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);

		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
		IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);

		IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EICR_TIMESYNC);
		break;
	default:
		break;
	}
}

int trace_print_message(char* str, size_t size,
    const void* msg, size_t msg_size, int cpu, u64 ts, void* user_data)
{
    int result, result_total = 0;
    const struct kedr_trace_message* msg_real =
        (const struct kedr_trace_message*)msg;
    // ts is time in nanoseconds since system starts
    u32 sec, ms;
   
    sec = div_u64_rem(ts, 1000000000, &ms);
    ms /= 1000;

    (void)user_data;

#define update_str(str, size, result) \
    if(size <= result) { str += size; size = 0; } \
    else{ str += result; size -= result; }

    result = snprintf(str, size, "%s-%d\t[%.03d]\t%lu.%.06u:\t",
        msg_real->command, msg_real->pid,
        cpu, (unsigned long)sec, (unsigned)ms);
    result_total += result;

    update_str(str, size, result);
    result = msg_real->pp(str,
        size, msg_real->data);
    result_total += result;

    update_str(str, size, result);
    result = snprintf(str, size, "\n");
    result_total += result;
#undef update_str
    return result_total;
}

static void do_test_int(void)
{
       unsigned long flags;
       unsigned int i;
       cycles_t time1, time2, time;
       u32 rem;

       local_irq_save(flags);
       preempt_disable();
       time1 = get_cycles();
       for (i = 0; i < NR_LOOPS; i++) {
       local_irq_restore(flags);
       local_irq_save(flags);
       }
       time2 = get_cycles();
       local_irq_restore(flags);
       preempt_enable();
       time = time2 - time1;

       printk(KERN_ALERT "test results: time for disabling/enabling interrupts (STI/CLI)\n");
       printk(KERN_ALERT "number of loops: %d\n", NR_LOOPS);
       printk(KERN_ALERT "total time: %llu\n", time);
       time = div_u64_rem(time, NR_LOOPS, &rem);
       printk(KERN_ALERT "-> enabling/disabling interrupts (STI/CLI) takes %llu cycles\n",
       time);
       printk(KERN_ALERT "test end\n");
}

s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder)
{
	u64 quotient;

	if (dividend < 0) {
		quotient = div_u64_rem(-dividend, abs(divisor), (u32 *)remainder);
		*remainder = -*remainder;
		if (divisor > 0)
			quotient = -quotient;
	} else {
		quotient = div_u64_rem(dividend, abs(divisor), (u32 *)remainder);
		if (divisor < 0)
			quotient = -quotient;
	}
	return quotient;
}

/**
 * __add_badblock_range() - Convert a physical address range to bad sectors
 * @bb:		badblocks instance to populate
 * @ns_offset:	namespace offset where the error range begins (in bytes)
 * @len:	number of bytes of poison to be added
 *
 * This assumes that the range provided with (ns_offset, len) is within
 * the bounds of physical addresses for this namespace, i.e. lies in the
 * interval [ns_start, ns_start + ns_size)
 */
static void __add_badblock_range(struct badblocks *bb, u64 ns_offset, u64 len)
{
	const unsigned int sector_size = 512;
	sector_t start_sector;
	u64 num_sectors;
	u32 rem;

	start_sector = div_u64(ns_offset, sector_size);
	num_sectors = div_u64_rem(len, sector_size, &rem);
	if (rem)
		num_sectors++;

	if (unlikely(num_sectors > (u64)INT_MAX)) {
		u64 remaining = num_sectors;
		sector_t s = start_sector;

		while (remaining) {
			int done = min_t(u64, remaining, INT_MAX);

			set_badblock(bb, s, done);
			remaining -= done;
			s += done;
		}
	} else
		set_badblock(bb, start_sector, num_sectors);
}

/**
 * stmmac_adjust_time
 *
 * @ptp: pointer to ptp_clock_info structure
 * @delta: desired change in nanoseconds
 *
 * Description: this function will shift/adjust the hardware clock time.
 */
static int stmmac_adjust_time(struct ptp_clock_info *ptp, s64 delta)
{
	struct stmmac_priv *priv =
	    container_of(ptp, struct stmmac_priv, ptp_clock_ops);
	unsigned long flags;
	u32 sec, nsec;
	u32 quotient, reminder;
	int neg_adj = 0;

	if (delta < 0) {
		neg_adj = 1;
		delta = -delta;
	}

	quotient = div_u64_rem(delta, 1000000000ULL, &reminder);
	sec = quotient;
	nsec = reminder;

	spin_lock_irqsave(&priv->ptp_lock, flags);

	priv->hw->ptp->adjust_systime(priv->ptpaddr, sec, nsec, neg_adj,
				      priv->plat->has_gmac4);

	spin_unlock_irqrestore(&priv->ptp_lock, flags);

	return 0;
}

/**
 * ixgbe_ptp_setup_sdp
 * @hw: the hardware private structure
 *
 * this function enables or disables the clock out feature on SDP0 for
 * the X540 device. It will create a 1second periodic output that can
 * be used as the PPS (via an interrupt).
 *
 * It calculates when the systime will be on an exact second, and then
 * aligns the start of the PPS signal to that value. The shift is
 * necessary because it can change based on the link speed.
 */
static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
{
	struct ixgbe_hw *hw = &adapter->hw;
	int shift = adapter->hw_cc.shift;
	u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
	u64 ns = 0, clock_edge = 0;

	if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
	    (hw->mac.type == ixgbe_mac_X540)) {

		/* disable the pin first */
		IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
		IXGBE_WRITE_FLUSH(hw);

		esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);

		/*
		 * enable the SDP0 pin as output, and connected to the
		 * native function for Timesync (ClockOut)
		 */
		esdp |= (IXGBE_ESDP_SDP0_DIR |
			 IXGBE_ESDP_SDP0_NATIVE);

		/*
		 * enable the Clock Out feature on SDP0, and allow
		 * interrupts to occur when the pin changes
		 */
		tsauxc = (IXGBE_TSAUXC_EN_CLK |
			  IXGBE_TSAUXC_SYNCLK |
			  IXGBE_TSAUXC_SDP0_INT);

		/* clock period (or pulse length) */
		clktiml = (u32)(NSECS_PER_SEC << shift);
		clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);

		/*
		 * Account for the cyclecounter wrap-around value by
		 * using the converted ns value of the current time to
		 * check for when the next aligned second would occur.
		 */
		clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
		clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
		ns = timecounter_cyc2time(&adapter->hw_tc, clock_edge);

		div_u64_rem(ns, NSECS_PER_SEC, &rem);
		clock_edge += ((NSECS_PER_SEC - (u64)rem) << shift);

		/* specify the initial clock start time */
		trgttiml = (u32)clock_edge;
		trgttimh = (u32)(clock_edge >> 32);

		IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
		IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
		IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
		IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);

		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
		IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
		IXGBE_WRITE_FLUSH(hw);
	} else {