C++ cyg_drv_interrupt_unmask函数代码示例

//
// Fill in the details of a PCMCIA slot and initialize the device
//
void
cf_hwr_init(struct cf_slot *slot)
{
    static int int_init = 0;
    unsigned long new_state = *SA11X0_GPIO_PIN_LEVEL;
    if (!int_init) {
        int_init = 1;
#ifdef CYGPKG_KERNEL
        // Set up interrupts
        cyg_drv_interrupt_create(SA1110_CF_DETECT,
                                 99,                     // Priority - what goes here?
                                 (cyg_addrword_t) slot,  //  Data item passed to interrupt handler
                                 (cyg_ISR_t *)cf_detect_isr,
                                 (cyg_DSR_t *)cf_detect_dsr,
                                 &cf_detect_interrupt_handle,
                                 &cf_detect_interrupt);
        cyg_drv_interrupt_attach(cf_detect_interrupt_handle);
        cyg_drv_interrupt_configure(SA1110_CF_DETECT, true, true);  // Detect either edge
        cyg_drv_interrupt_acknowledge(SA1110_CF_DETECT);
        cyg_drv_interrupt_unmask(SA1110_CF_DETECT);
        cyg_drv_interrupt_create(SA1110_CF_IRQ,
                                 99,                     // Priority - what goes here?
                                 (cyg_addrword_t) slot,  //  Data item passed to interrupt handler
                                 (cyg_ISR_t *)cf_irq_isr,
                                 (cyg_DSR_t *)cf_irq_dsr,
                                 &cf_irq_interrupt_handle,
                                 &cf_irq_interrupt);
        cyg_drv_interrupt_attach(cf_irq_interrupt_handle);
        cyg_drv_interrupt_unmask(SA1110_CF_IRQ);
#endif
        cyg_drv_interrupt_configure(SA1110_CF_IRQ, false, false);  // Falling edge
        cyg_drv_interrupt_acknowledge(SA1110_CF_IRQ);
    }
    slot->attr = (unsigned char *)0x38000000;
    slot->attr_length = 0x200;
    slot->io = (unsigned char *)0x30000000;
    slot->io_length = 0x04000000;
    slot->mem = (unsigned char *)0x3C000000;
    slot->mem_length = 0x04000000;
    slot->int_num = SA1110_CF_IRQ;
#ifdef CYG_HAL_STARTUP_ROM
    // Disable CF bus & power (idle/off)
    assabet_BCR(SA1110_BCR_CF_POWER |
                SA1110_BCR_CF_RESET |
                SA1110_BCR_CF_BUS,
                SA1110_BCR_CF_POWER_OFF |
                SA1110_BCR_CF_RESET_DISABLE |
                SA1110_BCR_CF_BUS_OFF);
#endif
    if ((new_state & SA1110_GPIO_CF_DETECT) == SA1110_GPIO_CF_PRESENT) {
        if ((_assabet_BCR & SA1110_BCR_CF_POWER) == SA1110_BCR_CF_POWER_ON) {
            // Assume that the ROM environment has turned the bus on
            slot->state = CF_SLOT_STATE_Ready;
        } else {
            slot->state = CF_SLOT_STATE_Inserted;
        }
    } else {
        slot->state = CF_SLOT_STATE_Empty;
    }
}

// Function to initialize the device.  Called at bootstrap time.
static bool 
vrc437x_serial_init(struct cyg_devtab_entry *tab)
{
    serial_channel *chan = (serial_channel *)tab->priv;
    vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv;
    static bool init = false;
#ifdef CYGDBG_IO_INIT
    diag_printf("VRC437X SERIAL init '%s' - dev: %x\n", tab->name, vrc437x_chan->base);
#endif
    (chan->callbacks->serial_init)(chan);  // Really only required for interrupt driven devices
    if (!init && chan->out_cbuf.len != 0) {
        init = true;
// Note that the hardware is rather broken.  The interrupt status needs to
// be read using only channel A
        cyg_drv_interrupt_create(VRC437X_SCC_INT,
                                 99,                     
                                 (cyg_addrword_t)VRC437X_SCC_BASE+SCC_CHANNEL_A,
                                 vrc437x_serial_ISR,
                                 vrc437x_serial_DSR,
                                 &vrc437x_serial_interrupt_handle,
                                 &vrc437x_serial_interrupt);
        cyg_drv_interrupt_attach(vrc437x_serial_interrupt_handle);
        cyg_drv_interrupt_unmask(VRC437X_SCC_INT);
    }
    vrc437x_serial_config_port(chan, &chan->config, true);
    return true;
}

static void
aeb_setup_timer1(cyg_uint32 period)
{
    cyg_uint32 iocr;

    // Set counter GATE input low (0) to halt counter while it's being setup
    HAL_READ_UINT32(CYG_DEVICE_IOCR, iocr);
    iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_LOW;
    HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr);

    // Scale timer0 clock
    HAL_WRITE_UINT32(CYG_DEVICE_CPM_CT1CCR, CT_X16);

    // Initialize counter, mode 2 = rate generator
    HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL, 
                    TIMER_CTL_TYPE_BIN|
                    TIMER_CTL_MODE_RG|
                    TIMER_CTL_RW_BOTH|
                    TIMER_CTL_SC_CTR1);
    HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, (period & 0xFF));        // LSB
    HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, ((period >> 8) & 0xFF)); // MSB
    // Enable timer
    iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_HIGH;
    HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr);
    cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_TIMER1,
                             99,             // Priority
                             0,              // Data item passed to interrupt handler
                             aeb_timer1_isr,
                             0,
                             &timer1_interrupt_handle,
                             &timer1_interrupt);
    cyg_drv_interrupt_attach(timer1_interrupt_handle);
    cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_TIMER1);
}

// Serial I/O - high level interrupt handler (DSR)
static void       
smdk2410_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
    serial_channel *chan = (serial_channel *)data;
    smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv;
    CYG_ADDRWORD base = smdk2410_chan->base;
    cyg_uint32 _intsubpnd, _status, _c;
    cyg_uint32 _rxd_bit = (smdk2410_chan->bit_sub_rxd<<0), _txd_bit=(smdk2410_chan->bit_sub_rxd<<1);

    HAL_READ_UINT32(SUBSRCPND, _intsubpnd);

    // Empty Rx FIFO
    if (_intsubpnd & _rxd_bit) {
        HAL_READ_UINT32(base+OFS_UFSTAT, _status);
        while((_status & 0x0f) != 0) {
            HAL_READ_UINT8(base+OFS_URXH, _c);
            (chan->callbacks->rcv_char)(chan, (unsigned char)_c);
            HAL_READ_UINT32(base+OFS_UFSTAT, _status);
        }
        HAL_WRITE_UINT32(SUBSRCPND, _rxd_bit);
    }

    // Fill into Tx FIFO. xmt_char will mask the interrupt when it
    // runs out of chars, so doing this in a loop is OK.
    if (_intsubpnd & _txd_bit) {
        (chan->callbacks->xmt_char)(chan);
        HAL_WRITE_UINT32(SUBSRCPND, _txd_bit);
    }

    cyg_drv_interrupt_unmask(smdk2410_chan->int_num);
}

// Serial I/O - high level interrupt handler (DSR)
static void
aaed2000_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
    serial_channel *chan = (serial_channel *)data;
    aaed2000_serial_info *aaed2000_chan = (aaed2000_serial_info *)chan->dev_priv;
    CYG_ADDRWORD base = aaed2000_chan->base;
    cyg_uint32 _intres, _c;

    HAL_READ_UINT32(base+AAEC_UART_INTRES, _intres);
    _intres &= (AAEC_UART_INT_TIS | AAEC_UART_INT_RIS | AAEC_UART_INT_RTIS);
    while (_intres) {

        // Empty Rx FIFO
        if (_intres & (AAEC_UART_INT_RIS|AAEC_UART_INT_RTIS)) {
            HAL_READ_UINT32(base+AAEC_UART_DATA, _c);
            (chan->callbacks->rcv_char)(chan, (unsigned char)_c);
        }

        // Fill into Tx FIFO. xmt_char will mask the interrupt when it
        // runs out of chars, so doing this in a loop is OK.
        if (_intres & AAEC_UART_INT_TIS) {
            (chan->callbacks->xmt_char)(chan);
        }

        HAL_READ_UINT32(base+AAEC_UART_INTRES, _intres);
        _intres &= (AAEC_UART_INT_TIS | AAEC_UART_INT_RIS | AAEC_UART_INT_RTIS);
    }

    cyg_drv_interrupt_unmask(aaed2000_chan->int_num);
}

static void phy_dsr(cyg_vector_t vector, cyg_ucount32 count,
		cyg_addrword_t data)
{
	cyg_uint32 status;
	struct eth_drv_sc *sc = (struct eth_drv_sc *) data;
	cyg_uint32 address =
			((struct tsec_eth_info *) sc->driver_private)->phyAddress;
//	os_printf("PHY DSR");
	status = phy_read_register(address, MII_PHY_IRQ_REG);
	if (status & (MII_PHY_IRQ_LINK_CHANGE| MII_PHY_IRQ_DUPLEX_CHANGE
			| MII_PHY_IRQ_SPEED_CHANGE))
	{
		int esa_ok = 0;
		(sc->funs->stop)(sc);
	    // Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
	    esa_ok = flash_get_config("tsec_esa", enaddr, CONFIG_ESA);
#else
		esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
				"tsec_esa", enaddr, CONFIG_ESA);
#endif
		if (!esa_ok)
		{
			// Can't figure out ESA
			os_printf("TSEC_ETH - Warning! ESA unknown\n");
			memcpy(&enaddr, &_default_enaddr, sizeof(enaddr));
		}

		(sc->funs->start)(sc, (unsigned char *) enaddr, 1);
	}
	cyg_drv_interrupt_unmask(vector);
}

// Function to initialize the device.  Called at bootstrap time.
static bool 
edb7xxx_serial_init(struct cyg_devtab_entry *tab)
{
    serial_channel *chan = (serial_channel *)tab->priv;
    edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv;
#ifdef CYGDBG_IO_INIT
    diag_printf("EDB7XXX SERIAL init - dev: %x.%d\n", edb7xxx_chan->control, edb7xxx_chan->tx_int_num);
#endif
    (chan->callbacks->serial_init)(chan);  // Really only required for interrupt driven devices
    if (chan->out_cbuf.len != 0) {
        cyg_drv_interrupt_create(edb7xxx_chan->tx_int_num,
                                 99,                     // Priority - unused
                                 (cyg_addrword_t)chan,   //  Data item passed to interrupt handler
                                 edb7xxx_serial_tx_ISR,
                                 edb7xxx_serial_tx_DSR,
                                 &edb7xxx_chan->serial_tx_interrupt_handle,
                                 &edb7xxx_chan->serial_tx_interrupt);
        cyg_drv_interrupt_attach(edb7xxx_chan->serial_tx_interrupt_handle);
        cyg_drv_interrupt_mask(edb7xxx_chan->tx_int_num);
        edb7xxx_chan->tx_enabled = false;
    }
    if (chan->in_cbuf.len != 0) {
        cyg_drv_interrupt_create(edb7xxx_chan->rx_int_num,
                                 99,                     // Priority - unused
                                 (cyg_addrword_t)chan,   //  Data item passed to interrupt handler
                                 edb7xxx_serial_rx_ISR,
                                 edb7xxx_serial_rx_DSR,
                                 &edb7xxx_chan->serial_rx_interrupt_handle,
                                 &edb7xxx_chan->serial_rx_interrupt);
        cyg_drv_interrupt_attach(edb7xxx_chan->serial_rx_interrupt_handle);
        cyg_drv_interrupt_unmask(edb7xxx_chan->rx_int_num);
    }
    edb7xxx_serial_config_port(chan, &chan->config, true);
    return true;
}

// Serial I/O - high level interrupt handler (DSR)
static void zynq_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
    serial_channel *chan = (serial_channel *)data;
    zynq_serial_info *zynq_chan = (zynq_serial_info *)chan->dev_priv;
    volatile cyg_uint32 isr;
    cyg_uint32 status, temp;
    unsigned char c;

    HAL_READ_UINT32(zynq_chan->base + XUARTPS_CHNL_INT_STS, isr);

    if (isr & XUARTPS_CHNL_INT_STS_TEMPTY)
		(chan->callbacks->xmt_char)(chan);

    if ((isr & XUARTPS_CHNL_INT_STS_RTRIG) || (isr & XUARTPS_CHNL_INT_STS_RTOUT)) // Data in the RxFiFo
    {
        HAL_READ_UINT32(zynq_chan->base + XUARTPS_CHANNEL_STS, status);
        while( !(status & XUARTPS_CHANNEL_STS_REMPTY) )
        {
            HAL_READ_UINT32(zynq_chan->base + XUARTPS_TX_RX_FIFO, temp);
            c = (unsigned char)(temp & 0xff);
            (chan->callbacks->rcv_char)(chan, c);
            HAL_READ_UINT32(zynq_chan->base + XUARTPS_CHANNEL_STS, status);
        }
        
    }
    
    // clear
    HAL_WRITE_UINT32(zynq_chan->base + XUARTPS_CHNL_INT_STS, isr);
    cyg_drv_interrupt_unmask(zynq_chan->int_num);
}

void
kbd_init(void)
{
    // Initialize environment, setup interrupt handler
    cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_KBDINT,
                             99,                     // Priority - what goes here?
                             0,                      //  Data item passed to interrupt handler
                             (cyg_ISR_t *)keyboard_isr,
                             (cyg_DSR_t *)keyboard_dsr,
                             &kbd_interrupt_handle,
                             &kbd_interrupt);
    cyg_drv_interrupt_attach(kbd_interrupt_handle);
    cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_KBDINT);
    cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_KBDINT);
    // Set up the mbox for keyboard data
    cyg_mbox_create(&kbd_events_mbox_handle, &kbd_events_mbox);
    // This semaphore is set when there is a keypress
    cyg_semaphore_init(&kbd_sem, 0);  
    // Create a thread whose job it is to de-bounce the keyboard and
    // actually process the input, turning it into a series of events
    cyg_thread_create(10,                           // Priority - just a number
                      kbd_server,                   // entry
                      0,                            // initial parameter
                      "KBD_server",                 // Name
                      &kbd_server_stack[0],         // Stack
                      STACK_SIZE,                   // Size
                      &kbd_server_thread_handle,    // Handle
                      &kbd_server_thread_data       // Thread data structure
            );
    cyg_thread_resume(kbd_server_thread_handle);  // Start it
}

//==========================================================================
// This function is called from the generic ADC package to enable the
// channel in response to a CYG_IO_SET_CONFIG_ADC_ENABLE config operation.
// It should take any steps needed to start the channel generating samples
//==========================================================================
static void at91_adc_enable(cyg_adc_channel *chan)
{
    at91_adc_info *info      = chan->device->dev_priv;

    // Enable the channel
    HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CHER), \
                      AT91_ADC_CHER_CHx(chan->channel));

    //
    // Unmask interrupt as soon as 1 channel is enable
    //
    if (!info->chan_mask)
    {
       cyg_drv_interrupt_unmask(info->timer_vector);

       // Enable timer interrupt
       HAL_WRITE_UINT32(info->tc_base+AT91_TC_IER, AT91_TC_IER_CPC);

       // Enable the clock
       HAL_WRITE_UINT32(info->tc_base+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);

       // Start timer
       HAL_WRITE_UINT32(info->tc_base+AT91_TC_CCR,  AT91_TC_CCR_TRIG);

       // Start ADC sampling
       HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CR), AT91_ADC_CR_START);

    }

    info->chan_mask |= AT91_ADC_CHER_CHx(chan->channel);

}

// Enable the transmitter on the device (nope, already in use by hal_diag)
static void
ebsa285_serial_start_xmit(serial_channel *chan)
{
    ebsa285_serial_info *ebsa285_chan = (ebsa285_serial_info *)chan->dev_priv;
    ebsa285_chan->tx_active = 1;
    cyg_drv_interrupt_unmask(ebsa285_chan->tx.int_num);
}

void hal_clock_initialize(cyg_uint32 period)
{
    cyg_uint32 tmod;

    // Disable timer 0
    HAL_READ_UINT32(E7T_TMOD, tmod);
    tmod &= ~(E7T_TMOD_TE0);
    HAL_WRITE_UINT32(E7T_TMOD, 0);

    tmod &= ~(E7T_TMOD_TMD0 | E7T_TMOD_TCLR0);
    tmod |= E7T_TMOD_TE0;

    // Set counter
    HAL_WRITE_UINT32(E7T_TDATA0, period);

    // And enable timer
    HAL_WRITE_UINT32(E7T_TMOD, tmod);

    _period = period;

#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
    cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_EXT0,
                             99,           // Priority
                             0,            // Data item passed to interrupt handler
                             e7t_abort_isr,
                             0,
                             &abort_interrupt_handle,
                             &abort_interrupt);
    cyg_drv_interrupt_attach(abort_interrupt_handle);
    cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT0);
#endif
}

static void
mpc8xxx_scc_serial_DSR(serial_channel *chan)
{
    mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv;
    volatile struct scc_regs_8260 *ctl = (volatile struct scc_regs_8260 *)smc_chan->ctl;
    volatile struct cp_bufdesc *txbd;
    volatile struct cp_bufdesc *rxbd = smc_chan->rxbd;
    volatile t_Smc_Pram *pram = (volatile t_Smc_Pram *)smc_chan->pram;
    struct cp_bufdesc *rxlast;
    int i, cache_state;

    if (ctl->scce & SCCE_Tx) {
        // Transmit interrupt
        ctl->scce = SCCE_Tx;  // Reset interrupt state;
        txbd = smc_chan->tbase;  // First buffer
        while (true) {
            if ((txbd->ctrl & (_BD_CTL_Ready|_BD_CTL_Int)) == _BD_CTL_Int) {
                txbd->length = 0;
                txbd->ctrl &= ~_BD_CTL_Int;  // Reset interrupt bit
            }
            if (txbd->ctrl & _BD_CTL_Wrap) {
                txbd = smc_chan->tbase;
                break;
            } else {
                txbd++;
            }
        }
        (chan->callbacks->xmt_char)(chan);
    }
    while (ctl->scce & SCCE_Rx) {
        // Receive interrupt
        ctl->scce = SCCE_Rx;  // Reset interrupt state;
        rxlast = (struct cp_bufdesc *) ((char *)IMM + pram->rbptr);
        while (rxbd != rxlast) {
            if ((rxbd->ctrl & _BD_CTL_Ready) == 0) {
                for (i = 0;  i < rxbd->length;  i++) {
                    (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]);
                }
                // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
                HAL_DCACHE_IS_ENABLED(cache_state);
                if (cache_state) {
                    HAL_DCACHE_INVALIDATE(rxbd->buffer, smc_chan->rxsize);  // Make sure no stale data
                }
                rxbd->length = 0;
                rxbd->ctrl |= _BD_CTL_Ready;
            }
            if (rxbd->ctrl & _BD_CTL_Wrap) {
                rxbd = smc_chan->rbase;
            } else {
                rxbd++;
            }
        }
        smc_chan->rxbd = (struct cp_bufdesc *)rxbd;
    }
    if (ctl->scce & SCCE_Bsy) {
        ctl->scce = SCCE_Bsy;  // Reset interrupt state;
    }
    cyg_drv_interrupt_acknowledge(smc_chan->int_num);
    cyg_drv_interrupt_unmask(smc_chan->int_num);
}

// Enable the transmitter (interrupt) on the device
static void
edb7xxx_serial_start_xmit(serial_channel *chan)
{
    edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv;
    edb7xxx_chan->tx_enabled = true;
    cyg_drv_interrupt_unmask(edb7xxx_chan->tx_int_num);
}

__externC CYG_WORD32 cyg_hal_cpu_message_dsr(CYG_WORD32 vector, CYG_ADDRWORD data) {

    struct smp_msg_t *m = &smp_msg[HAL_SMP_CPU_THIS()];
    CYG_WORD32 reschedule;

#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE
    CYG_WORD32 timeslice;
#endif

    cyg_drv_interrupt_mask(vector);
    HAL_SPINLOCK_SPIN(m->lock);

    reschedule = m->reschedule;
#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE
    timeslice = m->timeslice;
    m->reschedule = m->timeslice = false;
#else
    m->reschedule = false;
#endif

    HAL_SPINLOCK_CLEAR(m->lock);
    cyg_drv_interrupt_unmask(vector);

    if (reschedule) {
        cyg_scheduler_set_need_reschedule();
    }
#ifdef CYGSEM_KERNEL_SCHED_TIMESLICE
    if (timeslice) {
        cyg_scheduler_timeslice_cpu();
    }
#endif

    return 0;
}