C++ cx_read函数代码示例

int cx25821_start_video_dma(struct cx25821_dev *dev,
			    struct cx25821_dmaqueue *q,
			    struct cx25821_buffer *buf,
			    const struct sram_channel *channel)
{
	int tmp = 0;

	/* setup fifo + format */
	cx25821_sram_channel_setup(dev, channel, buf->bpl, buf->risc.dma);

	/* reset counter */
	cx_write(channel->gpcnt_ctl, 3);

	/* enable irq */
	cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << channel->i));
	cx_set(channel->int_msk, 0x11);

	/* start dma */
	cx_write(channel->dma_ctl, 0x11);	/* FIFO and RISC enable */

	/* make sure upstream setting if any is reversed */
	tmp = cx_read(VID_CH_MODE_SEL);
	cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);

	return 0;
}

static irqreturn_t cx25821_upstream_irq_audio(int irq, void *dev_id)
{
	struct cx25821_dev *dev = dev_id;
	u32 msk_stat, audio_status;
	int handled = 0;
	struct sram_channel *sram_ch;

	if (!dev)
		return -1;

	sram_ch = &dev->sram_channels[dev->_audio_upstream_channel_select];

	msk_stat = cx_read(sram_ch->int_mstat);
	audio_status = cx_read(sram_ch->int_stat);

	// Only deal with our interrupt
	if (audio_status) {
		handled =
		    cx25821_audio_upstream_irq(dev,
					       dev->
					       _audio_upstream_channel_select,
					       audio_status);
	}

	if (handled < 0) {
		cx25821_stop_upstream_audio(dev);
	} else {
		handled += handled;
	}

	return IRQ_RETVAL(handled);
}

int cx25821_start_audio_dma_upstream(struct cx25821_dev *dev,
				     struct sram_channel *sram_ch)
{
	u32 tmp = 0;
	int err = 0;

	// Set the physical start address of the RISC program in the initial program counter(IPC) member of the CMDS.
	cx_write(sram_ch->cmds_start + 0, dev->_risc_phys_addr);
	cx_write(sram_ch->cmds_start + 4, 0);	/* Risc IPC High 64 bits 63-32 */

	/* reset counter */
	cx_write(sram_ch->gpcnt_ctl, 3);

	//Set the line length       (It looks like we do not need to set the line length)
	cx_write(sram_ch->aud_length, AUDIO_LINE_SIZE & FLD_AUD_DST_LN_LNGTH);

	//Set the input mode to 16-bit
	tmp = cx_read(sram_ch->aud_cfg);
	tmp |=
	    FLD_AUD_SRC_ENABLE | FLD_AUD_DST_PK_MODE | FLD_AUD_CLK_ENABLE |
	    FLD_AUD_MASTER_MODE | FLD_AUD_CLK_SELECT_PLL_D | FLD_AUD_SONY_MODE;
	cx_write(sram_ch->aud_cfg, tmp);

	// Read and write back the interrupt status register to clear it
	tmp = cx_read(sram_ch->int_stat);
	cx_write(sram_ch->int_stat, tmp);

	// Clear our bits from the interrupt status register.
	cx_write(sram_ch->int_stat, _intr_msk);

	//Set the interrupt mask register, enable irq.
	cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
	tmp = cx_read(sram_ch->int_msk);
	cx_write(sram_ch->int_msk, tmp |= _intr_msk);

	err =
	    request_irq(dev->pci->irq, cx25821_upstream_irq_audio,
			IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
	if (err < 0) {
		printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
		       dev->pci->irq);
		goto fail_irq;
	}

	// Start the DMA  engine
	tmp = cx_read(sram_ch->dma_ctl);
	cx_set(sram_ch->dma_ctl, tmp | sram_ch->fld_aud_risc_en);

	dev->_audio_is_running = 1;
	dev->_is_first_audio_frame = 1;

	// The fifo_en bit turns on by the first Risc program
	cx25821_wait_fifo_enable(dev, sram_ch);

	return 0;

      fail_irq:
	cx25821_dev_unregister(dev);
	return err;
}

static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
{
	struct cx25821_dev *dev = dev_id;
	u32 msk_stat, vid_status;
	int handled = 0;
	int channel_num = 0;
	struct sram_channel *sram_ch;

	if (!dev)
		return -1;

	channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
	sram_ch = dev->channels[channel_num].sram_channels;

	msk_stat = cx_read(sram_ch->int_mstat);
	vid_status = cx_read(sram_ch->int_stat);

	/* Only deal with our interrupt */
	if (vid_status)
		handled = cx25821_video_upstream_irq_ch2(dev, channel_num,
				vid_status);

	if (handled < 0)
		cx25821_stop_upstream_video_ch2(dev);
	else
		handled += handled;

	return IRQ_RETVAL(handled);
}

static int cx25821_start_video_dma_upstream(struct cx25821_channel *chan,
					    const struct sram_channel *sram_ch)
{
	struct cx25821_video_out_data *out = chan->out;
	struct cx25821_dev *dev = chan->dev;
	u32 tmp = 0;
	int err = 0;

	/* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
	 * channel A-C
	 */
	tmp = cx_read(VID_CH_MODE_SEL);
	cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);

	/* Set the physical start address of the RISC program in the initial
	 * program counter(IPC) member of the cmds.
	 */
	cx_write(sram_ch->cmds_start + 0, out->_dma_phys_addr);
	/* Risc IPC High 64 bits 63-32 */
	cx_write(sram_ch->cmds_start + 4, 0);

	/* reset counter */
	cx_write(sram_ch->gpcnt_ctl, 3);

	/* Clear our bits from the interrupt status register. */
	cx_write(sram_ch->int_stat, _intr_msk);

	/* Set the interrupt mask register, enable irq. */
	cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
	tmp = cx_read(sram_ch->int_msk);
	cx_write(sram_ch->int_msk, tmp |= _intr_msk);

	err = request_irq(dev->pci->irq, cx25821_upstream_irq,
			IRQF_SHARED, dev->name, chan);
	if (err < 0) {
		pr_err("%s: can't get upstream IRQ %d\n",
		       dev->name, dev->pci->irq);
		goto fail_irq;
	}

	/* Start the DMA  engine */
	tmp = cx_read(sram_ch->dma_ctl);
	cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);

	out->_is_running = 1;
	out->_is_first_frame = 1;

	return 0;

fail_irq:
	cx25821_dev_unregister(dev);
	return err;
}

s32 cx88_dsp_detect_stereo_sap(struct cx88_core *core)
{
	s16 *samples;
	u32 N = 0;
	s32 ret = UNSET;

	/* If audio RDS fifo is disabled, we can't read the samples */
	if (!(cx_read(MO_AUD_DMACNTRL) & 0x04))
		return ret;
	if (!(cx_read(AUD_CTL) & EN_FMRADIO_EN_RDS))
		return ret;

	/* Wait at least 500 ms after an audio standard change */
	if (time_before(jiffies, core->last_change + msecs_to_jiffies(500)))
		return ret;

	samples = read_rds_samples(core, &N);

	if (!samples)
		return ret;

	switch (core->tvaudio) {
	case WW_BG:
	case WW_DK:
	case WW_EIAJ:
	case WW_M:
		ret = detect_a2_a2m_eiaj(core, samples, N);
		break;
	case WW_BTSC:
		ret = detect_btsc(core, samples, N);
		break;
	case WW_NONE:
	case WW_I:
	case WW_L:
	case WW_I2SPT:
	case WW_FM:
	case WW_I2SADC:
		break;
	}

	kfree(samples);

	if (UNSET != ret)
		dprintk(1, "stereo/sap detection result:%s%s%s\n",
			   (ret & V4L2_TUNER_SUB_MONO) ? " mono" : "",
			   (ret & V4L2_TUNER_SUB_STEREO) ? " stereo" : "",
			   (ret & V4L2_TUNER_SUB_LANG2) ? " dual" : "");

	return ret;
}

void cx25821_stop_upstream_audio(struct cx25821_dev *dev)
{
	struct sram_channel *sram_ch =
		dev->channels[AUDIO_UPSTREAM_SRAM_CHANNEL_B].sram_channels;
	u32 tmp = 0;

	if (!dev->_audio_is_running) {
		printk(KERN_DEBUG
		       pr_fmt("No audio file is currently running so return!\n"));
		return;
	}
	/* Disable RISC interrupts */
	cx_write(sram_ch->int_msk, 0);

	/* Turn OFF risc and fifo enable in AUD_DMA_CNTRL */
	tmp = cx_read(sram_ch->dma_ctl);
	cx_write(sram_ch->dma_ctl,
		 tmp & ~(sram_ch->fld_aud_fifo_en | sram_ch->fld_aud_risc_en));

	/* Clear data buffer memory */
	if (dev->_audiodata_buf_virt_addr)
		memset(dev->_audiodata_buf_virt_addr, 0,
		       dev->_audiodata_buf_size);

	dev->_audio_is_running = 0;
	dev->_is_first_audio_frame = 0;
	dev->_audioframe_count = 0;
	dev->_audiofile_status = END_OF_FILE;

	kfree(dev->_irq_audio_queues);
	dev->_irq_audio_queues = NULL;

	kfree(dev->_audiofilename);
}

static int i2c_readbytes(struct i2c_adapter *i2c_adap,
                         const struct i2c_msg *msg, int joined)
{
    struct cx23885_i2c *bus = i2c_adap->algo_data;
    struct cx23885_dev *dev = bus->dev;
    u32 ctrl, cnt;
    int retval;


    if (i2c_debug && !joined)
        dprintk(1, "%s(msg->len=%d)\n", __func__, msg->len);

    /* Deal with i2c probe functions with zero payload */
    if (msg->len == 0) {
        cx_write(bus->reg_addr, msg->addr << 25);
        cx_write(bus->reg_ctrl, bus->i2c_period | (1 << 2) | 1);
        if (!i2c_wait_done(i2c_adap))
            return -EIO;
        if (!i2c_slave_did_ack(i2c_adap))
            return -ENXIO;


        dprintk(1, "%s() returns 0\n", __func__);
        return 0;
    }

    if (i2c_debug) {
        if (joined)
            dprintk(1, " R");
        else
            dprintk(1, " <R %02x", (msg->addr << 1) + 1);
    }

    for (cnt = 0; cnt < msg->len; cnt++) {

        ctrl = bus->i2c_period | (1 << 12) | (1 << 2) | 1;

        if (cnt < msg->len - 1)
            ctrl |= I2C_NOSTOP | I2C_EXTEND;

        cx_write(bus->reg_addr, msg->addr << 25);
        cx_write(bus->reg_ctrl, ctrl);

        if (!i2c_wait_done(i2c_adap))
            goto eio;
        msg->buf[cnt] = cx_read(bus->reg_rdata) & 0xff;
        if (i2c_debug) {
            dprintk(1, " %02x", msg->buf[cnt]);
            if (!(ctrl & I2C_NOSTOP))
                dprintk(1, " >\n");
        }
    }
    return msg->len;

eio:
    retval = -EIO;
    if (i2c_debug)
        pr_err(" ERR: %d\n", retval);
    return retval;
}

/********************* GPIO stuffs *********************/
void cx25821_set_gpiopin_direction(struct cx25821_dev *dev,
				   int pin_number, int pin_logic_value)
{
	int bit = pin_number;
	u32 gpio_oe_reg = GPIO_LO_OE;
	u32 gpio_register = 0;
	u32 value = 0;

	/* Check for valid pinNumber */
	if (pin_number >= 47)
		return;

	if (pin_number > 31) {
		bit = pin_number - 31;
		gpio_oe_reg = GPIO_HI_OE;
	}
	/* Here we will make sure that the GPIOs 0 and 1 are output. keep the
	 * rest as is */
	gpio_register = cx_read(gpio_oe_reg);

	if (pin_logic_value == 1)
		value = gpio_register | Set_GPIO_Bit(bit);
	else
		value = gpio_register & Clear_GPIO_Bit(bit);

	cx_write(gpio_oe_reg, value);
}

static void cx25821_set_gpiopin_logicvalue(struct cx25821_dev *dev,
					   int pin_number, int pin_logic_value)
{
	int bit = pin_number;
	u32 gpio_reg = GPIO_LO;
	u32 value = 0;

	/* Check for valid pinNumber */
	if (pin_number >= 47)
		return;

	/* change to output direction */
	cx25821_set_gpiopin_direction(dev, pin_number, 0);

	if (pin_number > 31) {
		bit = pin_number - 31;
		gpio_reg = GPIO_HI;
	}

	value = cx_read(gpio_reg);

	if (pin_logic_value == 0)
		value &= Clear_GPIO_Bit(bit);
	else
		value |= Set_GPIO_Bit(bit);

	cx_write(gpio_reg, value);
}

static irqreturn_t cx25821_upstream_irq_audio(int irq, void *dev_id)
{
	struct cx25821_dev *dev = dev_id;
	u32 audio_status;
	int handled = 0;
	struct sram_channel *sram_ch;

	if (!dev)
		return -1;

	sram_ch = dev->channels[dev->_audio_upstream_channel].sram_channels;

	audio_status = cx_read(sram_ch->int_stat);

	/* Only deal with our interrupt */
	if (audio_status) {
		handled = cx25821_audio_upstream_irq(dev,
				dev->_audio_upstream_channel, audio_status);
	}

	if (handled < 0)
		cx25821_stop_upstream_audio(dev);
	else
		handled += handled;

	return IRQ_RETVAL(handled);
}

/*
 * BOARD Specific: Handles audio IRQ
 */
int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask)
{
	struct cx23885_audio_dev *chip = dev->audio_dev;

	if (0 == (status & mask))
		return 0;

	cx_write(AUDIO_INT_INT_STAT, status);

	/* risc op code error */
	if (status & AUD_INT_OPC_ERR) {
		printk(KERN_WARNING "%s/1: Audio risc op code error\n",
			dev->name);
		cx_clear(AUD_INT_DMA_CTL, 0x11);
		cx23885_sram_channel_dump(dev,
			&dev->sram_channels[AUDIO_SRAM_CHANNEL]);
	}
	if (status & AUD_INT_DN_SYNC) {
		dprintk(1, "Downstream sync error\n");
		cx_write(AUD_INT_A_GPCNT_CTL, GP_COUNT_CONTROL_RESET);
		return 1;
	}
	/* risc1 downstream */
	if (status & AUD_INT_DN_RISCI1) {
		atomic_set(&chip->count, cx_read(AUD_INT_A_GPCNT));
		snd_pcm_period_elapsed(chip->substream);
	}
	/* FIXME: Any other status should deserve a special handling? */

	return 1;
}

int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
					 struct sram_channel *sram_ch)
{
	u32 tmp = 0;
	int err = 0;

	// 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
	tmp = cx_read(VID_CH_MODE_SEL);
	cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);

	// Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds.
	cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
	cx_write(sram_ch->cmds_start + 4, 0);	/* Risc IPC High 64 bits 63-32 */

	/* reset counter */
	cx_write(sram_ch->gpcnt_ctl, 3);

	// Clear our bits from the interrupt status register.
	cx_write(sram_ch->int_stat, _intr_msk);

	//Set the interrupt mask register, enable irq.
	cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
	tmp = cx_read(sram_ch->int_msk);
	cx_write(sram_ch->int_msk, tmp |= _intr_msk);

	err =
	    request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
			IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
	if (err < 0) {
		printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
		       dev->pci->irq);
		goto fail_irq;
	}
	// Start the DMA  engine
	tmp = cx_read(sram_ch->dma_ctl);
	cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);

	dev->_is_running_ch2 = 1;
	dev->_is_first_frame_ch2 = 1;

	return 0;

      fail_irq:
	cx25821_dev_unregister(dev);
	return err;
}

static int vp3054_bit_getsda(void *data)
{
	struct cx8802_dev *dev = data;
	struct cx88_core *core = dev->core;
	u32 state;

	state = cx_read(MO_GP0_IO);
	return (state & 0x02) ? 1 : 0;
}

static int cx23885_g_host_register(struct cx23885_dev *dev,
				   struct v4l2_dbg_register *reg)
{
	if ((reg->reg & 0x3) != 0 || reg->reg >= pci_resource_len(dev->pci, 0))
		return -EINVAL;

	reg->size = 4;
	reg->val = cx_read(reg->reg);
	return 0;
}