本文整理汇总了C++中cvmx_read_csr函数的典型用法代码示例。如果您正苦于以下问题:C++ cvmx_read_csr函数的具体用法?C++ cvmx_read_csr怎么用?C++ cvmx_read_csr使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了cvmx_read_csr函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: cvmx_raid_shutdown
/**
* Shutdown the RAID block. RAID must be idle when
* this function is called.
*
* @return Zero on success, negative on failure
*/
int cvmx_raid_shutdown(void)
{
cvmx_rad_reg_ctl_t rad_reg_ctl;
if (cvmx_cmd_queue_length(CVMX_CMD_QUEUE_RAID)) {
cvmx_dprintf("ERROR: cvmx_raid_shutdown: RAID not idle.\n");
return -1;
}
rad_reg_ctl.u64 = cvmx_read_csr(CVMX_RAD_REG_CTL);
rad_reg_ctl.s.reset = 1;
cvmx_write_csr(CVMX_RAD_REG_CTL, rad_reg_ctl.u64);
cvmx_wait(100);
cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_RAID);
cvmx_write_csr(CVMX_RAD_REG_CMD_BUF, 0);
return 0;
}
示例2: cvmx_pko_enable
/**
* Enables the packet output hardware. It must already be
* configured.
*/
void cvmx_pko_enable(void)
{
union cvmx_pko_reg_flags flags;
flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
if (flags.s.ena_pko)
cvmx_dprintf
("Warning: Enabling PKO when PKO already enabled.\n");
flags.s.ena_dwb = 1;
flags.s.ena_pko = 1;
/*
* always enable big endian for 3-word command. Does nothing
* for 2-word.
*/
flags.s.store_be = 1;
cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64);
}
示例3: __cvmx_helper_rgmii_link_get
/**
* Return the link state of an IPD/PKO port as returned by
* auto negotiation. The result of this function may not match
* Octeon's link config if auto negotiation has changed since
* the last call to cvmx_helper_link_set().
*
* @ipd_port: IPD/PKO port to query
*
* Returns Link state
*/
cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port)
{
int interface = cvmx_helper_get_interface_num(ipd_port);
int index = cvmx_helper_get_interface_index_num(ipd_port);
union cvmx_asxx_prt_loop asxx_prt_loop;
asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
if (asxx_prt_loop.s.int_loop & (1 << index)) {
/* Force 1Gbps full duplex on internal loopback */
cvmx_helper_link_info_t result;
result.u64 = 0;
result.s.full_duplex = 1;
result.s.link_up = 1;
result.s.speed = 1000;
return result;
} else
return __cvmx_helper_board_link_get(ipd_port);
}
示例4: cvmx_ilk_runtime_status
void cvmx_ilk_runtime_status (int interface)
{
cvmx_ilk_txx_cfg1_t ilk_txx_cfg1;
cvmx_ilk_txx_flow_ctl0_t ilk_txx_flow_ctl0;
cvmx_ilk_rxx_cfg1_t ilk_rxx_cfg1;
cvmx_ilk_rxx_int_t ilk_rxx_int;
cvmx_ilk_rxx_flow_ctl0_t ilk_rxx_flow_ctl0;
cvmx_ilk_rxx_flow_ctl1_t ilk_rxx_flow_ctl1;
cvmx_ilk_gbl_int_t ilk_gbl_int;
cvmx_dprintf ("\nilk run-time status: interface: %d\n", interface);
ilk_txx_cfg1.u64 = cvmx_read_csr (CVMX_ILK_TXX_CFG1(interface));
cvmx_dprintf ("\nilk txx cfg1: 0x%16lx\n", ilk_txx_cfg1.u64);
if (ilk_txx_cfg1.s.rx_link_fc)
cvmx_dprintf ("link flow control received\n");
if (ilk_txx_cfg1.s.tx_link_fc)
cvmx_dprintf ("link flow control sent\n");
ilk_txx_flow_ctl0.u64 = cvmx_read_csr (CVMX_ILK_TXX_FLOW_CTL0(interface));
cvmx_dprintf ("\nilk txx flow ctl0: 0x%16lx\n", ilk_txx_flow_ctl0.u64);
ilk_rxx_cfg1.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG1(interface));
cvmx_dprintf ("\nilk rxx cfg1: 0x%16lx\n", ilk_rxx_cfg1.u64);
cvmx_dprintf ("rx fifo count: %d\n", ilk_rxx_cfg1.s.rx_fifo_cnt);
ilk_rxx_int.u64 = cvmx_read_csr (CVMX_ILK_RXX_INT(interface));
cvmx_dprintf ("\nilk rxx int: 0x%16lx\n", ilk_rxx_int.u64);
if (ilk_rxx_int.s.pkt_drop_rxf)
cvmx_dprintf ("rx fifo packet drop\n");
if (ilk_rxx_int.u64)
cvmx_write_csr (CVMX_ILK_RXX_INT(interface), ilk_rxx_int.u64);
ilk_rxx_flow_ctl0.u64 = cvmx_read_csr (CVMX_ILK_RXX_FLOW_CTL0(interface));
cvmx_dprintf ("\nilk rxx flow ctl0: 0x%16lx\n", ilk_rxx_flow_ctl0.u64);
ilk_rxx_flow_ctl1.u64 = cvmx_read_csr (CVMX_ILK_RXX_FLOW_CTL1(interface));
cvmx_dprintf ("\nilk rxx flow ctl1: 0x%16lx\n", ilk_rxx_flow_ctl1.u64);
ilk_gbl_int.u64 = cvmx_read_csr (CVMX_ILK_GBL_INT);
cvmx_dprintf ("\nilk gbl int: 0x%16lx\n", ilk_gbl_int.u64);
if (ilk_gbl_int.s.rxf_push_full)
cvmx_dprintf ("rx fifo overflow\n");
if (ilk_gbl_int.u64)
cvmx_write_csr (CVMX_ILK_GBL_INT, ilk_gbl_int.u64);
}
示例5: cvm_oct_xaui_open
int cvm_oct_xaui_open(struct net_device *dev)
{
union cvmx_gmxx_prtx_cfg gmx_cfg;
struct octeon_ethernet *priv = netdev_priv(dev);
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
cvmx_helper_link_info_t link_info;
gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
gmx_cfg.s.en = 1;
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
if (!octeon_is_simulation()) {
link_info = cvmx_helper_link_get(priv->port);
if (!link_info.s.link_up)
netif_carrier_off(dev);
}
return 0;
}
示例6: ciu_en1_intr_bind
static int
ciu_en1_intr_bind(void *arg, u_char target)
{
uint64_t mask;
int core;
int irq;
irq = (uintptr_t)arg;
CPU_FOREACH(core) {
mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(core*2));
if (core == target)
mask |= 1ull << (irq - CIU_IRQ_EN1_BEGIN);
else
mask &= ~(1ull << (irq - CIU_IRQ_EN1_BEGIN));
cvmx_write_csr(CVMX_CIU_INTX_EN1(core*2), mask);
}
return (0);
}
示例7: __cvmx_qlm_set_mult
/**
* @INTERNAL
* Decrement the MPLL Multiplier for the DLM as per Errata G-20669
*
* @param qlm DLM to configure
* @param baud_mhz Speed of the DLM configured at
* @param old_multiplier MPLL_MULTIPLIER value to decrement
*/
void __cvmx_qlm_set_mult(int qlm, int baud_mhz, int old_multiplier)
{
cvmx_gserx_dlmx_mpll_multiplier_t mpll_multiplier;
uint64_t meas_refclock, mult;
if (!OCTEON_IS_MODEL(OCTEON_CN70XX))
return;
if (qlm == -1)
return;
meas_refclock = cvmx_qlm_measure_clock(qlm);
if (meas_refclock == 0) {
cvmx_warn("DLM%d: Reference clock not running\n", qlm);
return;
}
mult = (uint64_t)baud_mhz * 1000000 + (meas_refclock/2);
mult /= meas_refclock;
#ifdef CVMX_BUILD_FOR_UBOOT
/* For simulator just write the multiplier directly, to make it
faster to boot. */
if (gd->arch.board_desc.board_type == CVMX_BOARD_TYPE_SIM) {
cvmx_write_csr(CVMX_GSERX_DLMX_MPLL_MULTIPLIER(qlm, 0), mult);
return;
}
#endif
/* 6. Decrease MPLL_MULTIPLIER by one continually until it reaches
the desired long-term setting, ensuring that each MPLL_MULTIPLIER
value is constant for at least 1 msec before changing to the next
value. The desired long-term setting is as indicated in HRM tables
21-1, 21-2, and 21-3. This is not required with the HRM
sequence. */
do {
mpll_multiplier.u64 = cvmx_read_csr(CVMX_GSERX_DLMX_MPLL_MULTIPLIER(qlm, 0));
mpll_multiplier.s.mpll_multiplier = --old_multiplier;
cvmx_write_csr(CVMX_GSERX_DLMX_MPLL_MULTIPLIER(qlm, 0), mpll_multiplier.u64);
/* Wait for 1 ms */
cvmx_wait_usec(1000);
} while (old_multiplier > (int)mult);
}
示例8: cvm_oct_common_set_mac_address
/**
* cvm_oct_common_set_mac_address - set the hardware MAC address for a device
* @dev: The device in question.
* @addr: Address structure to change it too.
* Returns Zero on success
*/
static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr)
{
struct octeon_ethernet *priv = netdev_priv(dev);
union cvmx_gmxx_prtx_cfg gmx_cfg;
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
memcpy(dev->dev_addr, addr + 2, 6);
if ((interface < 2)
&& (cvmx_helper_interface_get_mode(interface) !=
CVMX_HELPER_INTERFACE_MODE_SPI)) {
int i;
uint8_t *ptr = addr;
uint64_t mac = 0;
for (i = 0; i < 6; i++)
mac = (mac << 8) | (uint64_t) (ptr[i + 2]);
gmx_cfg.u64 =
cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
gmx_cfg.u64 & ~1ull);
cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac);
cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface),
ptr[2]);
cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface),
ptr[3]);
cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface),
ptr[4]);
cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface),
ptr[5]);
cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface),
ptr[6]);
cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface),
ptr[7]);
cvm_oct_common_set_multicast_list(dev);
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
gmx_cfg.u64);
}
return 0;
}
示例9: ehci_octeon_start
static void ehci_octeon_start(struct device *dev)
{
union cvmx_uctlx_ehci_ctl ehci_ctl;
octeon2_usb_clocks_start(dev);
ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
/* Use 64-bit addressing. */
ehci_ctl.s.ehci_64b_addr_en = 1;
ehci_ctl.s.l2c_addr_msb = 0;
#ifdef __BIG_ENDIAN
ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
#else
ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
ehci_ctl.s.inv_reg_a2 = 1;
#endif
cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
}
示例10: __cvmx_helper_agl_enable
/**
* @INTERNAL
* Bringup and enable a RGMII interface. After this call packet
* I/O should be fully functional. This is called with IPD
* enabled but PKO disabled.
*
* @param interface Interface to bring up
*
* @return Zero on success, negative on failure
*/
int __cvmx_helper_agl_enable(int interface)
{
int port = cvmx_helper_agl_get_port(interface);
int ipd_port = cvmx_helper_get_ipd_port(interface, port);
union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs;
union cvmx_pko_reg_read_idx read_idx;
int do_link_set = 1;
int i;
/* Setup PKO for AGL interface. Back pressure is not supported. */
pko_mem_port_ptrs.u64 = 0;
read_idx.u64 = 0;
read_idx.s.inc = 1;
cvmx_write_csr(CVMX_PKO_REG_READ_IDX, read_idx.u64);
for (i = 0 ; i < 40; i++) {
pko_mem_port_ptrs.u64 = cvmx_read_csr(CVMX_PKO_MEM_PORT_PTRS);
if (pko_mem_port_ptrs.s.pid == 24) {
pko_mem_port_ptrs.s.eid = 10;
pko_mem_port_ptrs.s.bp_port = 40;
cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
break;
}
}
cvmx_agl_enable(port);
#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
/*
* Linux kernel driver will call ....link_set with the
* proper link state. In the simulator there is no
* link state polling and hence it is set from
* here.
*/
if (!(cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM))
do_link_set = 0;
#endif
if (do_link_set)
cvmx_agl_link_set(port, cvmx_agl_link_get(ipd_port), 1);
return 0;
}
示例11: ptp_to_ktime
static ktime_t ptp_to_ktime(u64 ptptime)
{
ktime_t ktimebase;
u64 ptpbase;
unsigned long flags;
local_irq_save(flags);
/* Fill the icache with the code */
ktime_get_real();
/* Flush all pending operations */
mb();
/* Read the time and PTP clock as close together as
* possible. It is important that this sequence take the same
* amount of time to reduce jitter
*/
ktimebase = ktime_get_real();
ptpbase = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_HI);
local_irq_restore(flags);
return ktime_sub_ns(ktimebase, ptpbase - ptptime);
}
示例12: cvm_oct_mdio_write
/**
* Perform an MII write. Called by the generic MII routines
*
* @param dev Device to perform write for
* @param phy_id The MII phy id
* @param location Register location to write
* @param val Value to write
*/
void cvm_oct_mdio_write(struct ifnet *ifp, int phy_id, int location, int val)
{
cvmx_smi_cmd_t smi_cmd;
cvmx_smi_wr_dat_t smi_wr;
MDIO_LOCK();
smi_wr.u64 = 0;
smi_wr.s.dat = val;
cvmx_write_csr(CVMX_SMI_WR_DAT, smi_wr.u64);
smi_cmd.u64 = 0;
smi_cmd.s.phy_op = 0;
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = location;
cvmx_write_csr(CVMX_SMI_CMD, smi_cmd.u64);
do {
smi_wr.u64 = cvmx_read_csr(CVMX_SMI_WR_DAT);
} while (smi_wr.s.pending);
MDIO_UNLOCK();
}
示例13: __cvmx_interrupt_asxx_enable
/**
* Enable ASX error interrupts that exist on CN3XXX, CN50XX, and
* CN58XX.
*
* @block: Interface to enable 0-1
*/
void __cvmx_interrupt_asxx_enable(int block)
{
int mask;
union cvmx_asxx_int_en csr;
/*
* CN38XX and CN58XX have two interfaces with 4 ports per
* interface. All other chips have a max of 3 ports on
* interface 0
*/
if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
mask = 0xf; /* Set enables for 4 ports */
else
mask = 0x7; /* Set enables for 3 ports */
/* Enable interface interrupts */
csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block));
csr.s.txpsh = mask;
csr.s.txpop = mask;
csr.s.ovrflw = mask;
cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64);
}
示例14: mailbox_interrupt
static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
{
const int coreid = cvmx_get_core_num();
uint64_t action;
/* Load the mailbox register to figure out what we're supposed to do */
action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;
/* Clear the mailbox to clear the interrupt */
cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
if (action & SMP_CALL_FUNCTION)
smp_call_function_interrupt();
if (action & SMP_RESCHEDULE_YOURSELF)
scheduler_ipi();
/* Check if we've been told to flush the icache */
if (action & SMP_ICACHE_FLUSH)
asm volatile ("synci 0($0)\n");
return IRQ_HANDLED;
}
示例15: flash_init
/**
* Module/ driver initialization.
*
* Returns Zero on success
*/
static int __init flash_init(void)
{
/*
* Read the bootbus region 0 setup to determine the base
* address of the flash.
*/
union cvmx_mio_boot_reg_cfgx region_cfg;
region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(0));
if (region_cfg.s.en) {
/*
* The bootloader always takes the flash and sets its
* address so the entire flash fits below
* 0x1fc00000. This way the flash aliases to
* 0x1fc00000 for booting. Software can access the
* full flash at the true address, while core boot can
* access 4MB.
*/
/* Use this name so old part lines work */
flash_map.name = "phys_mapped_flash";
flash_map.phys = region_cfg.s.base << 16;
flash_map.size = 0x1fc00000 - flash_map.phys;
/* 8-bit bus (0 + 1) or 16-bit bus (1 + 1) */
flash_map.bankwidth = region_cfg.s.width + 1;
flash_map.virt = ioremap(flash_map.phys, flash_map.size);
pr_notice("Bootbus flash: Setting flash for %luMB flash at "
"0x%08llx\n", flash_map.size >> 20, flash_map.phys);
// simple_map_init(&flash_map);
flash_map.read = octeon_flash_map_read;
flash_map.write = octeon_flash_map_write;
flash_map.copy_from = octeon_flash_map_copy_from;
flash_map.copy_to = octeon_flash_map_copy_to;
mymtd = do_map_probe("cfi_probe", &flash_map);
if (mymtd) {
mymtd->owner = THIS_MODULE;
mtd_device_parse_register(mymtd, part_probe_types,
NULL, NULL, 0);
} else {
pr_err("Failed to register MTD device for flash\n");
}
}