本文整理汇总了C++中cpuid函数的典型用法代码示例。如果您正苦于以下问题：C++ cpuid函数的具体用法？C++ cpuid怎么用？C++ cpuid使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了cpuid函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: get_vendor
static int get_vendor(void){
int eax, ebx, ecx, edx;
union
{
char vchar[16];
int vint[4];
} vendor;
cpuid(0, &eax, &ebx, &ecx, &edx);
*(&vendor.vint[0]) = ebx;
*(&vendor.vint[1]) = edx;
*(&vendor.vint[2]) = ecx;
vendor.vchar[12] = '\0';
if (!strcmp(vendor.vchar, "GenuineIntel")) return VENDOR_INTEL;
if (!strcmp(vendor.vchar, "AuthenticAMD")) return VENDOR_AMD;
if (!strcmp(vendor.vchar, "CentaurHauls")) return VENDOR_CENTAUR;
if ((eax == 0) || ((eax & 0x500) != 0)) return VENDOR_INTEL;
return VENDOR_UNKNOWN;
}示例2: cpuid_smp_cpuid
static void cpuid_smp_cpuid(void *cmd_block)
{
struct cpuid_command *cmd = (struct cpuid_command *)cmd_block;
cpuid(cmd->reg, &cmd->data[0], &cmd->data[1], &cmd->data[2],
&cmd->data[3]);
}示例3: get_vendor
int get_vendor(void){
int eax, ebx, ecx, edx;
char vendor[13];
cpuid(0, &eax, &ebx, &ecx, &edx);
*(int *)(&vendor[0]) = ebx;
*(int *)(&vendor[4]) = edx;
*(int *)(&vendor[8]) = ecx;
vendor[12] = (char)0;
if (!strcmp(vendor, "GenuineIntel")) return VENDOR_INTEL;
if (!strcmp(vendor, " UMC UMC UMC")) return VENDOR_UMC;
if (!strcmp(vendor, "AuthenticAMD")) return VENDOR_AMD;
if (!strcmp(vendor, "CyrixInstead")) return VENDOR_CYRIX;
if (!strcmp(vendor, "NexGenDriven")) return VENDOR_NEXGEN;
if (!strcmp(vendor, "CentaurHauls")) return VENDOR_CENTAUR;
if (!strcmp(vendor, "RiseRiseRise")) return VENDOR_RISE;
if (!strcmp(vendor, " SiS SiS SiS")) return VENDOR_SIS;
if (!strcmp(vendor, "GenuineTMx86")) return VENDOR_TRANSMETA;
if (!strcmp(vendor, "Geode by NSC")) return VENDOR_NSC;
if ((eax == 0) || ((eax & 0x500) != 0)) return VENDOR_INTEL;
return VENDOR_UNKNOWN;
}示例4: get_l3_size
static __inline__ int get_l3_size(void){
int eax, ebx, ecx, edx;
cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
return BITMASK(edx, 18, 0x3fff) * 512;
}示例5: cpuid_flag
static word32 cpuid_flag(word32 leaf, word32 sub, word32 num, word32 bit) {
int got_intel_cpu=0;
unsigned int reg[5];
reg[4] = '\0' ;
cpuid(reg, 0, 0);
if(XMEMCMP((char *)&(reg[EBX]), "Genu", 4) == 0 &&
XMEMCMP((char *)&(reg[EDX]), "ineI", 4) == 0 &&
XMEMCMP((char *)&(reg[ECX]), "ntel", 4) == 0) {
got_intel_cpu = 1;
}
if (got_intel_cpu) {
cpuid(reg, leaf, sub);
return((reg[num]>>bit)&0x1) ;
}
return 0 ;
}示例6: cpuid_init
static void cpuid_init( ) {
if (!cpuid_done) {
cpuid(0x1, cpuid_ecx, cpuid_edx);
cpuid_done = true;
print_cpu_info( );
}
}示例7: cpuid_smp_cpuid
static void cpuid_smp_cpuid(void *cmd_block)
{
struct cpuid_command *cmd = (struct cpuid_command *)cmd_block;
if (cmd->cpu == smp_processor_id())
cpuid(cmd->reg, &cmd->data[0], &cmd->data[1], &cmd->data[2],
&cmd->data[3]);
}示例8: slave_main
void slave_main(void)
{
send(MSIM_MASTER_ID, 0, 4);
set_trap_handler();
tlb_init();
kprintf("--DEBUG-- Hello world from CPU #%d!\n", cpuid());
for (;;);
}示例9: is_cpu_clflush_present
/*
* is_cpu_clflush_present -- checks if CLFLUSH instruction is supported
*/
int is_cpu_clflush_present(void) {
unsigned cpuinfo[4] = {0};
cpuid(0x1, 0x0, cpuinfo);
int ret = (cpuinfo[EDX_IDX] & bit_CLFLUSH) != 0;
return ret;
}示例10: is_sse2_available
inline static bool is_sse2_available()
{
#if (defined(__x86_64__) || defined(__amd64))
return true;
#endif
int a,b,c,d;
cpuid(1, a, b, c, d);
return d & (1<<26); // edx bit 26 is set when SSE2 is present
}示例11: core2_get_pmc_count
static int core2_get_pmc_count(void)
{
u32 eax, ebx, ecx, edx;
if ( arch_pmc_cnt == 0 )
{
cpuid(0xa, &eax, &ebx, &ecx, &edx);
arch_pmc_cnt = (eax & 0xff00) >> 8;
}示例12: cpu_info
inline
cpu_info::
cpu_info()
{
constexpr std::uint32_t SSE42 = 1 << 20;
std::uint32_t eax = 0;
std::uint32_t ebx = 0;
std::uint32_t ecx = 0;
std::uint32_t edx = 0;
cpuid(0, eax, ebx, ecx, edx);
if(eax >= 1)
{
cpuid(1, eax, ebx, ecx, edx);
sse42 = (ecx & SSE42) != 0;
}
}示例13: oc_cpu_flags_get
ogg_uint32_t oc_cpu_flags_get(void){
ogg_uint32_t flags;
ogg_uint32_t eax;
ogg_uint32_t ebx;
ogg_uint32_t ecx;
ogg_uint32_t edx;
# if !defined(__amd64__)&&!defined(__x86_64__)
/*Not all x86-32 chips support cpuid, so we have to check.*/
__asm__ __volatile__(
"pushfl\n\t"
"pushfl\n\t"
"popl %[a]\n\t"
"movl %[a],%[b]\n\t"
"xorl $0x200000,%[a]\n\t"
"pushl %[a]\n\t"
"popfl\n\t"
"pushfl\n\t"
"popl %[a]\n\t"
"popfl\n\t"
:[a]"=r"(eax),[b]"=r"(ebx)
:
:"cc"
);
/*No cpuid.*/
if(eax==ebx)return 0;
# endif
cpuid(0,eax,ebx,ecx,edx);
/* l e t n I e n i u n e G*/
if(ecx==0x6C65746E&&edx==0x49656E69&&ebx==0x756E6547||
/* 6 8 x M T e n i u n e G*/
ecx==0x3638784D&&edx==0x54656E69&&ebx==0x756E6547){
int family;
int model;
/*Intel, Transmeta (tested with Crusoe TM5800):*/
cpuid(1,eax,ebx,ecx,edx);
flags=oc_parse_intel_flags(edx,ecx);
family=(eax>>8)&0xF;
model=(eax>>4)&0xF;
/*The SSE unit on the Pentium M and Core Duo is much slower than the MMX
unit, so don't use it.*/
if(family==6&&(model==9||model==13||model==14)){
flags&=~(OC_CPU_X86_SSE2|OC_CPU_X86_PNI);
}
}示例14: cpu_info
void cpu_info()
{
char idstr[64];
idstr[0] = 0;
fillCpuString(idstr);
trim(idstr);
unsigned cpuver = cpuid(1,0);
unsigned features = cpuid(1,1);
temp.mmx = (features >> 23) & 1;
temp.sse = (features >> 25) & 1;
temp.sse2 = (features >> 26) & 1;
temp.cpufq = GetCPUFrequency();
color(CONSCLR_HARDITEM); printf("cpu: ");
color(CONSCLR_HARDINFO);
printf("%s ", idstr);
color(CONSCLR_HARDITEM);
printf("%d.%d.%d [MMX:%s,SSE:%s,SSE2:%s] ",
(cpuver>>8) & 0x0F, (cpuver>>4) & 0x0F, cpuver & 0x0F,
temp.mmx ? "YES" : "NO",
temp.sse ? "YES" : "NO",
temp.sse2 ? "YES" : "NO");
color(CONSCLR_HARDINFO);
printf("at %d MHz\n", (unsigned)(temp.cpufq/1000000));
#ifdef MOD_SSE2
if (!temp.sse2) {
color(CONSCLR_WARNING);
printf("warning: this is an SSE2 build, recompile or download non-P4 version\n");
}
#else //MOD_SSE2
if (temp.sse2) {
color(CONSCLR_WARNING);
printf("warning: SSE2 disabled in compile-time, recompile or download P4 version\n");
}
#endif
}示例15: calibrate_tsc
static void
calibrate_tsc(void)
{
if (0) {
u32 eax, ebx, ecx, edx, cpuid_features = 0;
cpuid(0, &eax, &ebx, &ecx, &edx);
if (eax > 0)
cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
if (!(cpuid_features & CPUID_TSC)) {
SET_GLOBAL(no_tsc, 1);
SET_GLOBAL(cpu_khz, PIT_TICK_RATE / 1000);
dprintf(3, "386/486 class CPU. Using TSC emulation\n");
return;
}
// Setup "timer2"
u8 orig = inb(PORT_PS2_CTRLB);
outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
/* binary, mode 0, LSB/MSB, Ch 2 */
outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
/* LSB of ticks */
outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
/* MSB of ticks */
outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
u64 start = rdtscll();
while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
;
u64 end = rdtscll();
// Restore PORT_PS2_CTRLB
outb(orig, PORT_PS2_CTRLB);
// Store calibrated cpu khz.
u64 diff = end - start;
dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
, (u32)start, (u32)end, (u32)diff);
u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
SET_GLOBAL(cpu_khz, hz / 1000);
dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
}