C++ cpu_reset函数代码示例

static void m68k_cpu_realizefn(DeviceState *dev, Error **errp)
{
    CPUState *cs = CPU(dev);
    M68kCPU *cpu = M68K_CPU(dev);
    M68kCPUClass *mcc = M68K_CPU_GET_CLASS(dev);
    Error *local_err = NULL;

    register_m68k_insns(&cpu->env);

    cpu_exec_realizefn(cs, &local_err);
    if (local_err != NULL) {
        error_propagate(errp, local_err);
        return;
    }

    m68k_cpu_init_gdb(cpu);

    cpu_reset(cs);
    qemu_init_vcpu(cs);

    mcc->parent_realize(dev, errp);
}

static void ppce500_cpu_reset(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUState *cs = CPU(cpu);
    CPUPPCState *env = &cpu->env;
    struct boot_info *bi = env->load_info;

    cpu_reset(cs);

    /* Set initial guest state. */
    cs->halted = 0;
    env->gpr[1] = (16<<20) - 8;
    env->gpr[3] = bi->dt_base;
    env->gpr[4] = 0;
    env->gpr[5] = 0;
    env->gpr[6] = EPAPR_MAGIC;
    env->gpr[7] = mmubooke_initial_mapsize(env);
    env->gpr[8] = 0;
    env->gpr[9] = 0;
    env->nip = bi->entry;
    mmubooke_create_initial_mapping(env);
}

int
cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
    unsigned long cpuid;

    if (argc < 3)
        return cmd_usage(cmdtp);

    cpuid = simple_strtoul(argv[1], NULL, 10);
    if (cpuid >= cpu_numcores()) {
        printf ("Core num: %lu is out of range[0..%d]\n",
                cpuid, cpu_numcores() - 1);
        return 1;
    }


    if (argc == 3) {
        if (strncmp(argv[2], "reset", 5) == 0)
            cpu_reset(cpuid);
        else if (strncmp(argv[2], "status", 6) == 0)
            cpu_status(cpuid);
        else if (strncmp(argv[2], "disable", 7) == 0)
            return cpu_disable(cpuid);
        else
            return cmd_usage(cmdtp);

        return 0;
    }

    /* 4 or greater, make sure its release */
    if (strncmp(argv[2], "release", 7) != 0)
        return cmd_usage(cmdtp);

    if (cpu_release(cpuid, argc - 3, argv + 3))
        return cmd_usage(cmdtp);

    return 0;
}

static void emu_main_loop_inner(void) {
    if (!emulationPaused) {
        if (cpuEvents & EVENT_RESET) {
            gui_console_printf("[CEmu] Calculator reset triggered...\n");
            cpu_reset();
            cpuEvents &= ~EVENT_RESET;
        }
#ifdef DEBUG_SUPPORT
        if (!cpu.halted && (cpuEvents & EVENT_DEBUG_STEP)) {
            cpuEvents &= ~EVENT_DEBUG_STEP;
            open_debugger(DBG_STEP, 0);
        }
#endif
        if (!asic.shipModeEnabled) {
            sched_process_pending_events();
            cpu_execute();
        } else {
            gui_emu_sleep(50);
        }
    } else {
        gui_emu_sleep(50);
    }
}

static void s390_cpu_initfn(Object *obj)
{
    S390CPU *cpu = S390_CPU(obj);
    CPUS390XState *env = &cpu->env;
    static int cpu_num = 0;
#if !defined(CONFIG_USER_ONLY)
    struct tm tm;
#endif

    cpu_exec_init(env);
#if !defined(CONFIG_USER_ONLY)
    qemu_get_timedate(&tm, 0);
    env->tod_offset = TOD_UNIX_EPOCH +
                      (time2tod(mktimegm(&tm)) * 1000000000ULL);
    env->tod_basetime = 0;
    env->tod_timer = qemu_new_timer_ns(vm_clock, s390x_tod_timer, cpu);
    env->cpu_timer = qemu_new_timer_ns(vm_clock, s390x_cpu_timer, cpu);
#endif
    env->cpu_num = cpu_num++;
    env->ext_index = -1;

    cpu_reset(CPU(cpu));
}

static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
{
    CPUState *cs = CPU(dev);
    TriCoreCPU *cpu = TRICORE_CPU(dev);
    TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev);
    CPUTriCoreState *env = &cpu->env;

    /* Some features automatically imply others */
    if (tricore_feature(env, TRICORE_FEATURE_161)) {
        set_feature(env, TRICORE_FEATURE_16);
    }

    if (tricore_feature(env, TRICORE_FEATURE_16)) {
        set_feature(env, TRICORE_FEATURE_131);
    }
    if (tricore_feature(env, TRICORE_FEATURE_131)) {
        set_feature(env, TRICORE_FEATURE_13);
    }
    cpu_reset(cs);
    qemu_init_vcpu(cs);

    tcc->parent_realize(dev, errp);
}

static void main_cpu_reset(void *opaque)
{
    ResetData *s = (ResetData *)opaque;
    CPUSPARCState *env = &s->cpu->env;
    static unsigned int nr_resets;

    cpu_reset(CPU(s->cpu));

    cpu_timer_reset(env->tick);
    cpu_timer_reset(env->stick);
    cpu_timer_reset(env->hstick);

    env->gregs[1] = 0; // Memory start
    env->gregs[2] = ram_size; // Memory size
    env->gregs[3] = 0; // Machine description XXX
    if (nr_resets++ == 0) {
        /* Power on reset */
        env->pc = s->prom_addr + 0x20ULL;
    } else {
        env->pc = s->prom_addr + 0x40ULL;
    }
    env->npc = env->pc + 4;
}

CPUM68KState *cpu_m68k_init(const char *cpu_model)
{
    CPUM68KState *env;
    static int inited;

    env = qemu_mallocz(sizeof(CPUM68KState));
    cpu_exec_init(env);
    if (!inited) {
        inited = 1;
        m68k_tcg_init();
    }

    env->cpu_model_str = cpu_model;

    if (cpu_m68k_set_model(env, cpu_model) < 0) {
        cpu_m68k_close(env);
        return NULL;
    }

    cpu_reset(env);
    qemu_init_vcpu(env);
    return env;
}

void machine_kexec(struct kimage *image)
{
	unsigned long page_list;
	unsigned long reboot_code_buffer_phys;
	void *reboot_code_buffer;


	page_list = image->head & PAGE_MASK;

	/* we need both effective and real address here */
	reboot_code_buffer_phys =
	    page_to_pfn(image->control_code_page) << PAGE_SHIFT;
	reboot_code_buffer = page_address(image->control_code_page);

	/* Prepare parameters for reboot_code_buffer*/
	kexec_start_address = image->start;
	kexec_indirection_page = page_list;
	kexec_mach_type = machine_arch_type;
	kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET;

	/* copy our kernel relocation code to the control code page */
	memcpy(reboot_code_buffer,
	       relocate_new_kernel, relocate_new_kernel_size);


	flush_icache_range((unsigned long) reboot_code_buffer,
			   (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
	printk(KERN_INFO "Bye!\n");

	local_irq_disable();
	local_fiq_disable();
	setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
	flush_cache_all();
	cpu_proc_fin();
	flush_cache_all();
	cpu_reset(reboot_code_buffer_phys);
}

Nios2CPU *cpu_nios2_init(const char *cpu_model)
{
    Nios2CPU *cpu;
    int i;

    cpu = NIOS2_CPU(object_new(TYPE_NIOS2_CPU));

    cpu->env.reset_addr = RESET_ADDRESS;
    cpu->env.exception_addr = EXCEPTION_ADDRESS;
    cpu->env.fast_tlb_miss_addr = FAST_TLB_MISS_ADDRESS;

    cpu_reset(CPU(cpu));
    qemu_init_vcpu(CPU(cpu));

    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

    for (i = 0; i < NUM_CORE_REGS; i++) {
        cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
                                      offsetof(CPUNios2State, regs[i]),
                                      regnames[i]);
    }

    return cpu;
}

/*
 * Reset the system. It is called by machine_restart().
 */
void arch_reset(char mode, const char *cmd)
{
	unsigned int wcr_enable;

#ifdef CONFIG_MACH_MX51_EFIKAMX
	if (machine_is_mx51_efikamx()) {
		mx51_efikamx_reset();
		return;
	}
#endif

	if (cpu_is_mx1()) {
		wcr_enable = (1 << 0);
	} else {
		struct clk *clk;

		clk = clk_get_sys("imx2-wdt.0", NULL);
		if (!IS_ERR(clk))
			clk_enable(clk);
		wcr_enable = (1 << 2);
	}

	/* Assert SRS signal */
	__raw_writew(wcr_enable, wdog_base);

	/* wait for reset to assert... */
	mdelay(500);

	printk(KERN_ERR "Watchdog reset failed to assert reset\n");

	/* delay to allow the serial port to show the message */
	mdelay(50);

	/* we'll take a jump through zero as a poor second */
	cpu_reset(0);
}

int main(void)
{

  /* USER CODE BEGIN 1 */
  my_usb_init();
  /* USER CODE END 1 */

  /* MCU Configuration----------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();

  /* Configure the system clock */
  SystemClock_Config();

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
  MX_TIM1_Init();
  MX_USB_DEVICE_Init();
  MX_USART3_UART_Init();
  MX_TIM2_Init();

  /* USER CODE BEGIN 2 */
  HAL_TIM_Base_Start(&htim2);
  delay_us_init(&htim2);
  softserial_init(SOFTSERIAL_TX_GPIO_Port, SOFTSERIAL_TX_Pin);
  hmi_lcd_init(&huart3);
  cpu_ctrl_init(&htim1);
  /* USER CODE END 2 */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  HAL_Delay(100);
  hsc_stop();
  cpu_reset();
  lcd_clear();
  addr_input();
  data_input();
  build_ui();
  HAL_Delay(100);

  while (1)
  {
  /* USER CODE END WHILE */

  /* USER CODE BEGIN 3 */
    if(is_running == 0)
      addr_data_display_update();

    // z80 reset button
    if(is_button_1_pressed)
    {
      hsc_stop();
      cpu_reset();
      lcd_print_width(130, 110, 180, 45, "CYAN", "RESET");
      is_button_1_pressed = 0;
      HAL_Delay(500);
      build_ui();
    }

    // clk step button
    if(is_button_3_pressed)
    {
      hsc_stop();
      cycle_clock(1);
      lcd_print_width(130, 110, 180, 45, "RED", "CLK STEP");
      is_button_3_pressed = 0;
      HAL_Delay(100);
      build_ui();
    }

    // ins step button
    if(is_button_4_pressed)
    {
      hsc_stop();
      lcd_print_width(130, 110, 180, 45, "GREEN", "INS STEP");
      // cycle clock until we're at next M1 cycle
      while(HAL_GPIO_ReadPin(CPU_CTRL_PORT, M1_Pin) == LOW)
        cycle_clock(1);
      while(HAL_GPIO_ReadPin(CPU_CTRL_PORT, M1_Pin) == HIGH)
        cycle_clock(1);
      is_button_4_pressed = 0;
      HAL_Delay(100);
      build_ui();
    }

    // run/stop button
    if(is_button_5_pressed)
    {
      is_running = (is_running + 1) % 2;
      if(is_running)
      {
        lcd_print_width(130, 110, 180, 45, "GREEN", "RUNNING");
        hsc_start();
      }
      else
      {
        hsc_stop();
        build_ui();
      }
//.........这里部分代码省略.........

void _exit(int status)
{
  status = status;
  /* TODO save stack + assert info into nvram */
  cpu_reset("SYSCALL EXIT");
}

static void s390_cpu_machine_reset_cb(void *opaque)
{
    S390CPU *cpu = opaque;

    cpu_reset(CPU(cpu));
}

static void ppc_heathrow_reset(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    cpu_reset(CPU(cpu));
}