C++ cpu_register_io_memory函数代码示例

static int xilinx_uartlite_init(SysBusDevice *dev)
{
    struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev);
    int uart_regs;

    sysbus_init_irq(dev, &s->irq);

    uart_update_status(s);
    uart_regs = cpu_register_io_memory(uart_read, uart_write, s,
                                       DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, R_MAX * 4, uart_regs);

    s->chr = qdev_init_chardev(&dev->qdev);
    if (s->chr)
        qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
    return 0;
}

PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
        qemu_irq irq)
{
    int iomemtype;
    PXA2xxKeyPadState *s;

    s = (PXA2xxKeyPadState *) qemu_mallocz(sizeof(PXA2xxKeyPadState));
    s->irq = irq;

    iomemtype = cpu_register_io_memory(pxa2xx_keypad_readfn,
                    pxa2xx_keypad_writefn, s, DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory(base, 0x00100000, iomemtype);

    vmstate_register(NULL, 0, &vmstate_pxa2xx_keypad, s);

    return s;
}

static int lm32_timer_init(SysBusDevice *dev)
{
    LM32TimerState *s = FROM_SYSBUS(typeof(*s), dev);
    int timer_regs;

    sysbus_init_irq(dev, &s->irq);

    s->bh = qemu_bh_new(timer_hit, s);
    s->ptimer = ptimer_init(s->bh);
    ptimer_set_freq(s->ptimer, s->freq_hz);

    timer_regs = cpu_register_io_memory(timer_read_fn, timer_write_fn, s,
            DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, R_MAX * 4, timer_regs);

    return 0;
}

static void etraxfs_ser_init(SysBusDevice *dev)
{
    struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
    int ser_regs;

    /* transmitter begins ready and idle.  */
    s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
    s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);

    sysbus_init_irq(dev, &s->irq);
    ser_regs = cpu_register_io_memory(ser_read, ser_write, s);
    sysbus_init_mmio(dev, R_MAX * 4, ser_regs);
    s->chr = qdev_init_chardev(&dev->qdev);
    if (s->chr)
        qemu_chr_add_handlers(s->chr,
                      serial_can_receive, serial_receive,
                      serial_event, s);
}

void icp_pit_init(uint32_t base, qemu_irq *pic, int irq)
{
    int iomemtype;
    icp_pit_state *s;

    s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));
    /* Timer 0 runs at the system clock speed (40MHz).  */
    s->timer[0] = arm_timer_init(40000000, pic[irq]);
    /* The other two timers run at 1MHz.  */
    s->timer[1] = arm_timer_init(1000000, pic[irq + 1]);
    s->timer[2] = arm_timer_init(1000000, pic[irq + 2]);

    iomemtype = cpu_register_io_memory(0, icp_pit_readfn,
                                       icp_pit_writefn, s);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);
    /* This device has no state to save/restore.  The component timers will
       save themselves.  */
}

void sp804_init(uint32_t base, qemu_irq irq)
{
    int iomemtype;
    sp804_state *s;
    qemu_irq *qi;

    s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));
    qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
    s->irq = irq;
    /* ??? The timers are actually configurable between 32kHz and 1MHz, but
       we don't implement that.  */
    s->timer[0] = arm_timer_init(1000000, qi[0]);
    s->timer[1] = arm_timer_init(1000000, qi[1]);
    iomemtype = cpu_register_io_memory(0, sp804_readfn,
                                       sp804_writefn, s);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);
    register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
}

static int lance_init(SysBusDevice *dev)
{
    SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev);
    PCNetState *s = &d->state;

    s->mmio_index =
        cpu_register_io_memory(lance_mem_read, lance_mem_write, d);

    qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);

    sysbus_init_mmio(dev, 4, s->mmio_index);

    sysbus_init_irq(dev, &s->irq);

    s->phys_mem_read = ledma_memory_read;
    s->phys_mem_write = ledma_memory_write;
    return pcnet_common_init(&dev->qdev, s, &net_lance_info);
}

static int smc91c111_init1(SysBusDevice *dev)
{
    smc91c111_state *s = FROM_SYSBUS(smc91c111_state, dev);

    s->mmio_index = cpu_register_io_memory(smc91c111_readfn,
                                           smc91c111_writefn, s);
    sysbus_init_mmio(dev, 16, s->mmio_index);
    sysbus_init_irq(dev, &s->irq);
    qemu_macaddr_default_if_unset(&s->conf.macaddr);

    smc91c111_reset(s);

    s->nic = qemu_new_nic(&net_smc91c111_info, &s->conf,
                          dev->qdev.info->name, dev->qdev.id, s);
    qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
    /* ??? Save/restore.  */
    return 0;
}

static int stm32l_sys_init(uint32_t base, qemu_irq irq,
                           stm32_board_info * board)
{
    int iomemtype;
    ssys_state *s;

    s = (ssys_state *)g_malloc0(sizeof(ssys_state));
    s->irq = irq;
    s->board = board;

    iomemtype = cpu_register_io_memory(ssys_readfn,
                                       ssys_writefn, s,
                                       DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);
    ssys_reset(s);
    vmstate_register(NULL, -1, &vmstate_stm32_sys, s);
    return 0;
}

PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
        qemu_irq irq)
{
    int iomemtype;
    PXA2xxKeyPadState *s;

    s = (PXA2xxKeyPadState *) qemu_mallocz(sizeof(PXA2xxKeyPadState));
    s->irq = irq;

    iomemtype = cpu_register_io_memory(pxa2xx_keypad_readfn,
                    pxa2xx_keypad_writefn, s);
    cpu_register_physical_memory(base, 0x00100000, iomemtype);

    register_savevm("pxa2xx_keypad", 0, 0,
                    pxa2xx_keypad_save, pxa2xx_keypad_load, s);

    return s;
}

static int lm32_uart_init(SysBusDevice *dev)
{
    LM32UartState *s = FROM_SYSBUS(typeof(*s), dev);
    int uart_regs;

    sysbus_init_irq(dev, &s->irq);

    uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s,
            DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, R_MAX * 4, uart_regs);

    s->chr = qdev_init_chardev(&dev->qdev);
    if (s->chr) {
        qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
    }

    return 0;
}

/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 * modified, it should be retrieved with msix_bar_size. */
int msix_init(struct PCIDevice *dev, unsigned short nentries,
              unsigned bar_nr, unsigned bar_size)
{
    int ret;
    /* Nothing to do if MSI is not supported by interrupt controller */
    if (!msix_supported)
        return -ENOTSUP;

    if (nentries > MSIX_MAX_ENTRIES)
        return -EINVAL;

    dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
                                        sizeof *dev->msix_entry_used);

    dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);
    msix_mask_all(dev, nentries);

    dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
                                                  msix_mmio_write, dev,
                                                  DEVICE_NATIVE_ENDIAN);
    if (dev->msix_mmio_index == -1) {
        ret = -EBUSY;
        goto err_index;
    }

    dev->msix_entries_nr = nentries;
    ret = msix_add_config(dev, nentries, bar_nr, bar_size);
    if (ret)
        goto err_config;

    dev->cap_present |= QEMU_PCI_CAP_MSIX;
    return 0;

err_config:
    dev->msix_entries_nr = 0;
    cpu_unregister_io_memory(dev->msix_mmio_index);
err_index:
    qemu_free(dev->msix_table_page);
    dev->msix_table_page = NULL;
    qemu_free(dev->msix_entry_used);
    dev->msix_entry_used = NULL;
    return ret;
}

static void sp804_init(SysBusDevice *dev)
{
    int iomemtype;
    sp804_state *s = FROM_SYSBUS(sp804_state, dev);
    qemu_irq *qi;

    qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
    sysbus_init_irq(dev, &s->irq);
    /* ??? The timers are actually configurable between 32kHz and 1MHz, but
       we don't implement that.  */
    s->timer[0] = arm_timer_init(1000000);
    s->timer[1] = arm_timer_init(1000000);
    s->timer[0]->irq = qi[0];
    s->timer[1]->irq = qi[1];
    iomemtype = cpu_register_io_memory(0, sp804_readfn,
                                       sp804_writefn, s);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
}

static int at91_pio_init(SysBusDevice *dev)
{
    PIOState *s = FROM_SYSBUS(typeof (*s), dev);
    int pio_regs;

    sysbus_init_irq(dev, &s->parent_irq);
    qdev_init_gpio_in(&dev->qdev, at91_pio_set_pin, PIO_PINS * 3);
    qdev_init_gpio_out(&dev->qdev, s->out, PIO_PINS * 3);

    pio_regs = cpu_register_io_memory(at91_pio_readfn, at91_pio_writefn, s, DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, PIO_SIZE, pio_regs);

    at91_pio_reset(s);
    qemu_register_reset(at91_pio_reset, s);
    //register_savevm(&dev->qdev, "at91_pio", -1, 1, at91_pio_save, at91_pio_load, s);
	
    vmstate_register(&dev->qdev, -1, &vmstate_at91sam9_pio, s);
	return 0;
}

static int s5pc1xx_onedram_init1(SysBusDevice *dev, ModemPlatformData *mp)
{
    S5pc1xxOneDRAMState *s = FROM_SYSBUS(S5pc1xxOneDRAMState, dev);
    int onedram_io;

    sysbus_init_irq(dev, &s->irq_onedram_int_ap);
    onedram_io = cpu_register_io_memory(onedram_mm_read,
                                        onedram_mm_write, s);
    sysbus_init_mmio(dev, ONEDRAM_REGISTER_SIZE, onedram_io);

    s->sem = 0;
    s->mbx_ab = 0;
    s->mbx_ba = 0;
    s->check_ab = 0;
    s->check_ba = 0;

    s->irq_onedram_int_ap_pending = 0;
    s->irq_onedram_int_cp_pending = 0;

    s->vmodem_connected = 0;
    s->vmodem_bootup = 0;
    s->fmt_info = (ModemInfo *)qemu_mallocz(sizeof(ModemInfo));

    s->socket_buffer = (uint8_t *)qemu_mallocz(SOCKET_BUFFER_MAX_SIZE);
    s->socket_len = 0;

    s->onedram_state.waiting_authority = FALSE;
    s->onedram_state.non_cmd = INT_MASK_CMD_NONE;
    s->onedram_state.send_size = 0;
    s->onedram_state.waiting_sem_rep = 0;
    s->onedram_state.send_buf = NULL;
    s->onedram_state.interruptable = 1;
    s->onedram_state.writable = 1;

    onedram_register_modem(s, mp);
    onedram_tcp_init(s);

    s->bootup_timer = qemu_new_timer(vm_clock, onedram_bootup, s);
    s->sem_timer = qemu_new_timer(vm_clock, onedram_wait_semaphore, s);

    return 0;
}