C++ cpu_physical_memory_read函数代码示例

static inline void pxa2xx_dma_descriptor_fetch(
                PXA2xxDMAState *s, int ch)
{
    uint32_t desc[4];
    hwaddr daddr = s->chan[ch].descr & ~0xf;
    if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
        daddr += 32;

    cpu_physical_memory_read(daddr, desc, 16);
    s->chan[ch].descr = desc[DDADR];
    s->chan[ch].src = desc[DSADR];
    s->chan[ch].dest = desc[DTADR];
    s->chan[ch].cmd = desc[DCMD];

    if (s->chan[ch].cmd & DCMD_FLOWSRC)
        s->chan[ch].src &= ~3;
    if (s->chan[ch].cmd & DCMD_FLOWTRG)
        s->chan[ch].dest &= ~3;

    if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT))
        printf("%s: unsupported mode in channel %i\n", __FUNCTION__, ch);

    if (s->chan[ch].cmd & DCMD_STARTIRQEN)
        s->chan[ch].state |= DCSR_STARTINTR;
}

/* Load new Frame Descriptors from DMA */
static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
{
    PXAFrameDescriptor desc;
    hwaddr descptr;
    int i;

    for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
        s->dma_ch[i].source = 0;

        if (!s->dma_ch[i].up)
            continue;

        if (s->dma_ch[i].branch & FBR_BRA) {
            descptr = s->dma_ch[i].branch & FBR_SRCADDR;
            if (s->dma_ch[i].branch & FBR_BINT)
                pxa2xx_dma_bs_set(s, i);
            s->dma_ch[i].branch &= ~FBR_BRA;
        } else
            descptr = s->dma_ch[i].descriptor;

        if (!((descptr >= PXA2XX_SDRAM_BASE && descptr +
                 sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size) ||
                (descptr >= PXA2XX_INTERNAL_BASE && descptr + sizeof(desc) <=
                 PXA2XX_INTERNAL_BASE + PXA2XX_INTERNAL_SIZE))) {
            continue;
        }

        cpu_physical_memory_read(descptr, &desc, sizeof(desc));
        s->dma_ch[i].descriptor = le32_to_cpu(desc.fdaddr);
        s->dma_ch[i].source = le32_to_cpu(desc.fsaddr);
        s->dma_ch[i].id = le32_to_cpu(desc.fidr);
        s->dma_ch[i].command = le32_to_cpu(desc.ldcmd);
    }
}

/* Load new Frame Descriptors from DMA */
static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
{
    PXAFrameDescriptor desc;
    target_phys_addr_t descptr;
    int i;

    for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
        s->dma_ch[i].source = 0;

        if (!s->dma_ch[i].up)
            continue;

        if (s->dma_ch[i].branch & FBR_BRA) {
            descptr = s->dma_ch[i].branch & FBR_SRCADDR;
            if (s->dma_ch[i].branch & FBR_BINT)
                pxa2xx_dma_bs_set(s, i);
            s->dma_ch[i].branch &= ~FBR_BRA;
        } else
            descptr = s->dma_ch[i].descriptor;

        if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
                    sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size))
            continue;

        cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc));
        s->dma_ch[i].descriptor = tswap32(desc.fdaddr);
        s->dma_ch[i].source = tswap32(desc.fsaddr);
        s->dma_ch[i].id = tswap32(desc.fidr);
        s->dma_ch[i].command = tswap32(desc.ldcmd);
    }
}

/*******************************************************************
UT_array* memfrs_scan_phymem( uint64_t start_addr, uint64_t end_addr, const char* pattern )

Scan for specific pattern in the VM's physical memory

INPUT:    uint64_t start_addr,  The start address
          uint64_t end_addr,    the end address
          const char* pattern   pattern to search, support only ascii string
OUTPUT:   UT_array*,            An UT_array that contains the address of found pattern

*******************************************************************/
UT_array* memfrs_scan_phymem( uint64_t start_addr, uint64_t end_addr, const char* pattern , int length ) {
    uint64_t i;
    UT_array *match_addr;
    if(start_addr >= end_addr) {
        printf("end_addr is not less than start_addr\n");
        return NULL;
    }

    uint8_t* buf = (uint8_t*)malloc(length);
    if(buf == NULL) {
        printf("Cannot allocate memory for memfrs_scan_phymem()\n");
        return NULL;
    }

    utarray_new( match_addr, &adr_icd);

    printf("Scan for pattern %s\n", pattern);
    for(i = start_addr; i < end_addr-length+1; i++)
    {
        cpu_physical_memory_read(i, buf, length);
        if(memcmp(buf, pattern, length)==0)
        {
            printf("pattern found %lx\n", i);
            utarray_push_back(match_addr, &i);
        }
    }
    return match_addr;
}

static uint32_t mmc_fifo_pop(S5pc1xxMMCState *s, uint32_t pos)
{
    uint32_t value = 0;

    cpu_physical_memory_read(s->sysad + pos, (uint8_t *)(&value), 4);
    return value;
}

static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
{
	target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);

	/* Load and decode. FIXME: handle endianness.  */
	cpu_physical_memory_read (addr, 
				  (void *) &ctrl->channels[c].current_g, 
				  sizeof ctrl->channels[c].current_g);
}

static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
{
	hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);

	/* Load and decode. FIXME: handle endianness.  */
	D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
	cpu_physical_memory_read (addr,
				  (void *) &ctrl->channels[c].current_d, 
				  sizeof ctrl->channels[c].current_d);

	D(dump_d(c, &ctrl->channels[c].current_d));
	ctrl->channels[c].regs[RW_DATA] = addr;
}

/* Get an array of words from main memory */
static inline int get_words(OHCIState *ohci,
                            uint32_t addr, uint16_t *buf, int num)
{
    int i;

    addr += ohci->localmem_base;

    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
        cpu_physical_memory_read(addr, buf, sizeof(*buf));
        *buf = le16_to_cpu(*buf);
    }

    return 1;
}

static int pdc_start_transfer(void *opaque,
                               target_phys_addr_t tx,
                               unsigned int *tx_len,
                               target_phys_addr_t rx,
                               unsigned int *rx_len,
                               int last_transfer)
{
    SPIState *s = opaque;
    unsigned int i;
    unsigned int tlen;


    DPRINTF("pdc: start transfer, last trans %d\n", last_transfer);
#if 1
    if (tx_len == NULL) {
        DPRINTF("ignore only read request\n");
        return -1;
    }
#endif
    tlen = *tx_len;

    if (rx_len != NULL) {
        tlen = *rx_len > tlen ? *rx_len : tlen;
    }
    /* suppose that transfer 8 bit,
       TODO: fix this, extract right value from csr
    */
    s->spi_control->set_chipselect(s->spi_control->opaque, 1);
    for (i = 0; i < tlen; ++i) {
        DPRINTF("pdc: transfering\n");
        uint8_t tmp = 0;
        if (tx_len != NULL && *tx_len > 0) {
            cpu_physical_memory_read(tx, &tmp, 1);
            ++tx;
            --*tx_len;
        }
        tmp = s->spi_control->txrx_callback(s->spi_control->opaque, tmp, 8);
        s->rdr = tmp;
        if (rx_len != NULL && *rx_len > 0) {
            cpu_physical_memory_write(rx, &tmp, 1);
            ++rx;
            --*rx_len;
        }
    }

    if (last_transfer) {        
        s->spi_control->set_chipselect(s->spi_control->opaque, 0);
    }
    return 0;
}

static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
{
	target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);

	/* Load and decode. FIXME: handle endianness.  */
	D(printf("%s addr=%x\n", __func__, addr));
	cpu_physical_memory_read (addr,
				  (void *) &ctrl->channels[c].current_d, 
				  sizeof ctrl->channels[c].current_d);

	D(dump_d(c, &ctrl->channels[c].current_d));
	ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
		(uint32_t)ctrl->channels[c].current_d.buf;
}

static void bcm2708_vc_fb(struct bcm2708_vc *_vc,
		int _chan, uint32_t _msg)
{
	target_phys_addr_t dma = _msg &~ (0xc << 28);
	cpu_physical_memory_read(dma, &_vc->fb, sizeof(_vc->fb));

	// TODO: much better calculations.

	int pitch;
	switch(_vc->fb.bpp)
	{
	case 8:
		pitch = _vc->fb.xres;
		_vc->fb_bpp = BPP_8;
		break;
	
	case 16:
		pitch = _vc->fb.xres << 1;
		_vc->fb_bpp = BPP_16_565;
		break;

	case 32:
		pitch = _vc->fb.xres << 2;
		_vc->fb_bpp = BPP_32;
		break;

	default:
		pitch = _vc->fb.xres << 1;
		_vc->fb_bpp = BPP_16_565;
		break;
	}

	target_phys_addr_t fbsz = pitch*_vc->fb.yres;
	target_phys_addr_t addr = 128*1024*1024; // Currently hard-coded in kernel?

	_vc->fb_invalidate = 1;
	_vc->fb.pitch = pitch;
	_vc->fb.base = addr;
	_vc->fb.screen_size = fbsz;

	qemu_console_resize(_vc->disp, _vc->fb.xres, _vc->fb.yres);

#ifdef DEBUG_FB
	printf("fb mapped to 0x%08x (%p).\n", addr, _vc->disp);
#endif
	
	cpu_physical_memory_write(dma, &_vc->fb, sizeof(_vc->fb));
	bcm2708_vc_send(_vc, _chan, 0);
}

int
kvm_ia64_copy_from_GFW_to_nvram()
{
    struct nvram_save_addr nvram_addr_buf;
    uint8_t *nvram_buf;
    unsigned long nvram_fd;
    unsigned long type = WRITE_TO_NVRAM;
    int ret = -1;

    nvram_buf = malloc(NVRAM_SIZE);
    if (!nvram_buf)
        goto out_free;

    cpu_physical_memory_read(NVRAM_START, (uint8_t *)&nvram_addr_buf,
                             sizeof(struct nvram_save_addr));
    if (nvram_addr_buf.signature != NVRAM_VALID_SIG) {
        goto out_free;
    }

    cpu_physical_memory_read(nvram_addr_buf.addr, nvram_buf, NVRAM_SIZE);

    nvram_fd = kvm_ia64_nvram_init(type);
    if (nvram_fd  == -1)
        goto out;

    lseek(nvram_fd, 0, SEEK_SET);
    if (write(nvram_fd, nvram_buf, NVRAM_SIZE) != NVRAM_SIZE)
        goto out;

    ret = 0;
 out:
    close(nvram_fd);
 out_free:
    free(nvram_buf);
    return ret;
}

static void apic_sync_vapic(APICCommonState *s, int sync_type)
{
    VAPICState vapic_state;
    //size_t length;
    //off_t start;
    int vector;

    if (!s->vapic_paddr) {
        return;
    }
    if (sync_type & SYNC_FROM_VAPIC) {
        cpu_physical_memory_read(NULL, s->vapic_paddr, &vapic_state,
                                 sizeof(vapic_state));
        s->tpr = vapic_state.tpr;
    }
    if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) {
        //start = offsetof(VAPICState, isr);
        //length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr);

        if (sync_type & SYNC_TO_VAPIC) {
            assert(qemu_cpu_is_self(CPU(s->cpu)));

            vapic_state.tpr = s->tpr;
            vapic_state.enabled = 1;
            //start = 0;
            //length = sizeof(VAPICState);
        }

        vector = get_highest_priority_int(s->isr);
        if (vector < 0) {
            vector = 0;
        }
        vapic_state.isr = vector & 0xf0;

        vapic_state.zero = 0;

        vector = get_highest_priority_int(s->irr);
        if (vector < 0) {
            vector = 0;
        }
        vapic_state.irr = vector & 0xff;

        //cpu_physical_memory_write_rom(&address_space_memory,
        //                              s->vapic_paddr + start,
        //                              ((void *)&vapic_state) + start, length);
        // FIXME qq
    }
}

static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
{
	target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);

	/* Load and decode. FIXME: handle endianness.  */
	cpu_physical_memory_read (addr, 
				  (void *) &ctrl->channels[c].current_c, 
				  sizeof ctrl->channels[c].current_c);

	D(dump_c(c, &ctrl->channels[c].current_c));
	/* I guess this should update the current pos.  */
	ctrl->channels[c].regs[RW_SAVED_DATA] = 
		(uint32_t)ctrl->channels[c].current_c.saved_data;
	ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
		(uint32_t)ctrl->channels[c].current_c.saved_data_buf;
}

static int  goldfish_mmc_bdrv_write(struct goldfish_mmc_state *s,
                                    int64_t                    sector_number,
                                    target_phys_addr_t         dst_address,
                                    int                        num_sectors)
{
    int  ret;

    while (num_sectors > 0) {
        cpu_physical_memory_read(dst_address, s->buf, 512);

        ret = bdrv_write(s->bs, sector_number, s->buf, 1);
        if (ret < 0)
            return ret;

        dst_address   += 512;
        num_sectors   -= 1;
        sector_number += 1;
    }
    return 0;
}