本文整理汇总了C++中cpu_is_omap44xx函数的典型用法代码示例。如果您正苦于以下问题:C++ cpu_is_omap44xx函数的具体用法?C++ cpu_is_omap44xx怎么用?C++ cpu_is_omap44xx使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了cpu_is_omap44xx函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: omap_serial_init_port
/**
* omap_serial_init_port() - initialize single serial port
* @bdata: port specific board data pointer
* @info: platform specific data pointer
*
* This function initialies serial driver for given port only.
* Platforms can call this function instead of omap_serial_init()
* if they don't plan to use all available UARTs as serial ports.
*
* Don't mix calls to omap_serial_init_port() and omap_serial_init(),
* use only one of the two.
*/
void __init omap_serial_init_port(struct omap_board_data *bdata,
struct omap_uart_port_info *info)
{
struct omap_hwmod *oh;
struct omap_device *od;
struct omap_uart_port_info *pdata;
char *name = DRIVER_NAME;
if (WARN_ON(!bdata))
return;
if (WARN_ON(bdata->id < 0))
return;
if (WARN_ON(bdata->id >= OMAP_MAX_HSUART_PORTS))
return;
oh = omap_uart_hwmod_lookup(bdata->id);
if (!oh)
return;
if (info == NULL)
info = omap_serial_default_info;
pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
if (!pdata) {
pr_err("Memory allocation for UART pdata failed\n");
return;
}
if (cpu_is_omap34xx() || cpu_is_omap44xx())
pdata->errata |= UART_ERRATA_i202_MDR1_ACCESS;
omap_uart_idle_init(pdata, bdata->id);
pdata->uartclk = OMAP24XX_BASE_BAUD * 16;
pdata->flags = UPF_BOOT_AUTOCONF;
pdata->enable_wakeup = omap_uart_wakeup_enable;
pdata->use_dma = info->use_dma;
pdata->chk_wakeup = omap_uart_chk_wakeup;
pdata->dma_rx_buf_size = info->dma_rx_buf_size;
pdata->dma_rx_poll_rate = info->dma_rx_poll_rate;
pdata->dma_rx_timeout = info->dma_rx_timeout;
pdata->auto_sus_timeout = info->auto_sus_timeout;
pdata->wake_peer = info->wake_peer;
pdata->rts_mux_driver_control = info->rts_mux_driver_control;
pdata->wer = info->wer;
if (bdata->id == omap_uart_con_id) {
pdata->console_uart = true;
#ifdef CONFIG_DEBUG_LL
pdata->auto_sus_timeout = -1;
#endif
}
if (pdata->use_dma &&
cpu_is_omap44xx() && omap_rev() > OMAP4430_REV_ES1_0)
pdata->errata |= OMAP4_UART_ERRATA_i659_TX_THR;
od = omap_device_build(name, bdata->id, oh, pdata,
sizeof(*pdata), omap_uart_latency,
ARRAY_SIZE(omap_uart_latency), false);
WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
name, oh->name);
oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads) ||
(pdata->wk_en && pdata->wk_mask)) {
device_init_wakeup(&od->pdev.dev, true);
}
kfree(pdata);
}
示例2: omap3_noncore_dpll_set_rate
/**
* omap3_noncore_dpll_set_rate - set non-core DPLL rate
* @clk: struct clk * of DPLL to set
* @rate: rounded target rate
*
* Set the DPLL CLKOUT to the target rate. If the DPLL can enter
* low-power bypass, and the target rate is the bypass source clock
* rate, then configure the DPLL for bypass. Otherwise, round the
* target rate if it hasn't been done already, then program and lock
* the DPLL. Returns -EINVAL upon error, or 0 upon success.
*/
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
{
struct clk *new_parent = NULL;
u16 freqsel = 0;
struct dpll_data *dd;
int ret;
if (!clk || !rate)
return -EINVAL;
dd = clk->dpll_data;
if (!dd)
return -EINVAL;
if (rate == omap2_get_dpll_rate(clk))
return 0;
/*
* Ensure both the bypass and ref clocks are enabled prior to
* doing anything; we need the bypass clock running to reprogram
* the DPLL.
*/
omap2_clk_enable(dd->clk_bypass);
omap2_clk_enable(dd->clk_ref);
if (dd->clk_bypass->rate == rate &&
(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
ret = _omap3_noncore_dpll_bypass(clk);
if (!ret)
new_parent = dd->clk_bypass;
} else {
if (dd->last_rounded_rate != rate)
omap2_dpll_round_rate(clk, rate);
if (dd->last_rounded_rate == 0)
return -EINVAL;
/* No freqsel on OMAP4 or OMAP3630 */
if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
freqsel = _omap3_dpll_compute_freqsel(clk,
dd->last_rounded_n);
if (!freqsel)
WARN_ON(1);
}
pr_debug("clock: %s: set rate: locking rate to %lu.\n",
clk->name, rate);
ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
dd->last_rounded_n, freqsel);
if (!ret)
new_parent = dd->clk_ref;
}
if (!ret) {
/*
* Switch the parent clock in the heirarchy, and make sure
* that the new parent's usecount is correct. Note: we
* enable the new parent before disabling the old to avoid
* any unnecessary hardware disable->enable transitions.
*/
if (clk->usecount) {
omap2_clk_enable(new_parent);
omap2_clk_disable(clk->parent);
}
clk_reparent(clk, new_parent);
clk->rate = rate;
}
omap2_clk_disable(dd->clk_ref);
omap2_clk_disable(dd->clk_bypass);
return 0;
}
示例3: omap_hsmmc_reset
/**
* omap_hsmmc_reset() - Full reset of each HS-MMC controller
*
* Ensure that each MMC controller is fully reset. Controllers
* left in an unknown state (by bootloader) may prevent retention
* or OFF-mode. This is especially important in cases where the
* MMC driver is not enabled, _or_ built as a module.
*
* In order for reset to work, interface, functional and debounce
* clocks must be enabled. The debounce clock comes from func_32k_clk
* and is not under SW control, so we only enable i- and f-clocks.
**/
static void __init omap_hsmmc_reset(void)
{
u32 i, nr_controllers;
struct clk *iclk, *fclk;
if (cpu_is_omap242x())
return;
nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
(cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
for (i = 0; i < nr_controllers; i++) {
u32 v, base = 0;
struct device *dev = &dummy_pdev.dev;
switch (i) {
case 0:
base = OMAP2_MMC1_BASE;
break;
case 1:
base = OMAP2_MMC2_BASE;
break;
case 2:
base = OMAP3_MMC3_BASE;
break;
case 3:
if (!cpu_is_omap44xx())
return;
base = OMAP4_MMC4_BASE;
break;
case 4:
if (!cpu_is_omap44xx())
return;
base = OMAP4_MMC5_BASE;
break;
}
if (cpu_is_omap44xx())
base += OMAP4_MMC_REG_OFFSET;
dummy_pdev.id = i;
dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
iclk = clk_get(dev, "ick");
if (IS_ERR(iclk))
goto err1;
if (clk_enable(iclk))
goto err2;
fclk = clk_get(dev, "fck");
if (IS_ERR(fclk))
goto err3;
if (clk_enable(fclk))
goto err4;
omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
v = omap_readl(base + MMCHS_SYSSTATUS);
while (!(omap_readl(base + MMCHS_SYSSTATUS) &
MMCHS_SYSSTATUS_RESETDONE))
cpu_relax();
clk_disable(fclk);
clk_put(fclk);
clk_disable(iclk);
clk_put(iclk);
}
return;
err4:
clk_put(fclk);
err3:
clk_disable(iclk);
err2:
clk_put(iclk);
err1:
printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
"cannot reset.\n", __func__, i);
}
示例4: audit_performances
/* ------------------------------------------------------------------------*//**
* @FUNCTION audit_performances
* @BRIEF audit performances (CPU Load, C-States, OPP,
* memory bandwidth, timers, interrrupts, ...).
* @RETURNS 0 in case of success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_NOT_AVAILABLE
* @param[in] stream: output file (NULL: no output (silent))
* @param[in] duration: audit duration, in seconds (>= 1).
* @param[in] delay: initial wait delay before starting audit (in sec)
* @DESCRIPTION audit performance (CPU Load, C-States, OPP,
* memory bandwidth, timers, interrrupts, ...).
*//*------------------------------------------------------------------------ */
int audit_performances(FILE *stream, unsigned int duration, unsigned int delay)
{
int ret = 0;
unsigned short skip_proc_stats_audit = 0;
unsigned int cpu_cores_cnt = 0, cpu_online_cores_cnt = 0;
unsigned short *cpu_online = NULL;
unsigned int *idle_t0 = NULL, *iowait_t0 = NULL, *sum_t0 = NULL;
unsigned int *idle_t1 = NULL, *iowait_t1 = NULL, *sum_t1 = NULL;
unsigned int *idle_cnt = NULL, *iowait_cnt = NULL, *sum_cnt = NULL;
double *load = NULL, load_total = 0;
unsigned int cstates_nbr = 0;
uint64_t cstates_usage[MAX_CSTATE][3] = { {0} };
uint64_t cstates_time[MAX_CSTATE][3] = { {0} };
unsigned short emif = 0;
unsigned int emif_busy_cycles[2] = { 0 };
unsigned int emif_cycles[2] = { 0 };
unsigned int emif_delta_cycles = 0,
emif_delta_busy_cycles = 0;
double emif_load = 0;
uint64_t *time_in_opp_t0 = NULL;
uint64_t *time_in_opp_t1 = NULL;
uint64_t *time_in_opp_cnt = NULL;
uint64_t total_trans_t0 = 0, total_trans_t1 = 0, total_trans_cnt = 0;
unsigned int i = 0;
uint64_t sec = 0, msec = 0, usec = 0, active_c0_time = 0;
double pct = 0;
char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN];
unsigned int row = 0;
char name[16] = { 0 };
FILE *fp = NULL;
char perf_summary_file[64];
FILE *fp_irq_1 = NULL, *fp_irq_2 = NULL, *fp_timerstats = NULL;
unsigned int irq_total_count = 0, occurred_irq_count = 0, timer_count = 0;
genlist occurred_irq_list, timerstats_list;
irq_info irq_inf = { 0 };
timerstat_info timer_inf = { 0 };
char irq_snap_file1[32] = { 0 };
char irq_snap_file2[32] = { 0 };
char timerstats_file[32] = { 0 };
char timerstats_summary[256] = { 0 };
unsigned int skip_irq_audit = 0, skip_cstate_audit = 0;
int skip_timerstats_audit = 0;
char *workdir = NULL;
unsigned short skip_cpufreq_audit = 0;
unsigned int opp_cnt = 0;
if (duration == 0) {
fprintf(stream, "Duration should be at least 1 second ...\n\n");
ret = OMAPCONF_ERR_ARG;
goto audit_performances_exit;
}
if (!cpu_is_omap44xx() && !cpu_is_omap54xx()) {
fprintf(stream, "Unsupported platform, sorry...\n\n");
ret = OMAPCONF_ERR_CPU;
goto audit_performances_exit;
}
/* Retrieve a writable directory */
workdir = workdir_get();
if (workdir != NULL) {
strcpy(irq_snap_file1, workdir);
strcpy(irq_snap_file2, workdir);
strcpy(timerstats_file, workdir);
strcpy(perf_summary_file, workdir);
strcat(irq_snap_file1, "proc_interrupts_1");
strcat(irq_snap_file2, "proc_interrupts_2");
strcat(timerstats_file, "proc_timerstats");
strcat(perf_summary_file, "performance_audit_report.txt");
skip_irq_audit = 0;
skip_timerstats_audit = 0;
} else {
skip_irq_audit = 1;
skip_timerstats_audit = 1;
}
/* Open trace output file */
fp = fopen(perf_summary_file, "w");
if (fp == NULL) {
fprintf(stderr, "%s(): could not create %s!\n",
__func__, perf_summary_file);
} else {
fprintf(fp, "OMAP Performance Audit Summary\n\n");
omapconf_revision_show(fp);
chips_info_show(fp, 1);
//.........这里部分代码省略.........
示例5: omap_mcbsp_start
/*
* Here we start the McBSP, by enabling transmitter, receiver or both.
* If no transmitter or receiver is active prior calling, then sample-rate
* generator and frame sync are started.
*/
void omap_mcbsp_start(unsigned int id, int tx, int rx)
{
struct omap_mcbsp *mcbsp;
int enable_srg = 0;
u16 w;
if (!omap_mcbsp_check_valid_id(id)) {
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
return;
}
mcbsp = id_to_mcbsp_ptr(id);
if (cpu_is_omap34xx())
omap_st_start(mcbsp);
/* Only enable SRG, if McBSP is master */
w = MCBSP_READ_CACHE(mcbsp, PCR0);
if (w & (FSXM | FSRM | CLKXM | CLKRM))
enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
if (enable_srg) {
/* Start the sample generator */
w = MCBSP_READ_CACHE(mcbsp, SPCR2);
MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
}
/* Enable transmitter and receiver */
tx &= 1;
w = MCBSP_READ_CACHE(mcbsp, SPCR2);
MCBSP_WRITE(mcbsp, SPCR2, w | tx);
rx &= 1;
w = MCBSP_READ_CACHE(mcbsp, SPCR1);
MCBSP_WRITE(mcbsp, SPCR1, w | rx);
/*
* Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
* REVISIT: 100us may give enough time for two CLKSRG, however
* due to some unknown PM related, clock gating etc. reason it
* is now at 500us.
*/
udelay(500);
if (enable_srg) {
/* Start frame sync */
w = MCBSP_READ_CACHE(mcbsp, SPCR2);
MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
}
if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
/* Release the transmitter and receiver */
w = MCBSP_READ_CACHE(mcbsp, XCCR);
w &= ~(tx ? XDISABLE : 0);
MCBSP_WRITE(mcbsp, XCCR, w);
w = MCBSP_READ_CACHE(mcbsp, RCCR);
w &= ~(rx ? RDISABLE : 0);
MCBSP_WRITE(mcbsp, RCCR, w);
}
/* Dump McBSP Regs */
omap_mcbsp_dump_reg(id);
}
示例6: mod44xx_get_standby_mode
/* ------------------------------------------------------------------------*//**
* @FUNCTION mod44xx_get_standby_mode
* @BRIEF retrieve omap module's standby mode
* @RETURNS 1 if success
* 0 if omap module's registers NOT accessible
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_REG_ACCESS
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_NOT_AVAILABLE
* OMAPCONF_ERR_INTERNAL
* @param[in] module_id: omap module ID
* @param[in,out] mode: returned omap module's standby mode
* @DESCRIPTION retrieve omap module's standby mode
*//*------------------------------------------------------------------------ */
int mod44xx_get_standby_mode(mod44xx_id module_id, mod_standby_mode *mode)
{
int ret_val = 0;
unsigned int sysconfig;
mod_interface_type type;
char name[MOD44XX_MAX_NAME_LENGTH];
*mode = MOD_STANDBY_MODE_MAX;
if (!cpu_is_omap44xx()) {
fprintf(stderr, "%s(): unsupported cpu!!!\n", __func__);
ret_val = OMAPCONF_ERR_CPU;
goto mod44xx_get_standby_mode_end;
}
if (module_id >= OMAP4_MODULE_ID_MAX) {
fprintf(stderr, "%s(): incorrect module id!!! (%u)\n",
__func__, module_id);
ret_val = OMAPCONF_ERR_ARG;
goto mod44xx_get_standby_mode_end;
}
mod44xx_get_interface_type(module_id, &type);
if ((module_id != OMAP4_MPU_M3) &&
(type != MOD_INTERFACE_MASTER) &&
(type != MOD_INTERFACE_DUAL)) {
dprintf("%s(): module #%d name = %s has no master interface\n",
__func__, module_id, mod44xx_get_name(module_id, name));
ret_val = OMAPCONF_ERR_NOT_AVAILABLE;
goto mod44xx_get_standby_mode_end;
}
ret_val = mod44xx_is_accessible(module_id);
if (ret_val == 0) {
/* Module is NOT accessible */
ret_val = 0;
dprintf("%s(): module #%d name = %s is NOT accessible\n",
__func__, module_id, mod44xx_get_name(module_id, name));
goto mod44xx_get_standby_mode_end;
} else if (ret_val != 1) {
/* Internal error */
dprintf("%s(): mod44xx_is_accessible() returned with %d!!!\n",
__func__, ret_val);
goto mod44xx_get_standby_mode_end;
}
/* Module is accessible */
dprintf("%s(): module #%d name = %s is accessible\n",
__func__, module_id, mod44xx_get_name(module_id, name));
if ((module_id != OMAP4_MPU_M3) &&
(mod44xx_info_table[module_id].sysconfig_addr == NULL)) {
fprintf(stderr,
"%s(): error module %s interface type is not NONE but SYSCONFIG ADDR == NULL\n",
__func__, mod44xx_get_name(module_id, name));
ret_val = OMAPCONF_ERR_INTERNAL;
goto mod44xx_get_standby_mode_end;
}
if (module_id != OMAP4_MPU_M3) {
OMAP_READREG((unsigned int)
mod44xx_info_table[module_id].sysconfig_addr,
sysconfig);
dprintf("%s(): SYSCONFIG ADDR = 0x%08X SYSCONFIG = 0x%08X\n",
__func__, (unsigned int)
mod44xx_info_table[module_id].sysconfig_addr,
sysconfig);
} else {
OMAP_READREG((unsigned int) OMAP4430_STANDBY_CORE_SYSCONFIG,
sysconfig);
dprintf(
"%s(): SYSCONFIG ADDR = 0x%08X, STANDBY_CORE_SYSCONFIG = 0x%08X\n",
__func__, (unsigned int) OMAP4430_IDLE_CORE_SYSCONFIG,
sysconfig);
}
/* Check module's standby mode */
switch (module_id) {
case OMAP4_IVAHD:
case OMAP4_ICONT1:
case OMAP4_ICONT2:
case OMAP4_VDMA:
case OMAP4_IME3:
case OMAP4_ILF3:
case OMAP4_AESS:
//.........这里部分代码省略.........
示例7: usb_musb_init
void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
{
struct omap_hwmod *oh;
struct omap_device *od;
struct platform_device *pdev;
struct device *dev = NULL;
int bus_id = -1;
const char *oh_name, *name;
struct omap_musb_board_data *board_data;
if (musb_board_data)
board_data = musb_board_data;
else
board_data = &musb_default_board_data;
/*
* REVISIT: This line can be removed once all the platforms using
* musb_core.c have been converted to use use clkdev.
*/
musb_plat.clock = "ick";
musb_plat.board_data = board_data;
musb_plat.power = board_data->power >> 1;
musb_plat.mode = board_data->mode;
musb_plat.extvbus = board_data->extvbus;
if (cpu_is_omap44xx())
omap4430_phy_init(dev); /* power down the phy */
if (cpu_is_omap3517() || cpu_is_omap3505()) {
oh_name = "am35x_otg_hs";
name = "musb-am35x";
} else {
oh_name = "usb_otg_hs";
name = "musb-omap2430";
}
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("Could not look up %s\n", oh_name);
return;
}
od = omap_device_build(name, bus_id, oh, &musb_plat,
sizeof(musb_plat), omap_musb_latency,
ARRAY_SIZE(omap_musb_latency), false);
if (IS_ERR(od)) {
pr_err("Could not build omap_device for %s %s\n",
name, oh_name);
return;
}
pdev = &od->pdev;
dev = &pdev->dev;
get_device(dev);
dev->dma_mask = &musb_dmamask;
dev->coherent_dma_mask = musb_dmamask;
put_device(dev);
if (cpu_is_omap44xx())
omap4430_phy_init(dev);
#ifdef CONFIG_USB_ANDROID_SAMSUNG_COMPOSITE
platform_device_register(&android_usb_device);
#endif
}
示例8: mod44xx_get_autoidle_mode
/* ------------------------------------------------------------------------*//**
* @FUNCTION mod44xx_get_autoidle_mode
* @BRIEF retrieve omap module's autoidle mode
* @RETURNS 1 if success
* 0 if omap module's registers NOT accessible
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_REG_ACCESS
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_NOT_AVAILABLE
* OMAPCONF_ERR_INTERNAL
* @param[in] module_id: omap module ID
* @param[in,out] mode: returned omap module's autoidle mode
* @DESCRIPTION retrieve omap module's autoidle mode
*//*------------------------------------------------------------------------ */
int mod44xx_get_autoidle_mode(mod44xx_id module_id,
mod_autoidle_mode *mode)
{
int ret_val = 0;
unsigned int sysconfig;
char name[MOD44XX_MAX_NAME_LENGTH];
mod_interface_type type;
*mode = MOD_AUTOIDLE_MODE_MAX;
if (!cpu_is_omap44xx())
return OMAPCONF_ERR_CPU;
if (module_id >= OMAP4_MODULE_ID_MAX)
return OMAPCONF_ERR_ARG;
mod44xx_get_interface_type(module_id, &type);
if (type == MOD_INTERFACE_NONE) {
dprintf("%s(): module #%d name = %s has no SYSCONFIG\n",
__func__, module_id,
mod44xx_get_name(module_id, name));
return OMAPCONF_ERR_NOT_AVAILABLE;
}
ret_val = mod44xx_is_accessible(module_id);
if (ret_val == 1) {
/* Module is accessible */
dprintf("%s(): module #%d name = %s is accessible\n",
__func__, module_id,
mod44xx_get_name(module_id, name));
if (mod44xx_info_table[module_id].sysconfig_addr != NULL) {
OMAP_READREG((unsigned int)
mod44xx_info_table[module_id].sysconfig_addr,
sysconfig);
dprintf(
"%s(): SYSCONFIG ADDR = 0x%08X SYSCONFIG = 0x%08X\n",
__func__,
(unsigned int)
mod44xx_info_table[module_id].sysconfig_addr,
sysconfig);
/* Check module's autoidle bit */
switch (module_id) {
case OMAP4_CONTROL_GEN_WKUP:
case OMAP4_CONTROL_PADCONF_WKUP:
case OMAP4_SYNCTIMER:
case OMAP4_WDT2:
case OMAP4_WDT3:
case OMAP4_TIMER3:
case OMAP4_TIMER4:
case OMAP4_TIMER5:
case OMAP4_TIMER6:
case OMAP4_TIMER7:
case OMAP4_TIMER8:
case OMAP4_TIMER9:
case OMAP4_TIMER11:
case OMAP4_MCASP:
case OMAP4_IVAHD:
case OMAP4_ICONT1:
case OMAP4_ICONT2:
case OMAP4_VDMA:
case OMAP4_IME3:
case OMAP4_ILF3:
case OMAP4_MC3:
case OMAP4_CALC3:
case OMAP4_ECD3:
case OMAP4_SMARTREFLEX_CORE:
case OMAP4_SMARTREFLEX_MPU:
case OMAP4_SMARTREFLEX_IVA:
case OMAP4_CONTROL_GEN_CORE:
case OMAP4_CONTROL_PADCONF_CORE:
case OMAP4_SYSTEM_MAILBOX:
case OMAP4_DMM:
case OMAP4_AESS:
case OMAP4_SIMCOP:
case OMAP4_SIMCOP_DMA:
case OMAP4_FDIF:
case OMAP4_HDMI:
case OMAP4_GFX:
case OMAP4_MMC1_HL:
case OMAP4_MMC2_HL:
case OMAP4_MMC3_HL:
case OMAP4_MMC4_HL:
case OMAP4_MMC5_HL:
//.........这里部分代码省略.........
示例9: mod44xx_get_idle_mode
/* ------------------------------------------------------------------------*//**
* @FUNCTION mod44xx_get_idle_mode
* @BRIEF retrieve omap module's idle mode
* @RETURNS 1 if success
* 0 if omap module's registers NOT accessible
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_REG_ACCESS
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_NOT_AVAILABLE
* OMAPCONF_ERR_INTERNAL
* @param[in] module_id: omap module ID
* @param[in,out] mode: returned omap module's idle mode
* @DESCRIPTION retrieve omap module's idle mode
*//*------------------------------------------------------------------------ */
int mod44xx_get_idle_mode(mod44xx_id module_id, mod_idle_mode *mode)
{
int ret_val = 0;
unsigned int sysconfig;
mod_interface_type type;
char name[MOD44XX_MAX_NAME_LENGTH];
*mode = MOD_IDLE_MODE_MAX;
if (!cpu_is_omap44xx()) {
fprintf(stderr, "%s(): unsupported cpu!!!\n", __func__);
ret_val = OMAPCONF_ERR_CPU;
goto mod44xx_get_idle_mode_end;
}
if (module_id >= OMAP4_MODULE_ID_MAX) {
fprintf(stderr, "%s(): incorrect module id!!! (%u)\n",
__func__, module_id);
ret_val = OMAPCONF_ERR_ARG;
goto mod44xx_get_idle_mode_end;
}
mod44xx_get_interface_type(module_id, &type);
if ((module_id != OMAP4_MPU_M3) &&
(type != MOD_INTERFACE_SLAVE) && (type != MOD_INTERFACE_DUAL)) {
dprintf("%s(): module #%d name = %s has no slave interface\n",
__func__, module_id, mod44xx_get_name(module_id, name));
ret_val = OMAPCONF_ERR_NOT_AVAILABLE;
goto mod44xx_get_idle_mode_end;
}
ret_val = mod44xx_is_accessible(module_id);
if (ret_val == 0) {
/* Module is NOT accessible */
ret_val = 0;
dprintf("%s(): module #%d name = %s is NOT accessible\n",
__func__, module_id, mod44xx_get_name(module_id, name));
goto mod44xx_get_idle_mode_end;
} else if (ret_val != 1) {
/* internal error */
dprintf("%s(): mod44xx_is_accessible() returned with %d!!!\n",
__func__, ret_val);
goto mod44xx_get_idle_mode_end;
}
/* Module is accessible */
dprintf("%s(): module #%d name = %s is accessible\n",
__func__, module_id, mod44xx_get_name(module_id, name));
if ((module_id != OMAP4_MPU_M3) &&
(mod44xx_info_table[module_id].sysconfig_addr == NULL)) {
fprintf(stderr,
"%s(): error module %s interface type is not NONE but SYSCONFIG ADDR == NULL\n",
__func__, mod44xx_get_name(module_id, name));
ret_val = OMAPCONF_ERR_INTERNAL;
goto mod44xx_get_idle_mode_end;
}
if (module_id != OMAP4_MPU_M3) {
OMAP_READREG((unsigned int)
mod44xx_info_table[module_id].sysconfig_addr,
sysconfig);
dprintf("%s(): SYSCONFIG ADDR = 0x%08X, SYSCONFIG = 0x%08X\n",
__func__, (unsigned int)
mod44xx_info_table[module_id].sysconfig_addr,
sysconfig);
} else {
OMAP_READREG((unsigned int) OMAP4430_IDLE_CORE_SYSCONFIG,
sysconfig);
dprintf(
"%s(): SYSCONFIG ADDR = 0x%08X, IDLE_CORE_SYSCONFIG = 0x%08X\n",
__func__, (unsigned int) OMAP4430_IDLE_CORE_SYSCONFIG,
sysconfig);
}
/* get module's idle mode */
switch (module_id) {
case OMAP4_MCASP:
case OMAP4_MPU_M3:
*mode = (mod_idle_mode) extract_bitfield(sysconfig, 0, 2);
ret_val = 1;
dprintf("%s(): module %s idle mode (bits [1:0])=%d\n",
__func__, mod44xx_get_name(module_id, name), *mode);
break;
case OMAP4_CONTROL_GEN_WKUP:
//.........这里部分代码省略.........
示例10: mod44xx_is_accessible
/* ------------------------------------------------------------------------*//**
* @FUNCTION mod44xx_is_accessible
* @BRIEF check omap module's registers accessibility
* @RETURNS 1 if omap module's registers accessible
* 0 if omap module's registers NOT accessible
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_REG_ACCESS
* OMAPCONF_ERR_CPU
* @param[in] module_id: omap module ID
* @DESCRIPTION check omap module's registers accessibility
*//*------------------------------------------------------------------------ */
int mod44xx_is_accessible(mod44xx_id module_id)
{
unsigned int cm_clkctrl_addr, cm_clkctrl;
int ret = 0;
mod_module_mode mmode;
#ifdef MODULE44XX_DEBUG
char name[MOD44XX_MAX_NAME_LENGTH];
#endif
if (!cpu_is_omap44xx()) {
fprintf(stderr, "%s(): cpu is not omap44xx!!!\n", __func__);
ret = OMAPCONF_ERR_CPU;
goto mod44xx_is_accessible_exit;
}
if (module_id >= OMAP4_MODULE_ID_MAX) {
fprintf(stderr, "%s(): module_id >= OMAP4_MODULE_ID_MAX!!!\n",
__func__);
ret = OMAPCONF_ERR_ARG;
goto mod44xx_is_accessible_exit;
}
/* Retrieve module mode */
mod44xx_get_mode(module_id, &mmode);
if (mmode == MOD_DISABLED_MODE) {
dprintf(
"%s(): module #%d name = %s mode is disabled => NOT accessible\n",
__func__,
module_id, mod44xx_get_name(module_id, name));
ret = 0;
goto mod44xx_is_accessible_exit;
} else if (mmode == MOD_ENABLED_MODE) {
dprintf(
"%s(): module #%d name = %s mode is enabled => accessible\n",
__func__,
module_id, mod44xx_get_name(module_id, name));
ret = 1;
goto mod44xx_is_accessible_exit;
}
/* Module mode is HW Auto, need to check status */
/* Retrieve CM_CLKCTRL address */
cm_clkctrl_addr = (unsigned int)
mod44xx_info_table[module_id].cm_clkctrl_addr;
dprintf("%s(): module #%d name = %s CM_CLKCTRL ADDR = 0x%08X\n",
__func__, module_id, mod44xx_get_name(module_id, name),
cm_clkctrl_addr);
/* Retrieve module state */
if ((void *) cm_clkctrl_addr != NULL) {
if (mem_read(cm_clkctrl_addr, &cm_clkctrl) != 0) {
fprintf(stderr, "%s(): could not read register!!!\n",
__func__);
ret = OMAPCONF_ERR_REG_ACCESS;
goto mod44xx_is_accessible_exit;
}
dprintf(
"%s(): CM_CLKCTRL ADDR = 0x%08X CM_CLKCTRL = 0x%08X IDLEST = %d\n",
__func__, (unsigned int)
mod44xx_info_table[module_id].cm_clkctrl_addr,
cm_clkctrl, extract_bitfield(cm_clkctrl, 16, 2));
/* Check if module is accessible */
switch (extract_bitfield(cm_clkctrl, 16, 2)) {
case 0:
/* Module is fully functional, including OCP */
dprintf(
"%s(): module is fully functional, including OCP\n",
__func__);
ret = 1;
break;
case 1:
/*
* Module is performing transition: wakeup, or sleep,
* or sleep abortion
*/
dprintf(
"%s(): module is performing transition: wakeup, or sleep, or sleep abortion\n",
__func__);
ret = 0;
break;
case 2:
/* Module is in Idle mode (only OCP part) */
dprintf(
"%s(): module is in Idle mode (only OCP part)\n",
__func__);
ret = 0;
break;
case 3:
//.........这里部分代码省略.........
示例11: mod44xx_get_clock_activity_mode
/* ------------------------------------------------------------------------*//**
* @FUNCTION mod44xx_get_clock_activity_mode
* @BRIEF retrieve omap module's clockactivity mode
* @RETURNS 1 if success
* 0 if omap module's registers NOT accessible
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_REG_ACCESS
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_NOT_AVAILABLE
* OMAPCONF_ERR_INTERNAL
* @param[in] module_id: omap module ID
* @param[in,out] mode: returned omap module's clockactivity mode
* @DESCRIPTION retrieve omap module's clockactivity mode
*//*------------------------------------------------------------------------ */
int mod44xx_get_clock_activity_mode(mod44xx_id module_id,
mod_clock_activity_mode *mode)
{
int ret_val = 0;
unsigned int sysconfig;
char name[MOD44XX_MAX_NAME_LENGTH];
*mode = MOD_CLOCK_ACTIVITY_MODE_MAX;
if (!cpu_is_omap44xx())
return OMAPCONF_ERR_CPU;
if (module_id >= OMAP4_MODULE_ID_MAX)
return OMAPCONF_ERR_ARG;
if (mod44xx_has_clockactivity_bit(module_id) != 1)
return OMAPCONF_ERR_NOT_AVAILABLE;
ret_val = mod44xx_is_accessible(module_id);
if (ret_val == 1) {
/* Module is accessible */
dprintf("%s(): module #%d name = %s is accessible\n",
__func__, module_id,
mod44xx_get_name(module_id, name));
if (mod44xx_info_table[module_id].sysconfig_addr != NULL) {
OMAP_READREG((unsigned int)
mod44xx_info_table[module_id].sysconfig_addr,
sysconfig);
dprintf(
"%s(): SYSCONFIG ADDR = 0x%08X SYSCONFIG = 0x%08X\n",
__func__, (unsigned int)
mod44xx_info_table[module_id].sysconfig_addr,
sysconfig);
/* Check module's idle mode */
switch (module_id) {
case OMAP4_SPINLOCK:
case OMAP4_ELM:
*mode = (mod_clock_activity_mode)
extract_bit(sysconfig, 8);
ret_val = 1;
dprintf(
"%s(): module %s clockactivity bit 8 = %d\n",
__func__,
mod44xx_get_name(module_id, name),
*mode);
break;
default:
*mode = (mod_clock_activity_mode)
extract_bitfield(sysconfig, 8, 2);
ret_val = 1;
dprintf(
"%s(): module %s clockactivity (bits [9:8]) = %d\n",
__func__,
mod44xx_get_name(module_id, name),
*mode);
}
} else {
fprintf(stderr,
"%s(): error module's %s interface type is not NONE but SYSCONFIG ADDR == NULL\n",
__func__, mod44xx_get_name(module_id, name));
ret_val = OMAPCONF_ERR_INTERNAL;
}
} else if (ret_val == 0) {
/* Module is NOT accessible */
ret_val = 0;
dprintf("%s(): module is NOT accessible\n", __func__);
} else {
/* internal error */
dprintf("%s(): mod44xx_is_accessible() returned with %d\n",
__func__, ret_val);
}
return ret_val;
}
示例12: help
//.........这里部分代码省略.........
"omapconf write PM_MPU_PWRSTCTRL 0xDEADBEEF\n");
printf("\n\tomapconf set bit [0x<physical address> | <name>] "
"<position>"
"\n");
printf("\t Set bit at <position> into any OMAP memory "
"address (register), given its <physical address> "
"or <name> as listed in TRM.\n");
printf("\t e.g: omapconf set bit 0x4A306300 1, "
"omapconf set bit PM_MPU_PWRSTCTRL 1\n");
printf("\n\tomapconf clear bit [0x<physical address> | <name>] "
"<position>\n");
printf("\t Clear bit at <position> into any OMAP memory "
"address (register), given its <physical address> "
"or <name> as listed in TRM.\n");
printf("\t e.g: omapconf clear bit 0x4A306300 1, "
"omapconf clear bit PM_MPU_PWRSTCTRL 1\n");
printf("\n\tomapconf dump 0x<start address> 0x<end address>\n");
printf("\t Dump a range of OMAP memory addresses, from "
"<start address> to <end address>.\n");
printf("\t Note all addresses within given range must be "
"valid and accessible.\n");
printf("\t e.g: omapconf dump 0x48243400 0x4824340C\n");
}
if ((cat == HELP_ALL) || (cat == HELP_RW) || (cat == HELP_I2C_RW)) {
printf("\n\t### WARNING ###: use the following I2C "
"[read | write] commands at your own risk!\n");
printf("\tNo address check done, may generate:\n");
printf("\t - I2C bus error (invalid or not accessible "
"<physical address>,\n");
printf("\t - platform crash/hang (bad <value>).\n");
printf("\n\tomapconf read i2c <bus> 0x<chip-addr> 0x<addr>\n");
printf("\t Read I2C register at address <addr> from I2C chip"
" at <chip-addr> on I2C <bus>.\n");
printf("\t e.g: omapconf i2c read 1 0x49 0x02\n");
printf("\n\tomapconf write i2c <bus> 0x<chip-addr> 0x<addr> "
"0x<value>\n");
printf("\t Write <value> in I2C register at address <addr> "
"from I2C chip at <chip-addr> on I2C <bus>.\n");
printf("\t e.g: omapconf i2c write 1 0x49 0x02 0xAA\n");
}
if ((cat == HELP_RW) || (cat == HELP_I2C_RW) ||
(cat == HELP_FORCEDETECT))
goto help_end;
/* OMAP4-specific commands */
if (cpu_is_omap44xx())
help44xx(cat, "all");
/* OMAP5-specific commands */
if (cpu_is_omap54xx())
help54xx(cat, "None");
/* DRA7-specific commands */
if (cpu_is_dra7xx())
help_dra7xx(cat, "None");
if (cat == HELP_ALL) {
printf("\nREPORTING BUGS\n");
printf("\tReport bugs to <[email protected]> "
"mailing-list.\n");
printf("\tYou do not have to be subsribed to the list to send "
"a message there.\n");
printf("\nSUGGESTIONS\n");
printf("\tSuggest any new idea to "
"<[email protected]> mailing-list.\n");
printf("\tYou do not have to be subsribed to the list to send "
"a message there.\n");
printf("\nCONTRIBUTIONS\n");
printf("\tSend patch to <[email protected]> "
"mailing-list.\n");
printf("\tYou do not have to be subsribed to the list to send "
"a message there.\n");
printf("\nNOTIFICATIONS\n");
printf("\tSubscribe to <[email protected]> "
"mailing-list for automatic update notification.\n");
printf("\tYou do not have to be subsribed to the list to send "
"a message there.\n");
printf("\nFURTHER DOCUMENTATION\n");
printf("\tVisit omapconf wiki:\n");
printf("\t\t<https://github.com/omapconf/omapconf/wiki>\n");
printf("\n");
}
help_end:
return;
}
示例13: vdd_opp_store
static ssize_t vdd_opp_store(struct kobject *kobj, struct kobj_attribute *attr,
const char *buf, size_t n)
{
unsigned long value;
static unsigned long prev_mpu_freq = 0;
if (sscanf(buf, "%lu", &value) != 1)
return -EINVAL;
if (attr == &tick_control_attr) {
if (value == 1)
tick_nohz_disable(1);
else if (value == 0)
tick_nohz_disable(0);
}
/* Check locks */
if (attr == &vdd1_lock_attr) {
if (vdd1_locked) {
/* vdd1 currently locked */
if (value == 0) {
omap_pm_cpu_set_freq(prev_mpu_freq * 1000);
vdd1_locked = 0;
return n;
} else {
printk(KERN_ERR "%s: vdd1 already locked to %d\n", __func__, vdd1_locked);
return -EINVAL;
}
} else {
/* vdd1 currently unlocked */
if (value != 0) {
u8 i = 0;
unsigned long freq = 0;
struct cpufreq_frequency_table *freq_table = *omap_pm_cpu_get_freq_table();
if (freq_table == NULL) {
printk(KERN_ERR "%s: Could not get freq_table\n", __func__);
return -ENODEV;
}
for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
if (freq_table[i].index == value - 1) {
freq = freq_table[i].frequency;
break;
}
}
if (freq_table[i].frequency == CPUFREQ_TABLE_END) {
printk(KERN_ERR "%s: Invalid value [0..%d]\n", __func__, i-1);
return -EINVAL;
}
prev_mpu_freq = omap_pm_cpu_get_freq();
omap_pm_cpu_set_freq(freq * 1000);
vdd1_locked = value;
} else {
printk(KERN_ERR "%s: vdd1 already unlocked\n", __func__);
return -EINVAL;
}
}
} else if (attr == &vdd2_lock_attr) {
if (vdd2_locked) {
/* vdd2 currently locked */
if (value == 0) {
int tmp_lock = vdd2_locked;
vdd2_locked = 0;
if (omap_pm_set_min_bus_tput(&sysfs_cpufreq_dev, OCP_INITIATOR_AGENT, -1)) {
printk(KERN_ERR "%s: Failed to remove vdd2_lock\n", __func__);
vdd2_locked = tmp_lock; /* restore previous lock */
} else {
return n;
}
} else {
printk(KERN_ERR "%s: vdd2 already locked to %d\n", __func__, vdd2_locked);
return -EINVAL;
}
} else {
/* vdd2 currently unlocked */
if (value != 0) {
unsigned long freq = 0;
if (cpu_is_omap3630()) {
if(value == 1) {
freq = 100*1000*4;
} else if (value == 2) {
freq = 200*1000*4;
} else {
printk(KERN_ERR "%s: Invalid value [1,2]\n", __func__);
return -EINVAL;
}
}
else if (cpu_is_omap44xx()) {
if (omap_rev() <= OMAP4430_REV_ES2_0) {
if(value == 1) {
freq = 100*1000*4;
} else if (value == 2) {
freq = 200*1000*4;
} else {
printk(KERN_ERR "%s: Invalid value [1,2]\n", __func__);
return -EINVAL;
}
} else {
if(value == 1) {
freq = 98304*4;
} else if (value == 2) {
freq = 100*1000*4;
//.........这里部分代码省略.........
示例14: dss_init_overlays
void dss_init_overlays(struct platform_device *pdev)
{
int i, r;
INIT_LIST_HEAD(&overlay_list);
num_overlays = 0;
for (i = 0; i < MAX_DSS_OVERLAYS; ++i) {
struct omap_overlay *ovl;
ovl = kzalloc(sizeof(*ovl), GFP_KERNEL);
BUG_ON(ovl == NULL);
mutex_init(&ovl->lock);
mutex_lock(&ovl->lock);
switch (i) {
case 0:
ovl->name = "gfx";
ovl->id = OMAP_DSS_GFX;
ovl->supported_modes = (cpu_is_omap44xx() |
cpu_is_omap34xx()) ?
OMAP_DSS_COLOR_GFX_OMAP3 :
OMAP_DSS_COLOR_GFX_OMAP2;
ovl->caps = OMAP_DSS_OVL_CAP_DISPC;
ovl->info.global_alpha = 255;
ovl->info.zorder = OMAP_DSS_OVL_ZORDER_3;
break;
case 1:
ovl->name = "vid1";
ovl->id = OMAP_DSS_VIDEO1;
ovl->supported_modes = (cpu_is_omap44xx() |
cpu_is_omap34xx()) ?
OMAP_DSS_COLOR_VID1_OMAP3 :
OMAP_DSS_COLOR_VID_OMAP2;
ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
OMAP_DSS_OVL_CAP_DISPC;
ovl->info.yuv2rgb_conv.type =
OMAP_DSS_COLOR_CONV_BT601_5_LR;
ovl->info.yuv2rgb_conv.dirty = true;
ovl->info.global_alpha = 255;
ovl->info.zorder = OMAP_DSS_OVL_ZORDER_2;
break;
case 2:
ovl->name = "vid2";
ovl->id = OMAP_DSS_VIDEO2;
ovl->supported_modes = (cpu_is_omap44xx() |
cpu_is_omap34xx()) ?
OMAP_DSS_COLOR_VID2_OMAP3 :
OMAP_DSS_COLOR_VID_OMAP2;
ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
OMAP_DSS_OVL_CAP_DISPC;
ovl->info.yuv2rgb_conv.type =
OMAP_DSS_COLOR_CONV_BT601_5_LR;
ovl->info.yuv2rgb_conv.dirty = true;
ovl->info.global_alpha = 255;
ovl->info.zorder = OMAP_DSS_OVL_ZORDER_1;
break;
case 3:
ovl->name = "vid3";
ovl->id = OMAP_DSS_VIDEO3;
ovl->supported_modes = OMAP_DSS_COLOR_VID3_OMAP3;
ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
OMAP_DSS_OVL_CAP_DISPC;
ovl->info.yuv2rgb_conv.type =
OMAP_DSS_COLOR_CONV_BT601_5_LR;
ovl->info.yuv2rgb_conv.dirty = true;
ovl->info.global_alpha = 255;
ovl->info.zorder = OMAP_DSS_OVL_ZORDER_0;
}
ovl->info.min_x_decim = ovl->info.min_y_decim = 1;
ovl->info.max_x_decim = ovl->info.max_y_decim =
cpu_is_omap44xx() ? 16 : 1;
ovl->info_dirty = true;
ovl->set_manager = &omap_dss_set_manager;
ovl->unset_manager = &omap_dss_unset_manager;
ovl->set_overlay_info = &dss_ovl_set_overlay_info;
ovl->get_overlay_info = &dss_ovl_get_overlay_info;
ovl->wait_for_go = &dss_ovl_wait_for_go;
omap_dss_add_overlay(ovl);
dispc_overlays[i] = ovl;
r = kobject_init_and_add(&ovl->kobj, &overlay_ktype,
&pdev->dev.kobj, "overlay%d", i);
if (r)
DSSERR("failed to create sysfs file\n");
mutex_unlock(&ovl->lock);
}
#ifdef L4_EXAMPLE
{
struct omap_overlay *ovl;
ovl = kzalloc(sizeof(*ovl), GFP_KERNEL);
//.........这里部分代码省略.........
示例15: omap_hsmmc_pdata_init
static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
struct omap_mmc_platform_data *mmc)
{
char *hc_name;
hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
if (!hc_name) {
pr_err("Cannot allocate memory for controller slot name\n");
kfree(hc_name);
return -ENOMEM;
}
if (c->name)
strncpy(hc_name, c->name, HSMMC_NAME_LEN);
else
snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
c->mmc, 1);
mmc->slots[0].name = hc_name;
mmc->nr_slots = 1;
mmc->slots[0].caps = c->caps;
mmc->slots[0].pm_caps = c->pm_caps;
mmc->slots[0].internal_clock = !c->ext_clock;
mmc->dma_mask = 0xffffffff;
mmc->max_freq = c->max_freq;
if (cpu_is_omap44xx())
mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
else
mmc->reg_offset = 0;
mmc->get_context_loss_count = hsmmc_get_context_loss;
mmc->slots[0].switch_pin = c->gpio_cd;
mmc->slots[0].gpio_wp = c->gpio_wp;
mmc->slots[0].remux = c->remux;
mmc->slots[0].init_card = c->init_card;
if (c->cover_only)
mmc->slots[0].cover = 1;
if (c->nonremovable)
mmc->slots[0].nonremovable = 1;
if (c->power_saving)
mmc->slots[0].power_saving = 1;
if (c->no_off)
mmc->slots[0].no_off = 1;
if (c->no_off_init)
mmc->slots[0].no_regulator_off_init = c->no_off_init;
if (c->vcc_aux_disable_is_sleep)
mmc->slots[0].vcc_aux_disable_is_sleep = 1;
/*
* NOTE: MMC slots should have a Vcc regulator set up.
* This may be from a TWL4030-family chip, another
* controllable regulator, or a fixed supply.
*
* temporary HACK: ocr_mask instead of fixed supply
*/
if (cpu_is_omap3505() || cpu_is_omap3517())
mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
MMC_VDD_26_27 |
MMC_VDD_27_28 |
MMC_VDD_29_30 |
MMC_VDD_30_31 |
MMC_VDD_31_32;
else
mmc->slots[0].ocr_mask = c->ocr_mask;
if (!cpu_is_omap3517() && !cpu_is_omap3505())
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
switch (c->mmc) {
case 1:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* on-chip level shifting via PBIAS0/PBIAS1 */
if (cpu_is_omap44xx()) {
mmc->slots[0].before_set_reg =
omap4_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap4_hsmmc1_after_set_reg;
} else {
mmc->slots[0].before_set_reg =
omap_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap_hsmmc1_after_set_reg;
}
}
if (cpu_is_omap3517() || cpu_is_omap3505())
mmc->slots[0].set_power = nop_mmc_set_power;
/* OMAP3630 HSMMC1 supports only 4-bit */
if (cpu_is_omap3630() &&
//.........这里部分代码省略.........