C++ cpu_is_omap446x函数代码示例

int __init omap_twl4030_init(void)
{
    /* Reuse OMAP3430 values */
    if (cpu_is_omap3630()) {
        omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
        omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
        omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
        omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
    }

    if (cpu_is_omap446x()) {
        /* use SMPS1  for CORE instead of SMPS3 on 4430 */
        omap_twl_map[1].pmic_data->volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG;
        omap_twl_map[1].pmic_data->cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG;
        /* Adjust min / max voltages */
        omap_twl_map[0].pmic_data->vp_vddmin = OMAP4460_VP_MPU_VLIMITTO_VDDMIN;
        omap_twl_map[0].pmic_data->vp_vddmax = OMAP4460_VP_MPU_VLIMITTO_VDDMAX;
        omap_twl_map[1].pmic_data->vp_vddmin = OMAP4460_VP_CORE_VLIMITTO_VDDMIN;
        omap_twl_map[1].pmic_data->vp_vddmax = OMAP4460_VP_CORE_VLIMITTO_VDDMAX;
        omap_twl_map[2].pmic_data->vp_vddmin = OMAP4460_VP_IVA_VLIMITTO_VDDMIN;
        omap_twl_map[2].pmic_data->vp_vddmax = OMAP4460_VP_IVA_VLIMITTO_VDDMAX;
    }

    if (cpu_is_omap34xx())
        return omap_pmic_register_data(omap3_twl_map);
    else if (cpu_is_omap443x())
        return omap_pmic_register_data(&omap_twl_map[0]);
    else if (cpu_is_omap446x()) /* mpu from tps6236x */
        return omap_pmic_register_data(&omap_twl_map[1]);
    else
        return 0;
}

static void __init omap4_panda_init(void)
{
	int package = OMAP_PACKAGE_CBS;
	int ret;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		package = OMAP_PACKAGE_CBL;

	omap_emif_set_device_details(1, &lpddr2_elpida_2G_S4_x2_info,
			lpddr2_elpida_2G_S4_timings,
			ARRAY_SIZE(lpddr2_elpida_2G_S4_timings),
			&lpddr2_elpida_S4_min_tck,
			&custom_configs);

	omap_emif_set_device_details(2, &lpddr2_elpida_2G_S4_x2_info,
			lpddr2_elpida_2G_S4_timings,
			ARRAY_SIZE(lpddr2_elpida_2G_S4_timings),
			&lpddr2_elpida_S4_min_tck,
			&custom_configs);

	if (cpu_is_omap446x())
		gpio_leds[0].gpio = 110;

	omap4_mux_init(board_mux, NULL, package);

	omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);

	omap_register_mac_device_fixup_paths(panda_fixup_mac_device_paths,
				     ARRAY_SIZE(panda_fixup_mac_device_paths));

	ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
	if (ret)
		pr_err("error setting wl12xx data: %d\n", ret);

	omap4_panda_init_rev();
	omap4_panda_i2c_init();
	platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
	platform_device_register(&omap_vwlan_device);
	omap_serial_init();
	omap_sdrc_init(NULL, NULL);
	omap4_twl6030_hsmmc_init(mmc);
	omap4_ehci_init();
	usb_musb_init(&musb_board_data);
	omap4_panda_display_init();
#ifdef CONFIG_MACH_OMAP4_PANDA_CAMERA_SUPPORT
	panda_camera_init(&panda_camera_board_info);
#endif
	if (cpu_is_omap446x()) {
		/* Vsel0 = gpio, vsel1 = gnd */
		ret = omap_tps6236x_board_setup(true, TPS62361_GPIO, -1,
				OMAP_PIN_OFF_OUTPUT_HIGH, -1);
		if (ret)
			pr_err("TPS62361 initialization failed: %d\n", ret);
	}
	omap_enable_smartreflex_on_init();
}

void __init omap44xx_voltagedomains_init(void)
{
	struct voltagedomain *voltdm;
	int i;

	/*
	 * XXX Will depend on the process, validation, and binning
	 * for the currently-running IC
	 */
#ifdef CONFIG_PM_OPP
	if (cpu_is_omap443x()) {
		omap4_voltdm_mpu.volt_data = omap443x_vdd_mpu_volt_data;
		omap4_voltdm_iva.volt_data = omap443x_vdd_iva_volt_data;
		omap4_voltdm_core.volt_data = omap443x_vdd_core_volt_data;
	} else if (cpu_is_omap446x()) {
		omap4_voltdm_mpu.volt_data = omap446x_vdd_mpu_volt_data;
		omap4_voltdm_iva.volt_data = omap446x_vdd_iva_volt_data;
		omap4_voltdm_core.volt_data = omap446x_vdd_core_volt_data;
	}
#endif

	omap4_voltdm_mpu.vp_param = &omap4_mpu_vp_data;
	omap4_voltdm_iva.vp_param = &omap4_iva_vp_data;
	omap4_voltdm_core.vp_param = &omap4_core_vp_data;

	omap4_voltdm_mpu.vc_param = &omap4_mpu_vc_data;
	omap4_voltdm_iva.vc_param = &omap4_iva_vc_data;
	omap4_voltdm_core.vc_param = &omap4_core_vc_data;

	for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
		voltdm->sys_clk.name = sys_clk_name;

	voltdm_init(voltagedomains_omap4);
};

/**
 * omap4_opp_init() - initialize omap4 opp table
 */
int __init omap4_opp_init(void)
{
	int r = -ENODEV;
	int trimmed = 1;

	if (!cpu_is_omap44xx())
		return r;
	if (cpu_is_omap443x())
		r = omap_init_opp_table(omap443x_opp_def_list,
			ARRAY_SIZE(omap443x_opp_def_list));
	else if (cpu_is_omap446x()) {
		r = omap_init_opp_table(omap446x_opp_def_list,
			ARRAY_SIZE(omap446x_opp_def_list));
		trimmed = omap_readl(0x4a002268) & ((1 << 18) | (1 << 19));
		/* if device is untrimmed override DPLL TRIM register */
		if (!trimmed)
			omap_writel(0x29, 0x4a002330);
	}

	if (!r) {
		if (omap4_has_mpu_1_2ghz())
			omap4_mpu_opp_enable(1200000000);
		if (!trimmed)
			pr_info("This is DPLL un-trimmed SOM. OPP is limited at 1.2 GHz\n");
		if (omap4_has_mpu_1_5ghz() && trimmed)
			omap4_mpu_opp_enable(1500000000);
	}

	return r;
}

/**
 * omap4_opp_init() - initialize omap4 opp table
 */
int __init omap4_opp_init(void)
{
	int r = -ENODEV;

	if (!cpu_is_omap44xx())
		return r;
	if (cpu_is_omap443x())
		r = omap_init_opp_table(omap443x_opp_def_list,
			ARRAY_SIZE(omap443x_opp_def_list));
	else if (cpu_is_omap446x())
		r = omap_init_opp_table(omap446x_opp_def_list,
			ARRAY_SIZE(omap446x_opp_def_list));

	if (!r) {
		if (omap4_has_mpu_1_2ghz())
			omap4_mpu_opp_enable(1200000000);
		/* 1.8Ghz까지 오버클럭 */
		if (omap4_has_mpu_1_5ghz())
			omap4_mpu_opp_enable(1340000000);
			omap4_mpu_opp_enable(1520000000);
			omap4_mpu_opp_enable(1650000000);
	}

	return r;
}

static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
{
	void *startup_addr = omap4_secondary_startup;
	void __iomem *base = omap_get_wakeupgen_base();

	/*
	 * Initialise the SCU and wake up the secondary core using
	 * wakeup_secondary().
	 */
	if (scu_base)
		scu_enable(scu_base);

	if (cpu_is_omap446x()) {
		startup_addr = omap4460_secondary_startup;
		pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
	}

	/*
	 * Write the address of secondary startup routine into the
	 * AuxCoreBoot1 where ROM code will jump and start executing
	 * on secondary core once out of WFE
	 * A barrier is added to ensure that write buffer is drained
	 */
	if (omap_secure_apis_support())
		omap_auxcoreboot_addr(virt_to_phys(startup_addr));
	else
		__raw_writel(virt_to_phys(omap5_secondary_startup),
						base + OMAP_AUX_CORE_BOOT_1);

}

static void __init omap_4430sdp_display_init(void)
{
	int r;

	/* Enable LCD2 by default (instead of Pico DLP) */
	r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
			"display_sel");
	if (r)
		pr_err("%s: Could not get display_sel GPIO\n", __func__);

	sdp4430_picodlp_init();
	omap_display_init(&sdp4430_dss_data);
	/*
	 * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and
	 * later have external pull up on the HDMI I2C lines
	 */
	if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2)
		omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
	else
		omap_hdmi_init(0);

	omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT);
	omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT);
	omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
}

static void __init wakeup_secondary(void)
{
	void *startup_addr = omap_secondary_startup;
	void __iomem *base = omap_get_wakeupgen_base();

	if (cpu_is_omap446x()) {
		startup_addr = omap_secondary_startup_4460;
		pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
	}

	/*
	 * Write the address of secondary startup routine into the
	 * AuxCoreBoot1 where ROM code will jump and start executing
	 * on secondary core once out of WFE
	 * A barrier is added to ensure that write buffer is drained
	 */
	if (omap_secure_apis_support())
		omap_auxcoreboot_addr(virt_to_phys(startup_addr));
	else
		__raw_writel(virt_to_phys(omap5_secondary_startup),
						base + OMAP_AUX_CORE_BOOT_1);

	smp_wmb();

	/*
	 * Send a 'sev' to wake the secondary core from WFE.
	 * Drain the outstanding writes to memory
	 */
	dsb_sev();
	mb();
}

int __init pcb_temp_sensor_init(void)
{
	if (!cpu_is_omap446x())
		return 0;

	return platform_driver_register(&pcb_temp_sensor_driver);
}

void __cpuinit platform_secondary_init(unsigned int cpu)
{
	u32 diag0_errata_flags = 0;
	/* Enable NS access to SMP bit for this CPU on HS devices */
	if (cpu_is_omap446x() || cpu_is_omap443x()) {
		if (omap_type() != OMAP2_DEVICE_TYPE_GP)
			omap4_secure_dispatcher(PPA_SERVICE_DEFAULT_POR_NS_SMP,
					FLAG_START_CRITICAL,
					0, 0, 0, 0, 0);
		else {
			diag0_errata_flags =
				omap4_get_diagctrl0_errata_flags();
			if (diag0_errata_flags)
				omap_smc1(HAL_DIAGREG_0, diag0_errata_flags);
		}

	}

	/*
	 * If any interrupts are already enabled for the primary
	 * core (e.g. timer irq), then they will not have been enabled
	 * for us: do so
	 */
	gic_secondary_init(0);

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}

 /*
  * omap4_sar_save -
  * Save the context to SAR_RAM1 and SAR_RAM2 as per
  * omap4xxx_sar_ram1_layout and omap4xxx_sar_ram2_layout for the device OFF
  * mode
  */
int omap4_sar_save(void)
{
	/*
	 * Not supported on ES1.0 silicon
	 */
	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN_ONCE(1, "omap4: SAR backup not supported on ES1.0 ..\n");
		return -ENODEV;
	}

	if (omap4_sar_not_accessible()) {
		pr_debug("%s: USB SAR CNTX registers are not accessible!\n",
			 __func__);
		return -EBUSY;
	}

	/*
	 * SAR bits and clocks needs to be enabled
	 */
	clkdm_wakeup(l3init_clkdm);
	pwrdm_enable_hdwr_sar(l3init_pwrdm);
	clk_enable(usb_host_ck);
	clk_enable(usb_tll_ck);

	/* Save SAR BANK1 */
	if (cpu_is_omap446x())
		sar_save(ARRAY_SIZE(omap446x_sar_ram1_layout), SAR_BANK1_OFFSET,
			 omap446x_sar_ram1_layout);
	else
		sar_save(ARRAY_SIZE(omap443x_sar_ram1_layout), SAR_BANK1_OFFSET,
			 omap443x_sar_ram1_layout);

	clk_disable(usb_host_ck);
	clk_disable(usb_tll_ck);
	pwrdm_disable_hdwr_sar(l3init_pwrdm);
	clkdm_allow_idle(l3init_clkdm);

	/* Save SAR BANK2 */
	if (cpu_is_omap446x())
		sar_save(ARRAY_SIZE(omap446x_sar_ram2_layout), SAR_BANK2_OFFSET,
			 omap446x_sar_ram2_layout);
	else
		sar_save(ARRAY_SIZE(omap443x_sar_ram2_layout), SAR_BANK2_OFFSET,
			 omap443x_sar_ram2_layout);

	return 0;
}

int __init omap_devinit_temp_sensor(void)
{
	if (!cpu_is_omap446x() && !cpu_is_omap447x())
		return 0;

	return omap_hwmod_for_each_by_class("thermal_sensor",
			temp_sensor_dev_init, NULL);
}

static int __init omap_die_governor_init(void)
{
	struct thermal_dev *thermal_fw;

	omap_gov = kzalloc(sizeof(struct omap_die_governor), GFP_KERNEL);
	if (!omap_gov) {
		pr_err("%s:Cannot allocate memory\n", __func__);
		return -ENOMEM;
	}

	thermal_fw = kzalloc(sizeof(struct thermal_dev), GFP_KERNEL);
	if (thermal_fw) {
		thermal_fw->name = "omap_ondie_governor";
		thermal_fw->domain_name = "cpu";
		thermal_fw->dev_ops = &omap_gov_ops;
		thermal_governor_dev_register(thermal_fw);
		therm_fw = thermal_fw;
	} else {
		pr_err("%s: Cannot allocate memory\n", __func__);
		kfree(omap_gov);
		return -ENOMEM;
	}

	if (cpu_is_omap446x()) {
		omap_gov->gradient_slope = OMAP_GRADIENT_SLOPE_4460;
		omap_gov->gradient_const = OMAP_GRADIENT_CONST_4460;
		omap_gov->gradient_slope_w_pcb = OMAP_GRADIENT_SLOPE_W_PCB_4460;
		omap_gov->gradient_const_w_pcb = OMAP_GRADIENT_CONST_W_PCB_4460;
	} else if (cpu_is_omap447x()) {
		omap_gov->gradient_slope = OMAP_GRADIENT_SLOPE_4470;
		omap_gov->gradient_const = OMAP_GRADIENT_CONST_4470;
		omap_gov->gradient_slope_w_pcb = OMAP_GRADIENT_SLOPE_W_PCB_4470;
		omap_gov->gradient_const_w_pcb = OMAP_GRADIENT_CONST_W_PCB_4470;
	} else {
		omap_gov->gradient_slope = 0;
		omap_gov->gradient_const = 0;
		omap_gov->gradient_slope_w_pcb = 0;
		omap_gov->gradient_const_w_pcb = 0;
	}

	/* Init delayed work to average on-die temperature */
	INIT_DELAYED_WORK(&omap_gov->average_cpu_sensor_work,
			  average_cpu_sensor_delayed_work_fn);
	INIT_DELAYED_WORK(&omap_gov->decrease_mpu_freq_work,
			  decrease_mpu_freq_fn);

	omap_gov->average_period = NORMAL_TEMP_MONITORING_RATE;
	omap_gov->decrease_mpu_freq_period = DECREASE_MPU_FREQ_PERIOD;
	omap_gov->avg_is_valid = 0;

	if (register_pm_notifier(&omap_die_pm_notifier))
		pr_err("%s: omap_die pm registration failed!\n", __func__);

	schedule_delayed_work(&omap_gov->average_cpu_sensor_work,
			msecs_to_jiffies(0));

	return 0;
}

static void sar_save(u32 nb_regs, u32 sar_bank, const u32 sar_layout_table[][4])
{
	u32 reg_val, size, i, j;
	void __iomem *reg_read_addr, *sar_wr_addr;
	void *usb_sar_start;
	void *usb_sar_end;
	int usb_sar_table = 0;

	usb_sar_start = sar_ram_base + sar_bank + USB_SAR_AREA_START;
	usb_sar_end   = sar_ram_base + sar_bank + USB_SAR_AREA_END;

	/* 4460 USB SAR Registers are offset by 4 bytes */
	if (cpu_is_omap446x()) {
		usb_sar_start += 0x04;
		usb_sar_end += 0x04;
	}

	if ((sar_layout_table == omap443x_sar_ram1_layout) ||
		(sar_layout_table == omap446x_sar_ram1_layout))
		usb_sar_table = 1;

	for (i = 0; i < nb_regs; i++) {
		if (omap4_sar_modules[(sar_layout_table[i][MODULE_ADDR_IDX])]) {
			size = sar_layout_table[i][MODULE_NB_REGS_IDX];
			reg_read_addr =
			    omap4_sar_modules[sar_layout_table[i]
					      [MODULE_ADDR_IDX]]
			    + sar_layout_table[i][MODULE_OFFSET_IDX];
			sar_wr_addr = sar_ram_base + sar_bank +
			    sar_layout_table[i][SAR_RAM_OFFSET_IDX];
			for (j = 0; j < size; j++) {
				reg_val = __raw_readl(reg_read_addr + j * 4);
				if (usb_sar_table &&
				    sar_wr_addr+j*4 >= usb_sar_start &&
				    sar_wr_addr+j*4 <  usb_sar_end) {
					if (!sar_needs_ehci_saving) {
						/* Use the stored version */
						reg_val =
						usb_sar_data
						[(sar_wr_addr-usb_sar_start)/4
							+ j].val;
					} else {
						/* Save the USB SAR register */
						usb_sar_data
						[(sar_wr_addr-usb_sar_start)/4
							+ j].val = reg_val;
						usb_sar_data
						[(sar_wr_addr-usb_sar_start)/4
						+ j].reg_addr = reg_read_addr;
					}
				}
				__raw_writel(reg_val, sar_wr_addr + j * 4);
			}
		}
	}
	if (usb_sar_table)
		sar_needs_ehci_saving = 0;
}

static void __init omap_tablet_init(void)
{
	int status;
	int package = OMAP_PACKAGE_CBS;
	int tablet_rev = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		package = OMAP_PACKAGE_CBL;
	omap4_mux_init(board_mux, NULL, package);

	omap_emif_setup_device_details(&emif_devices, &emif_devices);

	omap_board_config = tablet_config;
	omap_board_config_size = ARRAY_SIZE(tablet_config);
	tablet_rev = omap_init_board_version(0);
	omap4_create_board_props();
	omap4_audio_conf();
	omap4_i2c_init();
	tablet_touch_init();
	tablet_camera_mux_init();
	omap_dmm_init();
	tablet_panel_init();
	tablet_pmic_mux_init();
	tablet_set_osc_timings();
	tablet_button_init();
	omap4_register_ion();
	board_serial_init();
	omap4_tablet_wifi_init();
	omap4_twl6030_hsmmc_init(mmc);
	tablet_sensor_init();
	platform_add_devices(tablet4430_devices,
			ARRAY_SIZE(tablet4430_devices));
	wake_lock_init(&st_wk_lock, WAKE_LOCK_SUSPEND, "st_wake_lock");
	omap4_ehci_ohci_init();
	usb_musb_init(&musb_board_data);

	status = omap_ethernet_init();
	if (status) {
		pr_err("Ethernet initialization failed: %d\n", status);
	} else {
		tablet_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ);
		spi_register_board_info(tablet_spi_board_info,
				ARRAY_SIZE(tablet_spi_board_info));
	}

	if (cpu_is_omap446x()) {
		/* Vsel0 = gpio, vsel1 = gnd */
		status = omap_tps6236x_board_setup(true, TPS62361_GPIO, -1,
					OMAP_PIN_OFF_OUTPUT_HIGH, -1);
		if (status)
			pr_err("TPS62361 initialization failed: %d\n", status);
	}

	omap_enable_smartreflex_on_init();
        if (enable_suspend_off)
                omap_pm_enable_off_mode();

}