C++ cpu_is_omap2430函数代码示例

static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
				  int power_on, int vdd)
{
	u32 reg, prog_io;
	struct omap_mmc_platform_data *mmc = dev->platform_data;

	if (mmc->slots[0].remux)
		mmc->slots[0].remux(dev, slot, power_on);

	if (power_on) {
		if (cpu_is_omap2430()) {
			reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
			if ((1 << vdd) >= MMC_VDD_30_31)
				reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
			else
				reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
			omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
		}

		if (mmc->slots[0].internal_clock) {
			reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
			reg |= OMAP2_MMCSDIO1ADPCLKISEL;
			omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
		}

		reg = omap_ctrl_readl(control_pbias_offset);
		if (cpu_is_omap3630()) {
			/* Set MMC I/O to 52Mhz */
			prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
			prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
			omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
		} else {
			reg |= OMAP2_PBIASSPEEDCTRL0;
		}
		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
		omap_ctrl_writel(reg, control_pbias_offset);
	} else {
		reg = omap_ctrl_readl(control_pbias_offset);
		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
		omap_ctrl_writel(reg, control_pbias_offset);
	}
}

void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
				 struct omap_sdrc_params *sdrc_cs1)
{
	u8 skip_setup_idle = 0;

	pwrdm_init(powerdomains_omap);
	clkdm_init(clockdomains_omap, clkdm_autodeps);
	if (cpu_is_omap242x())
		omap2420_hwmod_init();
	else if (cpu_is_omap243x())
		omap2430_hwmod_init();
	else if (cpu_is_omap34xx())
		omap3xxx_hwmod_init();
	/* The OPP tables have to be registered before a clk init */
	omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);

	if (cpu_is_omap2420())
		omap2420_clk_init();
	else if (cpu_is_omap2430())
		omap2430_clk_init();
	else if (cpu_is_omap34xx())
		omap3xxx_clk_init();
	else if (cpu_is_omap44xx())
		omap4xxx_clk_init();
	else
		pr_err("Could not init clock framework - unknown CPU\n");

	omap_serial_early_init();

#ifndef CONFIG_PM_RUNTIME
	skip_setup_idle = 1;
#endif
	if (cpu_is_omap24xx() || cpu_is_omap34xx())   /* FIXME: OMAP4 */
		omap_hwmod_late_init(skip_setup_idle);

	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
		omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
		_omap2_init_reprogram_sdrc();
	}
	gpmc_init();
}

static void omap_init_32k(void)
{
	if (cpu_is_omap2420()) {
		omap_32k_resources[0].start = OMAP2420_32KSYNCT_BASE;
		omap_32k_resources[0].end = OMAP2420_32KSYNCT_BASE + SZ_4K;
	} else if (cpu_is_omap2430()) {
		omap_32k_resources[0].start = OMAP2430_32KSYNCT_BASE;
		omap_32k_resources[0].end = OMAP2430_32KSYNCT_BASE + SZ_4K;
	} else if (cpu_is_omap34xx()) {
		omap_32k_resources[0].start = OMAP3430_32KSYNCT_BASE;
		omap_32k_resources[0].end = OMAP3430_32KSYNCT_BASE + SZ_4K;
	} else if (cpu_is_omap44xx()) {
		omap_32k_resources[0].start = OMAP4430_32KSYNCT_BASE;
		omap_32k_resources[0].end = OMAP4430_32KSYNCT_BASE + SZ_4K;
	} else {        /* not supported */
		return;
	}


	(void) platform_device_register(&omap_32k_device);
};

/**
 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 *
 * @param lch
 * @param read_prio - Read priority
 * @param write_prio - Write priority
 * Both of the above can be set with one of the following values :
 * 	DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 */
int
omap_dma_set_prio_lch(int lch, unsigned char read_prio,
					  unsigned char write_prio)
{
	u32 l;
	
	if (unlikely((lch < 0 || lch >= dma_lch_count))) {
		IOLog("Invalid channel id\n");
		return -EINVAL;
	}
	l = dma_read(CCR(lch));
	l &= ~((1 << 6) | (1 << 26));
	if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
		l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
	else
		l |= ((read_prio & 0x1) << 6);
	
	dma_write(l, CCR(lch));
	
	return 0;
}

void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	u32 reg;

	if (!cpu_is_omap44xx()) {
		if (cpu_is_omap2430()) {
			control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
		} else {
			control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
		}
	} else {
		control_pbias_offset =
			OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
		control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
		reg = omap4_ctrl_pad_readl(control_mmc1);
		reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
		reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
		reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
			OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
			OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
		omap4_ctrl_pad_writel(reg, control_mmc1);
	}

// from GB MMC0 and MMC1 was swapping. [START]
#ifdef TI_FS_MMC
	for (; controllers->mmc; controllers++)
		omap_init_hsmmc(controllers, controllers->mmc);
#else
	omap_init_hsmmc(&controllers[1], controllers[1].mmc);
	omap_init_hsmmc(&controllers[0], controllers[0].mmc);
	omap_init_hsmmc(&controllers[2], controllers[2].mmc);
#endif // TI_FS_MMC
// from GB MMC0 and MMC1 was swapping. [END]
    sd_ldo_init();

}

void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	u32 reg;

	if (omap_hsmmc_done)
		return;

	omap_hsmmc_done = 1;

	if (!(cpu_is_omap44xx() || cpu_is_omap54xx())) {
		if (cpu_is_omap2430()) {
			control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
		} else {
			control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
		}
	} else if (cpu_is_omap44xx()) {
		control_pbias_offset =
			OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
		control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
		reg = omap4_ctrl_pad_readl(control_mmc1);
		reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
		reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
		reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
			OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
			OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
		omap4_ctrl_pad_writel(reg, control_mmc1);
	} else if (cpu_is_omap54xx()) {
		control_pbias_offset =
			OMAP5_CTRL_MODULE_CORE_PAD_CONTROL_PBIAS;
	}

	for (; controllers->mmc; controllers++)
		omap_hsmmc_init_one(controllers, controllers->mmc);

}

void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	u32 reg;

	if (!cpu_is_omap44xx()) {
		if (cpu_is_omap2430()) {
			control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
		} else {
			control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
		}

		if (machine_is_omap3_pandora()) {
			/* needed for gpio_126 - gpio_129 to work correctly */
			reg = omap_ctrl_readl(control_pbias_offset);
			reg &= ~OMAP343X_PBIASLITEVMODE1;
			omap_ctrl_writel(reg, control_pbias_offset);
		}
	} else {
		control_pbias_offset =
			OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
		control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
		reg = omap4_ctrl_pad_readl(control_mmc1);
		reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
		reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
		reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
			OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
			OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
		omap4_ctrl_pad_writel(reg, control_mmc1);
	}

	for (; controllers->mmc; controllers++)
		omap_init_hsmmc(controllers, controllers->mmc);

}

void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
				 struct omap_sdrc_params *sdrc_cs1,
				 struct omap_opp *mpu_opps,
				 struct omap_opp *dsp_opps,
				 struct omap_opp *l3_opps)
{
	struct omap_hwmod **hwmods = NULL;

	if (cpu_is_omap2420())
		hwmods = omap2420_hwmods;
	else if (cpu_is_omap2430())
		hwmods = omap2430_hwmods;
	else if (cpu_is_omap34xx())
		hwmods = omap34xx_hwmods;
	else if (cpu_is_omap44xx())
		hwmods = omap44xx_hwmods;

	pwrdm_init(powerdomains_omap);
	clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
	omap_hwmod_init(hwmods);
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
	/* The OPP tables have to be registered before a clk init */
	omap2_mux_init();
	omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
#endif
	omap2_clk_init();
	omap_serial_early_init();
	omap_hwmod_late_init();
#ifndef CONFIG_ARCH_OMAP4
	omap_pm_if_init();
	omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
	_omap2_init_reprogram_sdrc();
#endif
	gpmc_init();
	omap_gpio_early_init();
	omap2_dm_timer_early_init();
}

void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	u32 reg;

	if (!cpu_is_omap44xx()) {
		if (cpu_is_omap2430()) {
			control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
		} else {
			control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
		}
	} else {
		control_pbias_offset =
			OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
		control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
		reg = omap4_ctrl_pad_readl(control_mmc1);
		reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
		reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
		if ((machine_is_omap_hummingbird() &&
				(system_rev > HUMMINGBIRD_EVT0B)) ||
				machine_is_omap_ovation())
			reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
				OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
				OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
		else
			reg |= (OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
				OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
		omap4_ctrl_pad_writel(reg, control_mmc1);
	}

	for (; controllers->mmc; controllers++)
		omap_init_hsmmc(controllers, controllers->mmc);

}

static void omap_init_mcspi(void)
{
	if (cpu_is_omap44xx()) {
		omap2_mcspi1_resources[0].start	= OMAP4_MCSPI1_BASE;
		omap2_mcspi1_resources[0].end	= OMAP4_MCSPI1_BASE + 0xff;
		omap2_mcspi2_resources[0].start	= OMAP4_MCSPI2_BASE;
		omap2_mcspi2_resources[0].end	= OMAP4_MCSPI2_BASE + 0xff;
		omap2_mcspi3_resources[0].start	= OMAP4_MCSPI3_BASE;
		omap2_mcspi3_resources[0].end	= OMAP4_MCSPI3_BASE + 0xff;
		omap2_mcspi4_resources[0].start	= OMAP4_MCSPI4_BASE;
		omap2_mcspi4_resources[0].end	= OMAP4_MCSPI4_BASE + 0xff;
	}
	platform_device_register(&omap2_mcspi1);
	platform_device_register(&omap2_mcspi2);
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
	defined(CONFIG_ARCH_OMAP4)
	if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
		platform_device_register(&omap2_mcspi3);
#endif
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
	if (cpu_is_omap343x() || cpu_is_omap44xx())
		platform_device_register(&omap2_mcspi4);
#endif
}

int __init omap2_clk_init(void)
{
    struct prcm_config *prcm;
    struct clk **clkp;
    u32 clkrate;

    if (cpu_is_omap242x())
        cpu_mask = RATE_IN_242X;
    else if (cpu_is_omap2430())
        cpu_mask = RATE_IN_243X;

    clk_init(&omap2_clk_functions);

    omap2_osc_clk_recalc(&osc_ck);
    omap2_sys_clk_recalc(&sys_ck);

    for (clkp = onchip_24xx_clks;
         clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
         clkp++) {

        if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
            clk_register(*clkp);
            continue;
        }

        if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
            clk_register(*clkp);
            continue;
        }
    }

    /* Check the MPU rate set by bootloader */
    clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
    for (prcm = rate_table; prcm->mpu_speed; prcm++) {
        if (!(prcm->flags & cpu_mask))
            continue;
        if (prcm->xtal_speed != sys_ck.rate)
            continue;
        if (prcm->dpll_speed <= clkrate)
             break;
    }
    curr_prcm_set = prcm;

    recalculate_root_clocks();

    printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
           "%ld.%01ld/%ld/%ld MHz\n",
           (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
           (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;

    /*
     * Only enable those clocks we will need, let the drivers
     * enable other clocks as necessary
     */
    clk_enable_init_clocks();

    /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
    vclk = clk_get(NULL, "virt_prcm_set");
    sclk = clk_get(NULL, "sys_ck");

    return 0;
}

static int omap_hsmmc_enable_clks(struct mmc_omap_host *host)
{
	unsigned long flags, timeout;
	int ret = 0;

	spin_lock_irqsave(&host->clk_lock, flags);

	if (host->clks_enabled)
		goto done;

	ret = clk_enable(host->iclk);
	if (ret)
		goto clk_en_err1;

	ret = clk_enable(host->fclk);
	if (ret)
		goto clk_en_err2;

	host->clks_enabled = 1;

	if (cpu_is_omap2430()) {
		/*
		 * MMC can still work without debounce clock.
		 */
		if (IS_ERR(host->dbclk))
			dev_warn(mmc_dev(host->mmc),
			"Failed to get debounce clock\n");
		else
			if (clk_enable(host->dbclk) != 0)
				dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
						" clk failed\n");
			else
				host->dbclk_enabled = 1;
	}

	if (!(host->pdata->context_loss) ||
		(host->pdata->context_loss(host->dev) != host->off_counter)) {
			/* Coming out of OFF:
			 * The SRA bit of SYSCTL reg has a wrong reset
			 * value.
			 * The bit resets automatically in subsequent
			 * reads. Idealy it should have been 0 as per
			 * the reset value of the register.
			 * Wait for the reset to complete */
			timeout = jiffies +
				msecs_to_jiffies(MMC_TIMEOUT_MS);
			while ((OMAP_HSMMC_READ(host->base, SYSSTATUS)
				& RESETDONE) != RESETDONE
				&& time_before(jiffies, timeout))
				;
			omap2_hsmmc_restore_ctx(host);
	}

done:
	spin_unlock_irqrestore(&host->clk_lock, flags);
	return ret;
clk_en_err2:
	clk_disable(host->iclk);
clk_en_err1:
	dev_dbg(mmc_dev(host->mmc),
		"Unable to enable MMC clocks \n");
	spin_unlock_irqrestore(&host->clk_lock, flags);
	return ret;
}

/* Sets basic clocks based on the specified rate */
static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
{
    u32 cur_rate, done_rate, bypass = 0, tmp;
    struct prcm_config *prcm;
    unsigned long found_speed = 0;
    unsigned long flags;

    if (clk != &virt_prcm_set)
        return -EINVAL;

    for (prcm = rate_table; prcm->mpu_speed; prcm++) {
        if (!(prcm->flags & cpu_mask))
            continue;

        if (prcm->xtal_speed != sys_ck.rate)
            continue;

        if (prcm->mpu_speed <= rate) {
            found_speed = prcm->mpu_speed;
            break;
        }
    }

    if (!found_speed) {
        printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
               rate / 1000000);
        return -EINVAL;
    }

    curr_prcm_set = prcm;
    cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);

    if (prcm->dpll_speed == cur_rate / 2) {
        omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
    } else if (prcm->dpll_speed == cur_rate * 2) {
        omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
    } else if (prcm->dpll_speed != cur_rate) {
        local_irq_save(flags);

        if (prcm->dpll_speed == prcm->xtal_speed)
            bypass = 1;

        if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
            CORE_CLK_SRC_DPLL_X2)
            done_rate = CORE_CLK_SRC_DPLL_X2;
        else
            done_rate = CORE_CLK_SRC_DPLL;

        /* MPU divider */
        cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);

        /* dsp + iva1 div(2420), iva2.1(2430) */
        cm_write_mod_reg(prcm->cm_clksel_dsp,
                 OMAP24XX_DSP_MOD, CM_CLKSEL);

        cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);

        /* Major subsystem dividers */
        tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
        cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
        if (cpu_is_omap2430())
            cm_write_mod_reg(prcm->cm_clksel_mdm,
                     OMAP2430_MDM_MOD, CM_CLKSEL);

        /* x2 to enter init_mem */
        omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);

        omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
                   bypass);

        omap2_init_memory_params(omap2_dll_force_needed());
        omap2_reprogram_sdrc(done_rate, 0);

        local_irq_restore(flags);
    }
    omap2_dpll_recalc(&dpll_ck);

    return 0;
}

int __init omap2_clk_init(void)
{
    /* struct prcm_config *prcm; */
    struct clk **clkp;
    /* u32 clkrate; */
    u32 cpu_clkflg;

    /* REVISIT: Ultimately this will be used for multiboot */
#if 0
    if (cpu_is_omap242x()) {
        cpu_mask = RATE_IN_242X;
        cpu_clkflg = CLOCK_IN_OMAP242X;
        clkp = onchip_24xx_clks;
    } else if (cpu_is_omap2430()) {
        cpu_mask = RATE_IN_243X;
        cpu_clkflg = CLOCK_IN_OMAP243X;
        clkp = onchip_24xx_clks;
    }
#endif
    if (cpu_is_omap34xx()) {
        cpu_mask = RATE_IN_343X;
        cpu_clkflg = CLOCK_IN_OMAP343X;
        clkp = onchip_34xx_clks;

        /*
         * Update this if there are further clock changes between ES2
         * and production parts
         */
        if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
            /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
            cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
        } else {
            cpu_mask |= RATE_IN_3430ES2;
            cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
        }
    }

    clk_init(&omap2_clk_functions);

    for (clkp = onchip_34xx_clks;
         clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
         clkp++) {
        if ((*clkp)->flags & cpu_clkflg)
            clk_register(*clkp);
    }

    /* REVISIT: Not yet ready for OMAP3 */
#if 0
    /* Check the MPU rate set by bootloader */
    clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
    for (prcm = rate_table; prcm->mpu_speed; prcm++) {
        if (!(prcm->flags & cpu_mask))
            continue;
        if (prcm->xtal_speed != sys_ck.rate)
            continue;
        if (prcm->dpll_speed <= clkrate)
             break;
    }
    curr_prcm_set = prcm;
#endif

    recalculate_root_clocks();

    printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
           "%ld.%01ld/%ld/%ld MHz\n",
           (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
           (core_ck.rate / 1000000), (arm_fck.rate / 1000000));

    /*
     * Only enable those clocks we will need, let the drivers
     * enable other clocks as necessary
     */
    clk_enable_init_clocks();

    /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
    /* REVISIT: not yet ready for 343x */
#if 0
    vclk = clk_get(NULL, "virt_prcm_set");
    sclk = clk_get(NULL, "sys_ck");
#endif
    return 0;
}

void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	struct omap2_hsmmc_info *c;
	int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
	int i;
	u32 reg;

	if (!cpu_is_omap44xx()) {
		if (cpu_is_omap2430()) {
			control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
		} else {
			control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
			control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
		}
	} else {
		control_pbias_offset =
			OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
		control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
		reg = omap4_ctrl_pad_readl(control_mmc1);
		reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
		reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
			OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
		reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
			OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
			OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
		omap4_ctrl_pad_writel(reg, control_mmc1);
	}

	for (c = controllers; c->mmc; c++) {
		struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
		struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];

		if (!c->mmc || c->mmc > nr_hsmmc) {
			pr_debug("MMC%d: no such controller\n", c->mmc);
			continue;
		}
		if (mmc) {
			pr_debug("MMC%d: already configured\n", c->mmc);
			continue;
		}

		mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
			      GFP_KERNEL);
		if (!mmc) {
			pr_err("Cannot allocate memory for mmc device!\n");
			goto done;
		}

		if (cpu_is_ti816x())
			mmc->version = MMC_CTRL_VERSION_2;

		if (c->name)
			strncpy(hc->name, c->name, HSMMC_NAME_LEN);
		else
			snprintf(hc->name, ARRAY_SIZE(hc->name),
				"mmc%islot%i", c->mmc, 1);
		mmc->slots[0].name = hc->name;
		mmc->nr_slots = 1;
		mmc->slots[0].caps = c->caps;
		mmc->slots[0].internal_clock = !c->ext_clock;
		mmc->dma_mask = 0xffffffff;
		if (cpu_is_omap44xx())
			mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
		else
			mmc->reg_offset = 0;

		mmc->get_context_loss_count = hsmmc_get_context_loss;

		mmc->slots[0].switch_pin = c->gpio_cd;
		mmc->slots[0].gpio_wp = c->gpio_wp;

		mmc->slots[0].remux = c->remux;
		mmc->slots[0].init_card = c->init_card;

		if (c->cover_only)
			mmc->slots[0].cover = 1;

		if (c->nonremovable)
			mmc->slots[0].nonremovable = 1;

		if (c->power_saving)
			mmc->slots[0].power_saving = 1;

		if (c->no_off)
			mmc->slots[0].no_off = 1;

		if (c->vcc_aux_disable_is_sleep)
			mmc->slots[0].vcc_aux_disable_is_sleep = 1;

		/* NOTE:  MMC slots should have a Vcc regulator set up.
		 * This may be from a TWL4030-family chip, another
		 * controllable regulator, or a fixed supply.
		 *
		 * temporary HACK: ocr_mask instead of fixed supply
		 */
		if (cpu_is_omap3505() || cpu_is_omap3517())
			mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
						 MMC_VDD_26_27 |
//.........这里部分代码省略.........