C++ cpu_init函数代码示例

void board_init(void)
{
    /* initialize the boards LEDs */
    gpio_init(LED0_PIN, GPIO_OUT);
    gpio_init(LED1_PIN, GPIO_OUT);
    gpio_init(LED2_PIN, GPIO_OUT);
    gpio_init(LED3_PIN, GPIO_OUT);

    /* initialize the CPU */
    cpu_init();
}

void board_init(void)
{
    /* setup on-board LEDs */
    NRF_P0->DIRSET = (LED_MASK_P0);
    NRF_P0->OUTSET = (LED_MASK_P0);
    NRF_P1->DIRSET = (LED_MASK_P1);
    NRF_P1->OUTSET = (LED_MASK_P1);

    /* initialize the CPU */
    cpu_init();
}

void board_init(void)
{
    /* initialize the CPU */
    cpu_init();

#ifdef AUTO_INIT_LED0
    /* The LED pin is also used for SPI, so we enable it
       only if explicitly wanted by the user */
    gpio_init(LED0_PIN, GPIO_OUT);
#endif
}

void boot_64(uint32_t magic, uint32_t multiboot) {
  // checking multiboot magic variable.
  VGA_AT(0,0) = VGA_ENTRY('H', WHITE_ON_BLACK);
  if (magic != MULTIBOOT_BOOTLOADER_MAGIC) {
    VGA_AT(0,1) = VGA_ENTRY('!', WHITE_ON_BLACK);
    kernel_panic();
  }

  // copying multiboot data.
  VGA_AT(0,1) = VGA_ENTRY('E', WHITE_ON_BLACK);
  multiboot_info_t *info = (multiboot_info_t *)kernel_p2v((uintptr_t)multiboot);
  switch (multiboot_copy(info)) {
  case MULTIBOOT_TOO_MANY_MEMORY_MAPS:
    VGA_AT(0,2) = VGA_ENTRY('?', WHITE_ON_BLACK);
    kernel_panic();
  case MULTIBOOT_TOO_MANY_MODULES:
    VGA_AT(0,2) = VGA_ENTRY('?', WHITE_ON_BLACK);
    kernel_panic();
  case MULTIBOOT_TOO_MANY_ELF_HEADERS:
    VGA_AT(0,2) = VGA_ENTRY('.', WHITE_ON_BLACK);
    kernel_panic();
  }

  // we no longer need the original memory map at zero address.
  VGA_AT(0,2) = VGA_ENTRY('L', WHITE_ON_BLACK);
  page_set_pdpt(0, 0, 0);
  page_invalidate_all();
  
  // initialize page allocators.
  VGA_AT(0,3) = VGA_ENTRY('L', WHITE_ON_BLACK);
  lomem_init();
  himem_init();

  // initialize CPUs.
  VGA_AT(0,4) = VGA_ENTRY('B', WHITE_ON_BLACK);
  cpu_enable_features();
  cpu_init();
  service_init();
  gdt_init(); // adds per-cpu TSS into GDT.
  tss_update();

  // initialize interrupt handling.
  VGA_AT(0,5) = VGA_ENTRY('E', WHITE_ON_BLACK);
  pic_init();
  idt_init();

  // kick-start the core service.
  VGA_AT(0,6) = VGA_ENTRY('N', WHITE_ON_BLACK);
  kernel_start_core();

  // start scheduler and do stuff.
  VGA_AT(0,7) = VGA_ENTRY('D', WHITE_ON_BLACK);
  kernel_main();
}

static void
petalogix_s3adsp1800_init(ram_addr_t ram_size,
                          const char *boot_device,
                          const char *kernel_filename,
                          const char *kernel_cmdline,
                          const char *initrd_filename, const char *cpu_model)
{
    DeviceState *dev;
    CPUMBState *env;
    DriveInfo *dinfo;
    int i;
    target_phys_addr_t ddr_base = MEMORY_BASEADDR;
    MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32], *cpu_irq;
    MemoryRegion *sysmem = get_system_memory();

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "microblaze";
    }
    env = cpu_init(cpu_model);

    /* Attach emulated BRAM through the LMB.  */
    memory_region_init_ram(phys_lmb_bram,
                           "petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE);
    vmstate_register_ram_global(phys_lmb_bram);
    memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);

    memory_region_init_ram(phys_ram, "petalogix_s3adsp1800.ram", ram_size);
    vmstate_register_ram_global(phys_ram);
    memory_region_add_subregion(sysmem, ddr_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    pflash_cfi01_register(FLASH_BASEADDR,
                          NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE,
                          dinfo ? dinfo->bdrv : NULL, (64 * 1024),
                          FLASH_SIZE >> 16,
                          1, 0x89, 0x18, 0x0000, 0x0, 1);

    cpu_irq = microblaze_pic_init_cpu(env);
    dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 2);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }

    sysbus_create_simple("xilinx,uartlite", UARTLITE_BASEADDR, irq[3]);
    /* 2 timers at irq 2 @ 62 Mhz.  */
    xilinx_timer_create(TIMER_BASEADDR, irq[0], 2, 62 * 1000000);
    xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0);

    microblaze_load_kernel(env, ddr_base, ram_size,
                    BINARY_DEVICE_TREE_FILE, machine_cpu_reset);
}

void s5l8930_iop_init(void *opaque)
{
    int io;
    s5l8930_iop_s *s = (s5l8930_iop_s *) qemu_mallocz(sizeof(s5l8930_iop_s));
    s5l8930_state *s5l8930 = opaque;
	CPUState *env;
    qemu_irq *cpu_irq;
    DeviceState *dev, *dev_prev;
    int i,j;

    env = cpu_init("cortex-a8");
    if(!env) {
        fprintf(stderr, "Unable to find CPU for IOP proccess definition\n");
        exit(1);
    }

  	cpu_irq = arm_pic_init_cpu(env);

    // Allocate 4 vic controllers
    s->irq = qemu_mallocz(S5L8930_ARM7_VIC_N * sizeof(qemu_irq *));
    dev = pl192_init(S5L8930_ARM7_VIC_BASE, 4,
                     cpu_irq[ARM_PIC_CPU_IRQ],
                     cpu_irq[ARM_PIC_CPU_FIQ], NULL);
    // Each with 32 irq's
    s->irq[0] = qemu_mallocz(S5L8930_ARM7_VIC_SIZE * sizeof(qemu_irq));
    for (i = 0; i < S5L8930_ARM7_VIC_SIZE; i++)
        s->irq[0][i] = qdev_get_gpio_in(dev, i);
    for (j = 1; j < S5L8930_ARM7_VIC_N; j++) {
        dev_prev = dev;
        dev = pl192_init(S5L8930_ARM7_VIC_BASE + S5L8930_ARM7_VIC_SHIFT * j, 4+j, NULL);

        s->irq[j] = qemu_mallocz(S5L8930_ARM7_VIC_SIZE * sizeof(qemu_irq));
        for (i = 0; i < S5L8930_ARM7_VIC_SIZE; i++)
            s->irq[j][i] = qdev_get_gpio_in(dev, i);
        pl192_chain(sysbus_from_qdev(dev_prev), sysbus_from_qdev(dev));
    }


    uint32_t base = 0x86300000;
    s->name = name0;
	s->s5l8930env = s5l8930->env;
	s->iopenv = env;
	s->cdma = s5l8930->cdma;
	s->timer = s5l8930->timer;
	s->iopirq = s5l8930_get_irq(s5l8930, S5L8930_IOP_IRQ);
    io = cpu_register_io_memory(s5l8930_iop_readfn, s5l8930_iop_writefn, s, DEVICE_LITTLE_ENDIAN);
    cpu_register_physical_memory(base, 0x1000, io);

	setTimerIRQ2(s->timer, s5l8930_iop_get_irq(s, S5L8930_TIMER0_IRQ));
	IOPCpuState = s->iopenv;
	MainCpuState = s5l8930->env;
	IOPState = s;
	cpu_interrupt(env, CPU_INTERRUPT_HALT);
}

void board_init(void)
{
    /* initialize core clocks via CMSIS function provided by Atmel */
    SystemInit();

    /* initialize the CPU */
    cpu_init();

    /* initialize the boards LEDs */
    led_init();
}

static void dummy_ppc_init(ram_addr_t ram_size, int vga_ram_size,
                     const char *boot_device, DisplayState *ds,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    int kernel_size;
    uint64_t elf_entry;
    target_ulong entry;

    if (!cpu_model)
        cpu_model = "default";
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find ppc CPU definition\n");
        exit(1);
    }

    cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
    /* RAM at address zero */
    cpu_register_physical_memory(0x10000000, ram_size,
        qemu_ram_alloc(ram_size) | IO_MEM_RAM);

    /* Load kernel.  */
    if (kernel_filename) {
        kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL);
        entry = elf_entry;
        if (kernel_size < 0) {
            kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
        }
        if (kernel_size < 0) {
            kernel_size = load_image(kernel_filename, phys_ram_base);
            entry = 0;
        }
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    } else {
        entry = 0;
    }
    env->nip = entry;
    if (semihosting_enabled) {
        /* Setup initial stack.  */
        target_ulong *p;
        p = (target_ulong *)(phys_ram_base + ram_size);
        *(--p) = 0;
        *(--p) = 0;
        env->gpr[1] = 0x10000000 + ram_size - 2 * sizeof(target_ulong);
        /* Enable FPU.  */
        env->msr |= (1 << MSR_FP);
    }
}

int main(void) {
	cpu_init();
	P1IFG = 0x00;
	uart_init();

	delayMs(1000);

	__enable_interrupt();

	/* Initialize RFM-module */
	rf12_initialize(2, RF12_433MHZ, 33);

	uint8_t c = 0;
	uart_puts("Hello\n");
	uint8_t payload[1];

	bool sendAck = false;
	while (true) {
		if (rf12_recvDone() && rf12_crc == 0) {
			switch(rf12_data[0]) {
			case PACKET_BAT_LEVEL:
				uart_puts("BATTERY LEVEL: ");
				uart_puts(rf12_data+1);
				break;
			case PACKET_SIGNAL:
				uart_puts("SIGNAL: ");
				uart_puts(rf12_data+1);
				break;
			default:
				uart_puts("UNKNOWN");
				break;
			}
			uart_putc('\n');
		}


		if (uart_getc(&c)) {
			if( c == 'I' ) {
				uart_putc('O');
				uart_putc('\n');
			}
		}

		/* Power down */
		// Only power down, if there is nothing to do

		if( !isReceiving && rxstate == TXRECV) {
			__bis_SR_register(LPM3_bits | GIE);
		}
	}

	return 0;
}

/*
 * Activate a secondary processor.
 */
notrace static void __cpuinit start_secondary(void *unused)
{
	/*
	 * Don't put *anything* before cpu_init(), SMP booting is too
	 * fragile that we want to limit the things done here to the
	 * most necessary things.
	 */
	cpu_init();
	x86_cpuinit.early_percpu_clock_init();
	preempt_disable();
	smp_callin();

	enable_start_cpu0 = 0;

	/* otherwise gcc will move up smp_processor_id before the cpu_init */
	barrier();

	/* switch away from the initial page table */
#ifdef CONFIG_PAX_PER_CPU_PGD
	load_cr3(get_cpu_pgd(smp_processor_id(), kernel));
	__flush_tlb_all();
#elif defined(CONFIG_X86_32)
	load_cr3(swapper_pg_dir);
	__flush_tlb_all();
#endif

	/*
	 * Check TSC synchronization with the BP:
	 */
	check_tsc_sync_target();

	/*
	 * We need to hold vector_lock so there the set of online cpus
	 * does not change while we are assigning vectors to cpus.  Holding
	 * this lock ensures we don't half assign or remove an irq from a cpu.
	 */
	lock_vector_lock();
	set_cpu_online(smp_processor_id(), true);
	unlock_vector_lock();
	per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
	x86_platform.nmi_init();

	/* enable local interrupts */
	local_irq_enable();

	/* to prevent fake stack check failure in clock setup */
	boot_init_stack_canary();

	x86_cpuinit.setup_percpu_clockev();

	wmb();
	cpu_startup_entry(CPUHP_ONLINE);
}

void board_init(void)
{
    /* enable access to the evaluation board controller chip. Without this, the
     * board controller does not forward the UART output to the USB port */
    gpio_init(BC_PIN, GPIO_OUT);
    gpio_set(BC_PIN);
    /* initialize the boards LEDs */
    gpio_init(LED0_PIN, GPIO_OUT);
    gpio_init(LED1_PIN, GPIO_OUT);
    /* initialize the CPU */
    cpu_init();
}

/*
 * Power collapse the Apps processor without involving Modem.
 *
 * Return value:
 *      0: success
 */
static int __ref msm_pm_power_collapse_standalone(bool from_idle)
{
	int collapsed = 0;
	int ret;
	void *entry;

	MSM_PM_DPRINTK(MSM_PM_DEBUG_SUSPEND|MSM_PM_DEBUG_POWER_COLLAPSE,
		KERN_INFO, "%s()\n", __func__);

	ret = msm_spm_set_low_power_mode(MSM_SPM_MODE_POWER_COLLAPSE, false);
	WARN_ON(ret);

	entry = (!smp_processor_id() || from_idle) ?
			msm_pm_collapse_exit : msm_secondary_startup;

	msm_pm_boot_config_before_pc(smp_processor_id(),
						virt_to_phys(entry));

#ifdef CONFIG_VFP
	vfp_pm_suspend();
#endif

#ifdef CONFIG_CACHE_L2X0
	if (!cpu_is_msm8625())
		l2cc_suspend();
#endif

	collapsed = msm_pm_collapse();

#ifdef CONFIG_CACHE_L2X0
	if (!cpu_is_msm8625())
		l2cc_resume();
#endif

	msm_pm_boot_config_after_pc(smp_processor_id());

	if (collapsed) {
#ifdef CONFIG_VFP
		vfp_pm_resume();
#endif
		cpu_init();
		local_fiq_enable();
	}

	MSM_PM_DPRINTK(MSM_PM_DEBUG_SUSPEND | MSM_PM_DEBUG_POWER_COLLAPSE,
		KERN_INFO,
		"%s(): msm_pm_collapse returned %d\n", __func__, collapsed);

	ret = msm_spm_set_low_power_mode(MSM_SPM_MODE_CLOCK_GATING, false);
	WARN_ON(ret);

	return !collapsed;
}

void emu_init(char* args){
	hal_init();
//	mem_init();
// init the ppu before rom otherwise set_mirroring will not work
	ppu_init();
	rom_init();
	readrom(args);
	cpu_init(&cpu);
	
	cpu_reset(&cpu);
	emu_running = true;
}

static void dummy_m68k_init(QEMUMachineInitArgs *args)
{
    ram_addr_t ram_size = args->ram_size;
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    CPUM68KState *env;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *ram = g_new(MemoryRegion, 1);
    int kernel_size;
    uint64_t elf_entry;
    hwaddr entry;

    if (!cpu_model)
        cpu_model = "cfv4e";
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find m68k CPU definition\n");
        exit(1);
    }

    /* Initialize CPU registers.  */
    env->vbr = 0;

    /* RAM at address zero */
    memory_region_init_ram(ram, "dummy_m68k.ram", ram_size);
    vmstate_register_ram_global(ram);
    memory_region_add_subregion(address_space_mem, 0, ram);

    /* Load kernel.  */
    if (kernel_filename) {
        kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
                               NULL, NULL, 1, ELF_MACHINE, 0);
        entry = elf_entry;
        if (kernel_size < 0) {
            kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
        }
        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename,
                                              KERNEL_LOAD_ADDR,
                                              ram_size - KERNEL_LOAD_ADDR);
            entry = KERNEL_LOAD_ADDR;
        }
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    } else {
        entry = 0;
    }
    env->pc = entry;
}

int main(int argc, char **argv) {

	int i;

	u_int32_t actual_program_counter = 0;// actual_pcb->program_counter;

    if (cpu_init(argc, argv[1])<0) return 0;

    cpu_state_machine();

    log_info(cpu_log, "=== Exiting CPU ===");
    return 0;
}