C++ cpu_getactivecpu函数代码示例

void m65ce02_set_irq_line(int irqline, int state)
{
	if (irqline == INPUT_LINE_NMI)
	{
		if (m65ce02.nmi_state == state) return;
		m65ce02.nmi_state = state;
		if( state != CLEAR_LINE )
		{
			LOG(("M65ce02#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
			EAD = M65CE02_NMI_VEC;
			m65ce02_ICount -= 7;
			PUSH(PCH);
			PUSH(PCL);
			PUSH(P & ~F_B);
			P = (P & ~F_D) | F_I;		/* knock out D and set I flag */
			PCL = RDMEM(EAD);
			PCH = RDMEM(EAD+1);
			LOG(("M65ce02#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PCD));
			change_pc(PCD);
		}
	}
	else
	{
		m65ce02.irq_state = state;
		if( state != CLEAR_LINE )
		{
			LOG(("M65ce02#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
			m65ce02.pending_irq = 1;
		}
	}
}

UINT32 debug_comment_get_opcode_crc32(offs_t address)
{
	int i;
	UINT32 crc;
	UINT8 opbuf[64], argbuf[64];
	char buff[256];
	offs_t numbytes;
	int maxbytes = activecpu_max_instruction_bytes();
	UINT32 addrmask = (debug_get_cpu_info(cpu_getactivecpu()))->space[ADDRESS_SPACE_PROGRAM].logaddrmask;

	int use_new_dasm = (activecpu_get_info_fct(CPUINFO_PTR_DISASSEMBLE_NEW) != NULL);

	memset(opbuf, 0x00, sizeof(opbuf));
	memset(argbuf, 0x00, sizeof(argbuf));

	// fetch the bytes up to the maximum
	for (i = 0; i < maxbytes; i++)
	{
		opbuf[i] = debug_read_opcode(address + i, 1, FALSE);
		argbuf[i] = debug_read_opcode(address + i, 1, TRUE);
	}

	if (use_new_dasm)
	{
		numbytes = cpunum_dasm_new(cpu_getactivecpu(), buff, address & addrmask, opbuf, argbuf, maxbytes) & DASMFLAG_LENGTHMASK;
	}
	else
	{
		numbytes = cpunum_dasm(cpu_getactivecpu(), buff, address & addrmask) & DASMFLAG_LENGTHMASK;
	}

	crc = crc32(0, argbuf, numbytes);

	return crc;
}

SEIBU_SOUND_SYSTEM_YM2203_HARDWARE

SEIBU_SOUND_SYSTEM_ADPCM_HARDWARE

/* Interrupt Generators */

static INTERRUPT_GEN( deadang_interrupt )
{
	if (cpu_getiloops())
		cpunum_set_input_line_and_vector(cpu_getactivecpu(), 0, HOLD_LINE, 0xc8/4);	/* VBL */
	else
		cpunum_set_input_line_and_vector(cpu_getactivecpu(), 0, HOLD_LINE, 0xc4/4);	/* VBL */
}

/****************************************************************************
 * Set IRQ line state
 ****************************************************************************/
static void set_irq_line(int irqline, int state)
{
	if (irqline == INPUT_LINE_NMI)
	{
		if (hd6309.nmi_state == state) return;
		hd6309.nmi_state = state;
		LOG(("HD6309#%d set_irq_line (NMI) %d (PC=%4.4X)\n", cpu_getactivecpu(), state, pPC));
		if( state == CLEAR_LINE ) return;

		/* if the stack was not yet initialized */
		if( !(hd6309.int_state & HD6309_LDS) ) return;

		hd6309.int_state &= ~HD6309_SYNC;
		/* HJB 990225: state already saved by CWAI? */
		if( hd6309.int_state & HD6309_CWAI )
		{
			hd6309.int_state &= ~HD6309_CWAI;
			hd6309.extra_cycles += 7;	/* subtract +7 cycles next time */
		}
		else
		{
			CC |= CC_E; 				/* save entire state */
			PUSHWORD(pPC);
			PUSHWORD(pU);
			PUSHWORD(pY);
			PUSHWORD(pX);
			PUSHBYTE(DP);
			if ( MD & MD_EM )
			{
				PUSHBYTE(F);
				PUSHBYTE(E);
				hd6309.extra_cycles += 2; /* subtract +2 cycles */
			}

			PUSHBYTE(B);
			PUSHBYTE(A);
			PUSHBYTE(CC);
			hd6309.extra_cycles += 19;	/* subtract +19 cycles next time */
		}
		CC |= CC_IF | CC_II;			/* inhibit FIRQ and IRQ */
		PCD = RM16(0xfffc);
		CHANGE_PC;
	}
	else if (irqline < 2)
	{
		LOG(("HD6309#%d set_irq_line %d, %d (PC=%4.4X)\n", cpu_getactivecpu(), irqline, state, pPC));
		hd6309.irq_state[irqline] = state;
		if (state == CLEAR_LINE) return;
		CHECK_IRQ_LINES();
	}
}

void saturn_set_nmi_line(int state)
{
	if (saturn.nmi_state == state) return;
	saturn.nmi_state = state;
	if( state != CLEAR_LINE )
	{
		LOG(( "M6502#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
		saturn_ICount -= 7;
		saturn_push(saturn.pc);
		saturn.pc=IRQ_ADDRESS;

		LOG(("M6502#%d takes NMI ($%04x)\n", cpu_getactivecpu(), PC));
		change_pc(saturn.pc);
	}
}

void pic16C5x_init(void)
{
	int cpu = cpu_getactivecpu();

	state_save_register_INT8("pic16C5x", cpu, "Old_Data", &old_data, 1);
	state_save_register_UINT8("pic16C5x", cpu, "W", &R.W, 1);
	state_save_register_UINT8("pic16C5x", cpu, "ALU", &R.ALU, 1);
	state_save_register_UINT8("pic16C5x", cpu, "Option", &R.OPTION, 1);
	state_save_register_UINT8("pic16C5x", cpu, "TRISA", &R.TRISA, 1);
	state_save_register_UINT8("pic16C5x", cpu, "TRISB", &R.TRISB, 1);
	state_save_register_UINT8("pic16C5x", cpu, "TRISC", &R.TRISC, 1);
	state_save_register_UINT8("pic16C5x", cpu, "PORTA", &R.PORTA, 1);
	state_save_register_UINT8("pic16C5x", cpu, "PORTB", &R.PORTB, 1);
	state_save_register_UINT8("pic16C5x", cpu, "PORTC", &R.PORTC, 1);
	state_save_register_UINT8("pic16C5x", cpu, "Old_T0", &old_T0, 1);
	state_save_register_UINT8("pic16C5x", cpu, "STR", &R.STATUS, 1);
	state_save_register_UINT8("pic16C5x", cpu, "RAM_mask", &picRAMmask, 1);
	state_save_register_UINT16("pic16C5x", cpu, "WDT", &R.WDT, 1);
	state_save_register_UINT16("pic16C5x", cpu, "Prescaler", &R.prescaler, 1);
	state_save_register_UINT16("pic16C5x", cpu, "Stack0", &R.STACK[0], 1);
	state_save_register_UINT16("pic16C5x", cpu, "Stack1", &R.STACK[1], 1);
	state_save_register_UINT16("pic16C5x", cpu, "PC", &R.PC, 1);
	state_save_register_UINT16("pic16C5x", cpu, "PrevPC", &R.PREVPC, 1);
	state_save_register_UINT16("pic16C5x", cpu, "Config", &R.CONFIG, 1);
	state_save_register_UINT32("pic16C5x", cpu, "Opcode", &R.opcode.d, 1);
	state_save_register_INT32("pic16C5x", cpu, "Delay_Timer", &delay_timer, 1);
	state_save_register_INT32("pic16C5x", cpu, "PIC_model", &picmodel, 1);
	state_save_register_INT32("pic16C5x", cpu, "Reset_Vector", &pic16C5x_reset_vector, 1);
}

static WRITE_HANDLER( ddragon_spriteram_w )
{
	if ( cpu_getactivecpu() == 1 && offset == 0 )
		dd_sub_cpu_busy = 0x10;

	ddragon_spriteram[offset] = data;
}

static WRITE8_HANDLER(write_a00x)
{
  switch(offset)
  {
	case 0x02: //A002 bit 7&6 = bank ????
	{
		int newbank;
		reg_a002=data;
		newbank=(data>>6)&3;
		if(newbank!=bank)
	    	{
	      		UINT8 *ROM = memory_region(REGION_CPU1);
	      		bank=newbank;
		    	ROM = &ROM[0x10000+0x8000 * newbank + UNBANKED_SIZE];
		    	memory_set_bankptr(1,ROM);
      		}
	}
	break;

	case 0x06: // bit 1 = coin lockout/counter ?
	break;

	case 0x08: //A008
    		cpunum_set_input_line(cpu_getactivecpu(),0,CLEAR_LINE);
    	break;
  }
}

static void tms7000_init(int index, int clock, const void *config, int (*irqcallback)(int))
{
	int cpu = cpu_getactivecpu();

	tms7000.irq_callback = irqcallback;

	memset(tms7000.pf, 0, 0x100);
	memset(tms7000.rf, 0, 0x80);

	/* Save register state */
	state_save_register_item("tms7000", cpu, pPC);
	state_save_register_item("tms7000", cpu, pSP);
	state_save_register_item("tms7000", cpu, pSR);

	/* Save Interrupt state */
	state_save_register_item_array("tms7000", cpu, tms7000.irq_state);

	/* Save register and perpherial file state */
	state_save_register_item_array("tms7000", cpu, tms7000.rf);
	state_save_register_item_array("tms7000", cpu, tms7000.pf);

	/* Save timer state */
	state_save_register_item("tms7000", cpu, tms7000.t1_prescaler);
	state_save_register_item("tms7000", cpu, tms7000.t1_capture_latch);
	state_save_register_item("tms7000", cpu, tms7000.t1_decrementer);

	state_save_register_item("tms7000", cpu, tms7000.idle_state);

	tms7000.irq_callback = irqcallback;
}

static void c128_bankswitch (int reset)
{
    if (mmu_cpu != MMU_CPU8502)
    {
        if (!MMU_CPU8502)
        {
            DBG_LOG (1, "switching to z80",
                     ("active %d\n",cpu_getactivecpu()) );
            memory_set_context(0);
            c128_bankswitch_z80();
            memory_set_context(1);
            cpunum_set_input_line(0, INPUT_LINE_HALT, CLEAR_LINE);
            cpunum_set_input_line(1, INPUT_LINE_HALT, ASSERT_LINE);
        }
        else
        {
            DBG_LOG (1, "switching to m6502",
                     ("active %d\n",cpu_getactivecpu()) );
            memory_set_context(1);
            c128_bankswitch_128(reset);
            memory_set_context(0);
            cpunum_set_input_line(0, INPUT_LINE_HALT, ASSERT_LINE);
            cpunum_set_input_line(1, INPUT_LINE_HALT, CLEAR_LINE);

            /* NPW 19-Nov-2005 - In the C128, CPU #0 starts out and hands over
             * control to CPU #1.  CPU #1 seems to execute garbage from 0x0000
             * up to 0x1100, at which point it finally hits some code
             * (presumably set up by CPU #1.) This always worked, but when I
             * changed the m8502 CPU core to use an internal memory map, it
             * started BRK-ing forever when trying to execute 0x0000.
             *
             * I am not sure whether the C128 actually executes this invalid
             * memory or if this is a bug in the C128 driver.  In any case, the
             * driver used to work with this behavior, so I am doing this hack
             * where I set CPU #1's PC to 0x1100 on reset.
             */
            if (cpunum_get_reg(1, REG_PC) == 0x0000)
                cpunum_set_reg(1, REG_PC, 0x1100);
        }
        mmu_cpu = MMU_CPU8502;
        return;
    }
    if (!MMU_CPU8502)
        c128_bankswitch_z80();
    else
        c128_bankswitch_128(reset);
}

SEIBU_SOUND_SYSTEM_YM3812_HARDWARE

/* Interrupt Generator */

static INTERRUPT_GEN( dynduke_interrupt )
{
	cpunum_set_input_line_and_vector(cpu_getactivecpu(), 0, HOLD_LINE, 0xc8/4);	// VBL
}

void computer_writemem_byte(int cpu, int addr, int value)
{
    int oldcpu = cpu_getactivecpu();
    memory_set_context(cpu);
    MEMORY_WRITE(cpu, addr, value);
    if (oldcpu != cpu)
		memory_set_context(oldcpu);
}

INLINE void irqn_line_assert(int irqline)
{
	int cpunum = cpu_getactivecpu();
	if (interrupt_enable[cpunum])
	{
		int vector = (irqline >= 0 && irqline < MAX_IRQ_LINES) ? interrupt_vector[cpunum][irqline] : 0xff;
		cpu_set_irq_line_and_vector(cpunum, irqline, ASSERT_LINE, vector);
	}
}

void saturn_set_irq_line(int irqline, int state)
{
	saturn.irq_state = state;
	if( state != CLEAR_LINE )
	{
		LOG(( "M6502#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
		saturn.pending_irq = 1;
	}
}

int computer_readmem_byte(int cpu, int addr)
{
    int oldcpu = cpu_getactivecpu(), result;
    memory_set_context(cpu);
    result = MEMORY_READ(cpu, addr);
    if (oldcpu != cpu)
    	memory_set_context(oldcpu);
    return result;
}