本文整理汇总了C++中clrsetbits_be32函数的典型用法代码示例。如果您正苦于以下问题:C++ clrsetbits_be32函数的具体用法?C++ clrsetbits_be32怎么用?C++ clrsetbits_be32使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了clrsetbits_be32函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: fsl_ssi_hw_params
/**
* fsl_ssi_hw_params - program the sample size
*
* Most of the SSI registers have been programmed in the startup function,
* but the word length must be programmed here. Unfortunately, programming
* the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
* cause a problem with supporting simultaneous playback and capture. If
* the SSI is already playing a stream, then that stream may be temporarily
* stopped when you start capture.
*
* Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
* clock master.
*/
static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
{
struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
if (substream == ssi_private->first_stream) {
struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
unsigned int sample_size =
snd_pcm_format_width(params_format(hw_params));
u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
/* The SSI should always be disabled at this points (SSIEN=0) */
/* In synchronous mode, the SSI uses STCCR for capture */
if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
!ssi_private->asynchronous)
clrsetbits_be32(&ssi->stccr,
CCSR_SSI_SxCCR_WL_MASK, wl);
else
clrsetbits_be32(&ssi->srccr,
CCSR_SSI_SxCCR_WL_MASK, wl);
}
return 0;
}
示例2: board_mmc_init
int board_mmc_init(bd_t *bd)
{
struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
if (!hwconfig("esdhc"))
return 0;
clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
return fsl_esdhc_mmc_init(bd);
}
示例3: checkboard
int checkboard (void)
{
u32 val_gpdat, board_rev_gpio;
volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
char board_rev = 0;
struct cpu_type *cpu;
val_gpdat = pgpio->gpdat;
board_rev_gpio = val_gpdat & BOARDREV_MASK;
if (board_rev_gpio == BOARDREV_C)
board_rev = 'C';
else if (board_rev_gpio == BOARDREV_B)
board_rev = 'B';
else
panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
cpu = gd->cpu;
printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
setbits_be32(&pgpio->gpdir, GPIO_DIR);
/*
* Bringing the following peripherals out of reset via GPIOs
* 0 = reset and 1 = out of reset
* GPIO12 - Reset to Ethernet Switch
* GPIO13 - Reset to SLIC/SLAC devices
* GPIO14 - Reset to SGMII_PHY_N
* GPIO15 - Reset to PCIe slots
* GPIO6 - Reset to RGMII PHY
* GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
*/
clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
return 0;
}
示例4: qe_usb_clock_set
int qe_usb_clock_set(enum qe_clock clk, int rate)
{
struct qe_mux __iomem *mux = &qe_immr->qmx;
unsigned long flags;
u32 val;
switch (clk) {
case QE_CLK3: val = QE_CMXGCR_USBCS_CLK3; break;
case QE_CLK5: val = QE_CMXGCR_USBCS_CLK5; break;
case QE_CLK7: val = QE_CMXGCR_USBCS_CLK7; break;
case QE_CLK9: val = QE_CMXGCR_USBCS_CLK9; break;
case QE_CLK13: val = QE_CMXGCR_USBCS_CLK13; break;
case QE_CLK17: val = QE_CMXGCR_USBCS_CLK17; break;
case QE_CLK19: val = QE_CMXGCR_USBCS_CLK19; break;
case QE_CLK21: val = QE_CMXGCR_USBCS_CLK21; break;
case QE_BRG9: val = QE_CMXGCR_USBCS_BRG9; break;
case QE_BRG10: val = QE_CMXGCR_USBCS_BRG10; break;
default:
pr_err("%s: requested unknown clock %d\n", __func__, clk);
return -EINVAL;
}
if (qe_clock_is_brg(clk))
qe_setbrg(clk, rate, 1);
spin_lock_irqsave(&cmxgcr_lock, flags);
clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);
spin_unlock_irqrestore(&cmxgcr_lock, flags);
return 0;
}
示例5: sdhci_be32bs_writeb
void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
{
int base = reg & ~0x3;
int shift = (reg & 0x3) * 8;
clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
}
示例6: guts_set_dmuxcr
/*
* Set the DMACR register in the GUTS
*
* The DMACR register determines the source of initiated transfers for each
* channel on each DMA controller. Rather than have a bunch of repetitive
* macros for the bit patterns, we just have a function that calculates
* them.
*
* guts: Pointer to GUTS structure
* co: The DMA controller (0 or 1)
* ch: The channel on the DMA controller (0, 1, 2, or 3)
* device: The device to set as the target (CCSR_GUTS_DMUXCR_xxx)
*/
static inline void guts_set_dmuxcr(struct ccsr_guts_85xx __iomem *guts,
unsigned int co, unsigned int ch, unsigned int device)
{
unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
clrsetbits_be32(&guts->dmuxcr, 3 << shift, device << shift);
}
示例7: esdhc_writew
static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
{
struct sdhci_of_host *of_host = sdhci_priv(host);
int base = reg & ~0x3;
int shift = (reg & 0x2) * 8;
switch (reg) {
case SDHCI_TRANSFER_MODE:
/*
* Postpone this write, we must do it together with a
* command write that is down below.
*/
of_host->xfer_mode_shadow = val;
return;
case SDHCI_COMMAND:
esdhc_writel(host, val << 16 | of_host->xfer_mode_shadow,
SDHCI_TRANSFER_MODE);
return;
case SDHCI_BLOCK_SIZE:
/*
* Two last DMA bits are reserved, and first one is used for
* non-standard blksz of 4096 bytes that we don't support
* yet. So clear the DMA boundary bits.
*/
val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
/* fall through */
}
clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
}
示例8: misc_init_r
/*
* Miscellaneous late-boot configurations
*
* If a VSC7385 microcode image is present, then upload it.
*/
int misc_init_r(void)
{
#ifdef CONFIG_MPC8XXX_SPI
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
sysconf83xx_t *sysconf = &immr->sysconf;
/*
* Set proper bits in SICRH to allow SPI on header J8
*
* NOTE: this breaks the TSEC2 interface, attached to the Vitesse
* switch. The pinmux configuration does not have a fine enough
* granularity to support both simultaneously.
*/
clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
puts("WARNING: SPI enabled, TSEC2 support is broken\n");
/* Set header J8 SPI chip select output, disabled */
setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
#endif
#ifdef CONFIG_VSC7385_IMAGE
if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
CONFIG_VSC7385_IMAGE_SIZE)) {
puts("Failure uploading VSC7385 microcode.\n");
return 1;
}
#endif
return 0;
}
示例9: checkboard
static void checkboard(void)
{
u32 val_gpdat, board_rev_gpio;
void __iomem *gpio_regs = (void __iomem *)MPC85xx_GPIO_ADDR;
val_gpdat = in_be32(gpio_regs + MPC85xx_GPIO_GPDAT);
board_rev_gpio = val_gpdat & BOARDREV_MASK;
if ((board_rev_gpio != BOARDREV_C) && (board_rev_gpio != BOARDREV_B) &&
(board_rev_gpio != BOARDREV_D))
panic("Unexpected Board REV %x detected!!\n", board_rev_gpio);
setbits_be32((gpio_regs + MPC85xx_GPIO_GPDIR), GPIO_DIR);
/*
* Bringing the following peripherals out of reset via GPIOs
* 0 = reset and 1 = out of reset
* GPIO12 - Reset to Ethernet Switch
* GPIO13 - Reset to SLIC/SLAC devices
* GPIO14 - Reset to SGMII_PHY_N
* GPIO15 - Reset to PCIe slots
* GPIO6 - Reset to RGMII PHY
* GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
*/
clrsetbits_be32((gpio_regs + MPC85xx_GPIO_GPDAT), USB_RST_CLR,
BOARD_PERI_RST_SET);
}
示例10: board_mmc_init
int board_mmc_init(bd_t *bd)
{
struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
char buffer[HWCONFIG_BUFFER_SIZE] = {0};
int esdhc_hwconfig_enabled = 0;
if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
if (esdhc_hwconfig_enabled == 0)
return 0;
clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
return fsl_esdhc_mmc_init(bd);
}
示例11: board_mmc_init
int board_mmc_init(bd_t *bd)
{
struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
if (!hwconfig("esdhc"))
return 0;
/* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
bcsr[0xc] |= 0x4c;
/* Set proper bits in SICR to allow SD signals through */
clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
SICRH_GPIO2_E_SD | SICRH_SPI_SD);
return fsl_esdhc_mmc_init(bd);
}
示例12: mpc512x_irq_set_type
static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
unsigned long gpio = irqd_to_hwirq(d);
void __iomem *reg;
unsigned int shift;
unsigned long flags;
if (gpio < 16) {
reg = mm->regs + GPIO_ICR;
shift = (15 - gpio) * 2;
} else {
reg = mm->regs + GPIO_ICR2;
shift = (15 - (gpio % 16)) * 2;
}
switch (flow_type) {
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_LEVEL_LOW:
spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
clrsetbits_be32(reg, 3 << shift, 2 << shift);
spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
break;
case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_LEVEL_HIGH:
spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
clrsetbits_be32(reg, 3 << shift, 1 << shift);
spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
break;
case IRQ_TYPE_EDGE_BOTH:
spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
clrbits32(reg, 3 << shift);
spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
break;
default:
return -EINVAL;
}
return 0;
}
示例13: mpc837x_rdb_sd_cfg
static void mpc837x_rdb_sd_cfg(void)
{
void __iomem *im;
im = ioremap(get_immrbase(), 0x1000);
if (!im) {
WARN_ON(1);
return;
}
/*
* On RDB boards (in contrast to MDS) USBB pins are used for SD only,
* so we can safely mux them away from the USB block.
*/
clrsetbits_be32(im + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USBB_MASK,
MPC837X_SICRL_SD);
clrsetbits_be32(im + MPC83XX_SICRH_OFFS, MPC837X_SICRH_SPI_MASK,
MPC837X_SICRH_SD);
iounmap(im);
}
示例14: iopin_initialize_bits
void iopin_initialize_bits(iopin_t *ioregs_init, int len)
{
short i, j, p;
u32 *reg, mask;
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
reg = (u32 *)&(im->io_ctrl);
/* iterate over table entries */
for (i = 0; i < len; i++) {
/* iterate over pins within a table entry */
for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
p < ioregs_init[i].nr_pins; p++, j++) {
if (ioregs_init[i].bit_or & IO_PIN_OVER_EACH) {
/* replace all settings at once */
out_be32(reg + j, ioregs_init[i].val);
} else {
/*
* only replace individual parts, but
* REPLACE them instead of just ORing
* them in and "inheriting" previously
* set bits which we don't want
*/
mask = 0;
if (ioregs_init[i].bit_or & IO_PIN_OVER_FMUX)
mask |= IO_PIN_FMUX(3);
if (ioregs_init[i].bit_or & IO_PIN_OVER_HOLD)
mask |= IO_PIN_HOLD(3);
if (ioregs_init[i].bit_or & IO_PIN_OVER_PULL)
mask |= IO_PIN_PUD(1) | IO_PIN_PUE(1);
if (ioregs_init[i].bit_or & IO_PIN_OVER_STRIG)
mask |= IO_PIN_ST(1);
if (ioregs_init[i].bit_or & IO_PIN_OVER_DRVSTR)
mask |= IO_PIN_DS(3);
/*
* DON'T do the "mask, then insert"
* in place on the register, it may
* break access to external hardware
* (like boot ROMs) when configuring
* LPB related pins, while the code to
* configure the pin is read from this
* very address region
*/
clrsetbits_be32(reg + j, mask,
ioregs_init[i].val & mask);
}
}
}
}
示例15: mpc837x_usb_cfg
int mpc837x_usb_cfg(void)
{
void __iomem *immap;
struct device_node *np = NULL;
const void *prop;
const void *dr_mode = NULL; /* 2011.2.28, added by panasonic ---> */
int ret = 0;
np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
if (!np)
return -ENODEV;
prop = of_get_property(np, "phy_type", NULL);
if (!prop || (strcmp(prop, "ulpi") && strcmp(prop, "serial"))) {
printk(KERN_WARNING "837x USB PHY type not supported\n");
of_node_put(np);
return -EINVAL;
}
dr_mode = of_get_property(np, "dr_mode", NULL); /* 2011.2.28, added by panasonic */
/* Map IMMR space for pin and clock settings */
immap = ioremap(get_immrbase(), 0x1000);
if (!immap) {
of_node_put(np);
return -ENOMEM;
}
/* Configure clock */
clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC837X_SCCR_USB_DRCM_11,
(!dr_mode||strcmp(dr_mode,"none"))? MPC837X_SCCR_USB_DRCM_11: 0);/* 2011.2.28, modified by panasonic (SAV) */
/* Configure pin mux for ULPI/serial */
clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USB_MASK,
MPC837X_SICRL_USB_ULPI);
iounmap(immap);
of_node_put(np);
return ret;
}