C++ clrbits_le32函数代码示例

void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
{
	struct mx28_power_regs *power_regs =
		(struct mx28_power_regs *)MXS_POWER_BASE;
	uint32_t cur_target, diff, bo_int = 0;
	uint32_t powered_by_linreg = 0;

	new_brownout = new_target - new_brownout;

	cur_target = readl(&power_regs->hw_power_vdddctrl);
	cur_target &= POWER_VDDDCTRL_TRG_MASK;
	cur_target *= 25;	/* 25 mV step*/
	cur_target += 800;	/* 800 mV lowest */

	powered_by_linreg = mx28_get_vddd_power_source_off();
	if (new_target > cur_target) {
		if (powered_by_linreg) {
			bo_int = readl(&power_regs->hw_power_vdddctrl);
			clrbits_le32(&power_regs->hw_power_vdddctrl,
					POWER_CTRL_ENIRQ_VDDD_BO);
		}

		setbits_le32(&power_regs->hw_power_vdddctrl,
				POWER_VDDDCTRL_BO_OFFSET_MASK);

		do {
			if (new_target - cur_target > 100)
				diff = cur_target + 100;
			else
				diff = new_target;

			diff -= 800;
			diff /= 25;

			clrsetbits_le32(&power_regs->hw_power_vdddctrl,
				POWER_VDDDCTRL_TRG_MASK, diff);

			if (powered_by_linreg ||
				(readl(&power_regs->hw_power_sts) &
					POWER_STS_VDD5V_GT_VDDIO))
				early_delay(1500);
			else {
				while (!(readl(&power_regs->hw_power_sts) &
					POWER_STS_DC_OK))
					;

			}

			cur_target = readl(&power_regs->hw_power_vdddctrl);
			cur_target &= POWER_VDDDCTRL_TRG_MASK;
			cur_target *= 25;	/* 25 mV step*/
			cur_target += 800;	/* 800 mV lowest */
		} while (new_target > cur_target);

		if (powered_by_linreg) {
			writel(POWER_CTRL_VDDD_BO_IRQ,
				&power_regs->hw_power_ctrl_clr);
			if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
				setbits_le32(&power_regs->hw_power_vdddctrl,
						POWER_CTRL_ENIRQ_VDDD_BO);
		}
	} else {
		do {
			if (cur_target - new_target > 100)
				diff = cur_target - 100;
			else
				diff = new_target;

			diff -= 800;
			diff /= 25;

			clrsetbits_le32(&power_regs->hw_power_vdddctrl,
					POWER_VDDDCTRL_TRG_MASK, diff);

			if (powered_by_linreg ||
				(readl(&power_regs->hw_power_sts) &
					POWER_STS_VDD5V_GT_VDDIO))
				early_delay(1500);
			else {
				while (!(readl(&power_regs->hw_power_sts) &
					POWER_STS_DC_OK))
					;

			}

			cur_target = readl(&power_regs->hw_power_vdddctrl);
			cur_target &= POWER_VDDDCTRL_TRG_MASK;
			cur_target *= 25;	/* 25 mV step*/
			cur_target += 800;	/* 800 mV lowest */
		} while (new_target < cur_target);
	}

	clrsetbits_le32(&power_regs->hw_power_vdddctrl,
			POWER_VDDDCTRL_BO_OFFSET_MASK,
			new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
}

void system_clock_init(struct mem_timings *mem,
		struct arm_clk_ratios *arm_clk_ratio)
{
	u32 val, tmp;

	/* Turn on the MCT as early as possible. */
	exynos_mct->g_tcon |= (1 << 8);

	clrbits_le32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK);
	do {
		val = readl(&exynos_clock->mux_stat_cpu);
	} while ((val | MUX_APLL_SEL_MASK) != val);

	clrbits_le32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK);
	do {
		val = readl(&exynos_clock->mux_stat_core1);
	} while ((val | MUX_MPLL_SEL_MASK) != val);

	clrbits_le32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK);
	clrbits_le32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK);
	clrbits_le32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK);
	clrbits_le32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK);
	tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
		| MUX_GPLL_SEL_MASK;
	do {
		val = readl(&exynos_clock->mux_stat_top2);
	} while ((val | tmp) != val);

	clrbits_le32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK);
	do {
		val = readl(&exynos_clock->mux_stat_cdrex);
	} while ((val | MUX_BPLL_SEL_MASK) != val);

	/* PLL locktime */
	writel(APLL_LOCK_VAL, &exynos_clock->apll_lock);

	writel(MPLL_LOCK_VAL, &exynos_clock->mpll_lock);

	writel(BPLL_LOCK_VAL, &exynos_clock->bpll_lock);

	writel(CPLL_LOCK_VAL, &exynos_clock->cpll_lock);

	writel(GPLL_LOCK_VAL, &exynos_clock->gpll_lock);

	writel(EPLL_LOCK_VAL, &exynos_clock->epll_lock);

	writel(VPLL_LOCK_VAL, &exynos_clock->vpll_lock);

	writel(CLK_REG_DISABLE, &exynos_clock->pll_div2_sel);

	writel(MUX_HPM_SEL_MASK, &exynos_clock->src_cpu);
	do {
		val = readl(&exynos_clock->mux_stat_cpu);
	} while ((val | HPM_SEL_SCLK_MPLL) != val);

	val = arm_clk_ratio->arm2_ratio << 28
		| arm_clk_ratio->apll_ratio << 24
		| arm_clk_ratio->pclk_dbg_ratio << 20
		| arm_clk_ratio->atb_ratio << 16
		| arm_clk_ratio->periph_ratio << 12
		| arm_clk_ratio->acp_ratio << 8
		| arm_clk_ratio->cpud_ratio << 4
		| arm_clk_ratio->arm_ratio;
	writel(val, &exynos_clock->div_cpu0);
	do {
		val = readl(&exynos_clock->div_stat_cpu0);
	} while (0 != val);

	writel(CLK_DIV_CPU1_VAL, &exynos_clock->div_cpu1);
	do {
		val = readl(&exynos_clock->div_stat_cpu1);
	} while (0 != val);

	/* switch A15 clock source to OSC clock before changing APLL */
	clrbits_le32(&exynos_clock->src_cpu, APLL_FOUT);

	/* Set APLL */
	writel(APLL_CON1_VAL, &exynos_clock->apll_con1);
	val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
			arm_clk_ratio->apll_sdiv);
	writel(val, &exynos_clock->apll_con0);
	while ((readl(&exynos_clock->apll_con0) & APLL_CON0_LOCKED) == 0)
		;

	/* now it is safe to switch to APLL */
	setbits_le32(&exynos_clock->src_cpu, APLL_FOUT);

	/* Set MPLL */
	writel(MPLL_CON1_VAL, &exynos_clock->mpll_con1);
	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
	writel(val, &exynos_clock->mpll_con0);
	while ((readl(&exynos_clock->mpll_con0) & MPLL_CON0_LOCKED) == 0)
		;

	/*
	 * Configure MUX_MPLL_FOUT to choose the direct clock source
	 * path and avoid the fixed DIV/2 block to save power
	 */
	setbits_le32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL);

//.........这里部分代码省略.........

static void rk_edp_enable_sw_function(struct rk3288_edp *regs)
{
	clrbits_le32(&regs->func_en_1, SW_FUNC_EN_N);
}

static void read_write_byte(struct s3c24x0_i2c *i2c)
{
	clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
}

/*
 * scan_mgr_io_scan_chain_prg
 * Program HPS IO Scan Chain
 */
unsigned long
scan_mgr_io_scan_chain_prg(
	IOScanChainSelect io_scan_chain_id,
	uint32_t io_scan_chain_len_in_bits,
	const unsigned long *iocsr_scan_chain)
{

	uint16_t tdi_tdo_header;
	uint32_t io_program_iter;
	uint32_t io_scan_chain_data_residual;
	uint32_t residual;
	uint32_t i;
	uint32_t index = 0;

	/*
	 * Check if IO bank is in frozen state before proceed to program IO
	 * scan chain.
	 * Note: IO scan chain ID is 1:1 mapping to freeze channel ID
	 */
	DEBUG_MEMORY
	 if (sys_mgr_frzctrl_frzchn_is_frozen(io_scan_chain_id)) {

		/* De-assert reinit if the IO scan chain is intended for HIO */
		if (IO_SCAN_CHAIN_3 == io_scan_chain_id) {
			DEBUG_MEMORY
			clrbits_le32((SOCFPGA_SYSMGR_ADDRESS+
				SYSMGR_FRZCTRL_HIOCTRL_ADDRESS),
				SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
		} /* if (HIO) */

		/*
		 * Check if the scan chain engine is inactive and the
		 * WFIFO is empty before enabling the IO scan chain
		 */
		if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
			!= scan_mgr_io_scan_chain_engine_is_idle(
			MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
			DEBUG_MEMORY
			return 1;
		}

		/*
		 * Enable IO Scan chain based on scan chain id
		 * Note: only one chain can be enabled at a time
		 */
		setbits_le32((SOCFPGA_SCANMGR_ADDRESS +
			SCANMGR_EN_ADDRESS),
			1 << io_scan_chain_id);

		/*
		 * Calculate number of iteration needed for
		 * full 128-bit (4 x32-bits) bits shifting.
		 * Each TDI_TDO packet can shift in maximum 128-bits
		 */
		io_program_iter
			= io_scan_chain_len_in_bits >>
			IO_SCAN_CHAIN_128BIT_SHIFT;
		io_scan_chain_data_residual
			= io_scan_chain_len_in_bits &
			IO_SCAN_CHAIN_128BIT_MASK;

		/*
		 * Construct TDI_TDO packet for
		 * 128-bit IO scan chain (2 bytes)
		 */
		tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE
			| (TDI_TDO_MAX_PAYLOAD <<
			TDI_TDO_HEADER_SECOND_BYTE_SHIFT);

		/* Program IO scan chain in 128-bit iteration */
		DEBUG_MEMORY
		for (i = 0; i < io_program_iter; i++) {

			/* write TDI_TDO packet header to scan manager */
			writel(tdi_tdo_header,
				(SOCFPGA_SCANMGR_ADDRESS +
				SCANMGR_FIFODOUBLEBYTE_ADDRESS));

			/* calculate array index */
			index = i * 4;

			/*
			 * write 4 successive 32-bit IO scan
			 * chain data into WFIFO
			 */
			writel(iocsr_scan_chain[index],
				(SOCFPGA_SCANMGR_ADDRESS +
				SCANMGR_FIFOQUADBYTE_ADDRESS));
			writel(iocsr_scan_chain[index + 1],
				(SOCFPGA_SCANMGR_ADDRESS +
				SCANMGR_FIFOQUADBYTE_ADDRESS));
			writel(iocsr_scan_chain[index + 2],
				(SOCFPGA_SCANMGR_ADDRESS +
				SCANMGR_FIFOQUADBYTE_ADDRESS));
			writel(iocsr_scan_chain[index + 3],
				(SOCFPGA_SCANMGR_ADDRESS +
//.........这里部分代码省略.........

static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
		     const void *dout, void *din, unsigned long flags)
{
	unsigned int tmpdout, tmpdin;
	int tm, isread = 0;

	debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);

	if (flags & SPI_XFER_BEGIN)
		_spi_cs_activate(reg);

	/*
	 * handle data in 8-bit chunks
	 * TBD: 2byte xfer mode to be enabled
	 */
	clrsetbits_le32(&reg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);

	while (bitlen > 4) {
		debug("loopstart bitlen %d\n", bitlen);
		tmpdout = 0;

		/* Shift data so it's msb-justified */
		if (dout)
			tmpdout = *(u32 *)dout & 0xff;

		clrbits_le32(&reg->irq_cause, KWSPI_SMEMRDIRQ);
		writel(tmpdout, &reg->dout);	/* Write the data out */
		debug("*** spi_xfer: ... %08x written, bitlen %d\n",
		      tmpdout, bitlen);

		/*
		 * Wait for SPI transmit to get out
		 * or time out (1 second = 1000 ms)
		 * The NE event must be read and cleared first
		 */
		for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
			if (readl(&reg->irq_cause) & KWSPI_SMEMRDIRQ) {
				isread = 1;
				tmpdin = readl(&reg->din);
				debug("spi_xfer: din %p..%08x read\n",
				      din, tmpdin);

				if (din) {
					*((u8 *)din) = (u8)tmpdin;
					din += 1;
				}
				if (dout)
					dout += 1;
				bitlen -= 8;
			}
			if (isread)
				break;
		}
		if (tm >= KWSPI_TIMEOUT)
			printf("*** spi_xfer: Time out during SPI transfer\n");

		debug("loopend bitlen %d\n", bitlen);
	}

	if (flags & SPI_XFER_END)
		_spi_cs_deactivate(reg);

	return 0;
}

static void mxs_power_init_4p2_regulator(void)
{
	struct mxs_power_regs *power_regs =
		(struct mxs_power_regs *)MXS_POWER_BASE;
	uint32_t tmp, tmp2;

	setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);

	writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);

	writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
		&power_regs->hw_power_5vctrl_clr);
	clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);

	/* Power up the 4p2 rail and logic/control */
	writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
		&power_regs->hw_power_5vctrl_clr);

	/*
	 * Start charging up the 4p2 capacitor. We ramp of this charge
	 * gradually to avoid large inrush current from the 5V cable which can
	 * cause transients/problems
	 */
	mxs_enable_4p2_dcdc_input(0);

	if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
		/*
		 * If we arrived here, we were unable to recover from mx23 chip
		 * errata 5837. 4P2 is disabled and sufficient battery power is
		 * not present. Exiting to not enable DCDC power during 5V
		 * connected state.
		 */
		clrbits_le32(&power_regs->hw_power_dcdc4p2,
			POWER_DCDC4P2_ENABLE_DCDC);
		writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
			&power_regs->hw_power_5vctrl_set);
		hang();
	}

	/*
	 * Here we set the 4p2 brownout level to something very close to 4.2V.
	 * We then check the brownout status. If the brownout status is false,
	 * the voltage is already close to the target voltage of 4.2V so we
	 * can go ahead and set the 4P2 current limit to our max target limit.
	 * If the brownout status is true, we need to ramp us the current limit
	 * so that we don't cause large inrush current issues. We step up the
	 * current limit until the brownout status is false or until we've
	 * reached our maximum defined 4p2 current limit.
	 */
	clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
			POWER_DCDC4P2_BO_MASK,
			22 << POWER_DCDC4P2_BO_OFFSET);	/* 4.15V */

	if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
		setbits_le32(&power_regs->hw_power_5vctrl,
			0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
	} else {
		tmp = (readl(&power_regs->hw_power_5vctrl) &
			POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
			POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
		while (tmp < 0x3f) {
			if (!(readl(&power_regs->hw_power_sts) &
					POWER_STS_DCDC_4P2_BO)) {
				tmp = readl(&power_regs->hw_power_5vctrl);
				tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
				early_delay(100);
				writel(tmp, &power_regs->hw_power_5vctrl);
				break;
			} else {
				tmp++;
				tmp2 = readl(&power_regs->hw_power_5vctrl);
				tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
				tmp2 |= tmp <<
					POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
				writel(tmp2, &power_regs->hw_power_5vctrl);
				early_delay(100);
			}
		}
	}

	clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
	writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
}

static void sdio_pwr_off(unsigned port)
{
	setbits_le32(P_PREG_CGPIO_O,(1<<12));
	clrbits_le32(P_PREG_CGPIO_EN_N,(1<<12));
}

static void hdmi_tx_set_hdmi_5v(void)
{
	/*Power on VCC_5V for HDMI_5V*/
	clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
}

void lowlevel_init(void* cur,void * target)
{
    int i;
#if 0    
	if(cur != target) //r0!=r1
	{
	    //running from spi
    	// take me as a spi rom boot mode
		romboot_info->por_cfg = POR_INTL_SPI |
		    (READ_CBUS_REG(ASSIST_POR_CONFIG)&(~POR_INTL_CFG_MASK));
		romboot_info->boot_id = 0;//boot from spi
		/// Release pull up registers .
	}
#endif	
	 //gpiob_8 
    clrbits_le32(P_PREG_GGPIO_O, 1<<16);
    clrbits_le32(P_PREG_GGPIO_EN_N, 1<<16);
    //gpiob_5 
    clrbits_le32(P_PREG_GGPIO_O, 1<<13);
    clrbits_le32(P_PREG_GGPIO_EN_N, 1<<13);
	//writel((1<<22)|100000,P_WATCHDOG_TC);//enable Watchdog 1 seconds
	//Adjust 1us timer base
	//clrbits_le32(P_PREG_FGPIO_O, 1<<21);
	//mute
//	setbits_le32(P_PREG_GGPIO_O, 1<<5);
//	clrbits_le32(P_PREG_GGPIO_EN_N, 1<<5);
//	//vcc_12v/24v power down GPIOX_70
//	setbits_le32(P_PREG_GGPIO_O, 1<<6);
//	clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
//	bl
//	setbits_le32(P_PREG_FGPIO_O, 1<<21);
//	clrbits_le32(P_PREG_FGPIO_EN_N, 1<<21);

	//Wr(REG_LVDS_PHY_CNTL4, 0);//LVDS_MDR_PU

	//clrbits_le32(P_PREG_GGPIO_O, 1<<6);
	//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
	WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
	/*
        Select TimerE 1 us base
    */
	clrsetbits_le32(P_ISA_TIMER_MUX,0x7<<8,0x1<<8);


	if(1)
	{
		writel(0,P_WATCHDOG_TC);//disable Watchdog   
		//while(1)
		{
			__udelay(50000);
		}
	}
	
    memory_pll_init(0,NULL);
	//serial_put_dword(get_timer(0));
	//serial_put_dword(readl(0xc1100000+0x200b*4));
#if CONFIG_ENABLE_SPL_DEBUG_ROM
    __udelay(100000);//wait for a uart input 
	if(serial_tstc()){
		writel(0,P_WATCHDOG_TC);//disable Watchdog	  
	    debug_rom(__FILE__,__LINE__);
		}
#else
    __udelay(1000);//delay 1 ms , wait pll ready	
#endif	

#if 1
#if CONFIG_ENABLE_SPL_DEBUG_ROM	
	if(ddr_init_test()){
		writel(0,P_WATCHDOG_TC);//disable Watchdog	  
	    debug_rom(__FILE__,__LINE__);
		}
#else

    do{
    }while(ddr_init_test(0x6));
#endif	    
#endif
	writel(0,P_WATCHDOG_TC);//disable Watchdog    
	//serial_puts("\nM2C (Haier TV) Systemp Started\n");
}

/*
 * flushes the i2stx fifo
 *
 * @param i2s_reg	i2s regiter address
 * @param flush		Tx fifo flush command (0x00 - do not flush
 *				0x80 - flush tx fifo)
 */
void i2s_fifo(struct exynos5_i2s *i2s_reg, unsigned int flush)
{
	/* Flush the FIFO */
	setbits_le32(&i2s_reg->fic, flush);
	clrbits_le32(&i2s_reg->fic, flush);
}

/* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */
void usb_setup_utmip(void *usb_base)
{
	struct usb_ctlr *usb = (struct usb_ctlr *)usb_base;

	/* KHz formulas were guessed from U-Boot constants. Formats unclear. */
	int khz = clock_get_pll_input_khz();

	/* Stop UTMI+ crystal clock while we mess with its settings */
	clrbits_le32(&usb->utmip.misc1, 1 << 30);	/* PHY_XTAL_CLKEN */
	udelay(1);

	/* Take stuff out of pwrdn and add some magic numbers from U-Boot */
	write32(0x8 << 25 |		/* HS slew rate [10:4] */
		0x3 << 22 |		/* HS driver output 'SETUP' [6:4] */
		0 << 21 |		/* LS bias selection */
		0 << 18 |		/* PDZI pwrdn */
		0 << 16 |		/* PD2 pwrdn */
		0 << 14 |		/* PD pwrdn */
		1 << 13 |		/* (rst) HS receiver terminations */
		0x1 << 10 |		/* (rst) LS falling slew rate */
		0x1 << 8 |		/* (rst) LS rising slew rate */
		0x4 << 0 |		/* HS driver output 'SETUP' [3:0] */
		0, &usb->utmip.xcvr0);
	write32(0x7 << 18 |		/* Termination range adjustment */
		0 << 4 |		/* PDDR pwrdn */
		0 << 2 |		/* PDCHRP pwrdn */
		0 << 0 |		/* PDDISC pwrdn */
		0, &usb->utmip.xcvr1);
	write32(1 << 19 |		/* FS send initial J before sync(?) */
		1 << 16 |		/* (rst) Allow stuff error on SoP */
		1 << 9 |		/* (rst) Check disc only on EoP */
		0, &usb->utmip.tx);
	write32(0x2 << 30 |		/* (rst) Keep pattern on active */
		1 << 28 |		/* (rst) Realign inertia on pkt */
		0x1 << 24 |		/* (rst) edges-1 to move sampling */
		0x3 << 21 |		/* (rst) squelch delay on EoP */
		0x11 << 15 |		/* cycles until IDLE */
		0x10 << 10 |		/* elastic input depth */
		0, &usb->utmip.hsrx0);

	/* U-Boot claims the USBD values for these are used across all UTMI+
	 * PHYs. That sounds so horribly wrong that I'm not going to implement
	 * it, but keep it in mind if we're ever not using the USBD port. */
	write32(0x1 << 24 |		/* HS disconnect detect level [2] */
		1 << 23 |		/* (rst) IDPD value */
		1 << 22 |		/* (rst) IDPD select */
		1 << 11 |		/* (rst) OTG pwrdn */
		0 << 10 |		/* bias pwrdn */
		0x1 << 2 |		/* HS disconnect detect level [1:0] */
		0x2 << 0 |		/* HS squelch detect level */
		0, &usb->utmip.bias0);

	write32(khz / 2200 << 3 |	/* bias pwrdn cycles (20us?) */
		1 << 2 |		/* (rst) VBUS wakeup pwrdn */
		0 << 0 |		/* PDTRK pwrdn */
		0, &usb->utmip.bias1);

	write32(0xffff << 16 |		/* (rst) */
		25 * khz / 10 << 0 |	/* TODO: what's this, really? */
		0, &usb->utmip.debounce);

	udelay(1);
	setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */

	write32(1 << 12 |		/* UTMI+ enable */
		0 << 11 |		/* UTMI+ reset */
		0, &usb->suspend_ctrl);

	usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP);
	printk(BIOS_DEBUG, "USB controller @ %p set up with UTMI+ PHY\n",usb_base);
}

//POWER key
inline void key_init(void)
{
	clrbits_le32(P_RTC_ADDR0, (1<<11));
	clrbits_le32(P_RTC_ADDR1, (1<<3));
}

/******************************************************************************
 * prcm_init() - inits clocks for PRCM as defined in clocks.h
 *               called from SRAM, or Flash (using temp SRAM stack).
 *****************************************************************************/
void prcm_init(void)
{
    u32 osc_clk = 0, sys_clkin_sel;
    u32 clk_index, sil_index = 0;
    struct prm *prm_base = (struct prm *)PRM_BASE;
    struct prcm *prcm_base = (struct prcm *)PRCM_BASE;

    /*
     * Gauge the input clock speed and find out the sys_clkin_sel
     * value corresponding to the input clock.
     */
    osc_clk = get_osc_clk_speed();
    get_sys_clkin_sel(osc_clk, &sys_clkin_sel);

    /* set input crystal speed */
    clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);

    /* If the input clock is greater than 19.2M always divide/2 */
    if (sys_clkin_sel > 2) {
        /* input clock divider */
        clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
        clk_index = sys_clkin_sel / 2;
    } else {
        /* input clock divider */
        clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
        clk_index = sys_clkin_sel;
    }

    if (get_cpu_family() == CPU_OMAP36XX) {
        /*
         * In warm reset conditions on OMAP36xx/AM/DM37xx
         * the rom code incorrectly sets the DPLL4 clock
         * input divider to /6.5. Section 3.5.3.3.3.2.1 of
         * the AM/DM37x TRM explains that the /6.5 divider
         * is used only when the input clock is 13MHz.
         *
         * If the part is in this cpu family *and* the input
         * clock *is not* 13 MHz, then reset the DPLL4 clock
         * input divider to /1 as it should never set to /6.5
         * in this case.
         */
        if (sys_clkin_sel != 1) {	/* 13 MHz */
            /* Bit 8: DPLL4_CLKINP_DIV */
            clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
        }

        /* Unlock MPU DPLL (slows things down, and needed later) */
        clrsetbits_le32(&prcm_base->clken_pll_mpu,
                        0x00000007, PLL_LOW_POWER_BYPASS);
        wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
                      LDELAY);

        dpll3_init_36xx(0, clk_index);
        dpll4_init_36xx(0, clk_index);
        dpll5_init_36xx(0, clk_index);
        iva_init_36xx(0, clk_index);
        mpu_init_36xx(0, clk_index);

        /* Lock MPU DPLL to set frequency */
        clrsetbits_le32(&prcm_base->clken_pll_mpu,
                        0x00000007, PLL_LOCK);
        wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
                      LDELAY);
    } else {
        /*
         * The DPLL tables are defined according to sysclk value and
         * silicon revision. The clk_index value will be used to get
         * the values for that input sysclk from the DPLL param table
         * and sil_index will get the values for that SysClk for the
         * appropriate silicon rev.
         */
        if (((get_cpu_family() == CPU_OMAP34XX)
                && (get_cpu_rev() >= CPU_3XX_ES20)) ||
                (get_cpu_family() == CPU_AM35XX))
            sil_index = 1;

        /* Unlock MPU DPLL (slows things down, and needed later) */
        clrsetbits_le32(&prcm_base->clken_pll_mpu,
                        0x00000007, PLL_LOW_POWER_BYPASS);
        wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
                      LDELAY);

        dpll3_init_34xx(sil_index, clk_index);
        dpll4_init_34xx(sil_index, clk_index);
        dpll5_init_34xx(sil_index, clk_index);
        if (get_cpu_family() != CPU_AM35XX)
            iva_init_34xx(sil_index, clk_index);

        mpu_init_34xx(sil_index, clk_index);

        /* Lock MPU DPLL to set frequency */
        clrsetbits_le32(&prcm_base->clken_pll_mpu,
                        0x00000007, PLL_LOCK);
        wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
                      LDELAY);
    }
//.........这里部分代码省略.........

static void rk_edp_enable_sw_function(struct rk_edp *edp)
{
	clrbits_le32(&edp->regs->func_en_1, SW_FUNC_EN_N);
}