C++ clrbits8函数代码示例

static void t102xqds_set_monitor_port(enum fsl_diu_monitor_port port)
{
	struct device_node *pixis_node;
	void __iomem *pixis;

	pixis_node = of_find_compatible_node(NULL, NULL, "fsl,tetra-fpga");
	if (!pixis_node) {
		pr_err("t102xqds: missing pixis node\n");
		goto exit;
	}

	pixis = of_iomap(pixis_node, 0);
	of_node_put(pixis_node);
	if (!pixis) {
		pr_err("t102xqds: could not map pixis registers\n");
		goto exit;
	}

	/* Route I2C4 to DIU system as HSYNC/VSYNC */
	clrbits8(pixis + BRDCFG5, BRDCFG5_IMX_DIU_LOW);
	setbits8(pixis + BRDCFG5, BRDCFG5_IMX_DIU_HIGH);

	switch (port) {
	case FSL_DIU_PORT_DVI:
		/* Enable the DVI(HDMI) port, disable the DFP and
		 * the backlight
		 */
		clrbits8(pixis + BRDCFG15, BRDCFG15_LCD_ENABLED);
		setbits8(pixis + BRDCFG15, BRDCFG15_LCD_PD);

		clrbits8(pixis + BRDCFG15, BRDCFG15_DIUSEL_HDMI);
		break;
	case FSL_DIU_PORT_LVDS:
		/*
		 * LVDS also needs backlight enabled, otherwise the display
		 * will be blank.
		 */
		/* Enable the DFP port, disable the DVI*/
		setbits8(pixis + BRDCFG15, BRDCFG15_DIUSEL_LVDS);

		clrbits8(pixis + BRDCFG15, BRDCFG15_LCD_PD);
		setbits8(pixis + BRDCFG15, BRDCFG15_LCD_ENABLED);
		break;
	default:
		pr_err("%s: Unsupported monitor port %i\n", __func__, port);
	}

	iounmap(pixis);

exit:
	return;
}

static void direct_access_pixis_reset_pcie_slot(void)
{
	struct device_node *pixis_node;
	void __iomem *pixis;

	/* Map the pixis registers. */
	pixis_node =
		of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
	if (!pixis_node) {
		pr_err("p1022ds: missing pixis node\n");
		return;
	}

	pixis = of_iomap(pixis_node, 0);
	of_node_put(pixis_node);
	if (!pixis) {
		pr_err("p1022ds: could not map pixis registers\n");
		return;
	}

	/* Rset PCIE slot */
	/* power down pcie slot */
	clrbits8(pixis + PX_RST, PX_RST_PCIE);

	/* power up pcie slot */
	setbits8(pixis + PX_RST, PX_RST_PCIE);

	iounmap(pixis);
}

static int cpm_uart_startup(struct uart_port *port)
{
	int retval;
	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;

	pr_debug("CPM uart[%d]:startup\n", port->line);

	/* If the port is not the console, make sure rx is disabled. */
	if (!(pinfo->flags & FLAG_CONSOLE)) {
		/* Disable UART rx */
		if (IS_SMC(pinfo)) {
			clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
			clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
		} else {
			clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
			clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
		}
		cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
	}
	/* Install interrupt handler. */
	retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
	if (retval)
		return retval;

	/* Startup rx-int */
	if (IS_SMC(pinfo)) {
		setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
		setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
	} else {
		setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
		setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
	}

	return 0;
}

/*
 * Initialize port. This is called from early_console stuff
 * so we have to be careful here !
 */
static int cpm_uart_request_port(struct uart_port *port)
{
	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
	int ret;

	pr_debug("CPM uart[%d]:request port\n", port->line);

	if (pinfo->flags & FLAG_CONSOLE)
		return 0;

	if (IS_SMC(pinfo)) {
		clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
		clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
	} else {
		clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
		clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
	}

	ret = cpm_uart_allocbuf(pinfo, 0);

	if (ret)
		return ret;

	cpm_uart_initbd(pinfo);
	if (IS_SMC(pinfo))
		cpm_uart_init_smc(pinfo);
	else
		cpm_uart_init_scc(pinfo);

	return 0;
}

static int __init ppc460ex_canyonlands_fixup(void)
{
	u8 __iomem *bcsr ;
	void __iomem *vaddr;
	struct device_node *np;
	int ret = 0;

	np = of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-bcsr");
	if (!np) {
		printk(KERN_ERR "failed did not find amcc, ppc460ex bcsr node\n");
		return -ENODEV;
	}

	bcsr = of_iomap(np, 0);
	of_node_put(np);

	if (!bcsr) {
		printk(KERN_CRIT "Could not remap bcsr\n");
		ret = -ENODEV;
		goto err_bcsr;
	}

	np = of_find_compatible_node(NULL, NULL, "ibm,ppc4xx-gpio");
	if (!np) {
		printk(KERN_ERR "failed did not find ibm,ppc4xx-gpio node\n");
		return -ENODEV;
	}

	vaddr = of_iomap(np, 0);
	of_node_put(np);

	if (!vaddr) {
		printk(KERN_CRIT "Could not get gpio node address\n");
		ret = -ENODEV;
		goto err_gpio;
	}
	/* Disable USB, through the BCSR7 bits */
	setbits8(&bcsr[7], BCSR_USB_EN);

	/* Wait for a while after reset */
	msleep(100);

	/* Enable USB here */
	clrbits8(&bcsr[7], BCSR_USB_EN);

	/*
	 * Configure multiplexed gpio16 and gpio19 as alternate1 output
	 * source after USB reset. In this configuration gpio16 will be
	 * USB2HStop and gpio19 will be USB2DStop. For more details refer to
	 * table 34-7 of PPC460EX user manual.
	 */
	setbits32((vaddr + GPIO0_OSRH), 0x42000000);
	setbits32((vaddr + GPIO0_TSRH), 0x42000000);
err_gpio:
	iounmap(vaddr);
err_bcsr:
	iounmap(bcsr);
	return ret;
}

void sbc8560_rstcr_restart(char * cmd)
{
	local_irq_disable();
	if(brstcr)
		clrbits8(brstcr, 0x80);

	while(1);
}

static void fhci_stop_sof_timer(struct fhci_hcd *fhci)
{
	fhci_dbg(fhci, "-> %s\n", __func__);

	clrbits8(&fhci->regs->usb_mod, USB_MODE_SFTE);
	qe_stop_timer(fhci->timer);

	fhci_dbg(fhci, "<- %s\n", __func__);
}

/*
 * Stop receiver
 */
static void cpm_uart_stop_rx(struct uart_port *port)
{
	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
	smc_t __iomem *smcp = pinfo->smcp;
	scc_t __iomem *sccp = pinfo->sccp;

	pr_debug("CPM uart[%d]:stop rx\n", port->line);

	if (IS_SMC(pinfo))
		clrbits8(&smcp->smc_smcm, SMCM_RX);
	else
		clrbits16(&sccp->scc_sccm, UART_SCCM_RX);
}

static void indirect_access_pixis_reset_pcie_slot(void)
{
	if (!verify_pixis_indirect_access_address()) {
		WARN_ON(1);
		return;
	}

	/* Set FPGA access address */
	out_8(lbc_lcs0_ba, PX_RST);

	/* power down pcie slot */
	clrbits8(lbc_lcs1_ba, PX_RST_PCIE);

	/* power up pcie slot */
	setbits8(lbc_lcs1_ba, PX_RST_PCIE);
}

static void __init mpc85xx_rds_setup_arch(void)
{
	struct device_node *np;

	if (ppc_md.progress)
		ppc_md.progress("p1023_rds_setup_arch()", 0);

	/*               */
	np = of_find_node_by_name(NULL, "bcsr");
	if (np != NULL) {
		static u8 __iomem *bcsr_regs;

		bcsr_regs = of_iomap(np, 0);
		of_node_put(np);

		if (!bcsr_regs) {
			printk(KERN_ERR
			       "BCSR: Failed to map bcsr register space\n");
			return;
		} else {
#define BCSR15_I2C_BUS0_SEG_CLR		0x07
#define BCSR15_I2C_BUS0_SEG2		0x02
/*
                                           
  
                                                                
                                                               
                                                                
 */
#ifdef CONFIG_RTC_CLASS
			/*                                          */
			clrbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG_CLR);
			setbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG2);
#endif

			iounmap(bcsr_regs);
		}
	}

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,p1023-pcie")
		fsl_add_bridge(np, 0);
#endif

	mpc85xx_smp_init();
}

/* ************************************************************************
 *
 * Setup the architecture
 *
 */
static void __init mpc85xx_rds_setup_arch(void)
{
	struct device_node *np;

	if (ppc_md.progress)
		ppc_md.progress("p1023_rds_setup_arch()", 0);

	/* Map BCSR area */
	np = of_find_node_by_name(NULL, "bcsr");
	if (np != NULL) {
		static u8 __iomem *bcsr_regs;

		bcsr_regs = of_iomap(np, 0);
		of_node_put(np);

		if (!bcsr_regs) {
			printk(KERN_ERR
			       "BCSR: Failed to map bcsr register space\n");
			return;
		} else {
#define BCSR15_I2C_BUS0_SEG_CLR		0x07
#define BCSR15_I2C_BUS0_SEG2		0x02
/*
 * Note: Accessing exclusively i2c devices.
 *
 * The i2c controller selects initially ID EEPROM in the u-boot;
 * but if menu configuration selects RTC support in the kernel,
 * the i2c controller switches to select RTC chip in the kernel.
 */
#ifdef CONFIG_RTC_CLASS
			/* Enable RTC chip on the segment #2 of i2c */
			clrbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG_CLR);
			setbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG2);
#endif

			iounmap(bcsr_regs);
		}
	}

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,p1023-pcie")
		fsl_add_bridge(np, 0);
#endif

	mpc85xx_smp_init();
}

/* ************************************************************************
 *
 * Setup the architecture
 *
 */
static void __init mpc832x_sys_setup_arch(void)
{
    struct device_node *np;
    u8 __iomem *bcsr_regs = NULL;

    if (ppc_md.progress)
        ppc_md.progress("mpc832x_sys_setup_arch()", 0);

    /* Map BCSR area */
    np = of_find_node_by_name(NULL, "bcsr");
    if (np) {
        struct resource res;

        of_address_to_resource(np, 0, &res);
        bcsr_regs = ioremap(res.start, res.end - res.start +1);
        of_node_put(np);
    }

#ifdef CONFIG_PCI
    for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
    mpc83xx_add_bridge(np);
#endif

#ifdef CONFIG_QUICC_ENGINE
    qe_reset();

    if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
        par_io_init(np);
        of_node_put(np);

        for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
            par_io_of_config(np);
    }

    if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
            != NULL) {
        /* Reset the Ethernet PHYs */
#define BCSR8_FETH_RST 0x50
        clrbits8(&bcsr_regs[8], BCSR8_FETH_RST);
        udelay(1000);
        setbits8(&bcsr_regs[8], BCSR8_FETH_RST);
        iounmap(bcsr_regs);
        of_node_put(np);
    }
#endif				/* CONFIG_QUICC_ENGINE */
}

static int mpc837xmds_usb_cfg(void)
{
	struct device_node *np;
	const void *phy_type, *mode;
	void __iomem *bcsr_regs = NULL;
	u8 bcsr12;
	int ret;

	ret = mpc837x_usb_cfg();
	if (ret)
		return ret;
	/* Map BCSR area */
	np = of_find_compatible_node(NULL, NULL, "fsl,mpc837xmds-bcsr");
	if (np) {
		bcsr_regs = of_iomap(np, 0);
		of_node_put(np);
	}
	if (!bcsr_regs)
		return -1;

	np = of_find_node_by_name(NULL, "usb");
	if (!np) {
		ret = -ENODEV;
		goto out;
	}
	phy_type = of_get_property(np, "phy_type", NULL);
	if (phy_type && !strcmp(phy_type, "ulpi")) {
		clrbits8(bcsr_regs + 12, BCSR12_USB_SER_PIN);
	} else if (phy_type && !strcmp(phy_type, "serial")) {
		mode = of_get_property(np, "dr_mode", NULL);
		bcsr12 = in_8(bcsr_regs + 12) & ~BCSR12_USB_SER_MASK;
		bcsr12 |= BCSR12_USB_SER_PIN;
		if (mode && !strcmp(mode, "peripheral"))
			bcsr12 |= BCSR12_USB_SER_DEVICE;
		out_8(bcsr_regs + 12, bcsr12);
	} else {
		printk(KERN_ERR "USB DR: unsupported PHY\n");
	}

	of_node_put(np);
out:
	iounmap(bcsr_regs);
	return ret;
}

/*
 * Shutdown the uart
 */
static void cpm_uart_shutdown(struct uart_port *port)
{
	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;

	pr_debug("CPM uart[%d]:shutdown\n", port->line);

	/* free interrupt handler */
	free_irq(port->irq, port);

	/* If the port is not the console, disable Rx and Tx. */
	if (!(pinfo->flags & FLAG_CONSOLE)) {
		/* Wait for all the BDs marked sent */
		while(!cpm_uart_tx_empty(port)) {
			set_current_state(TASK_UNINTERRUPTIBLE);
			schedule_timeout(2);
		}

		if (pinfo->wait_closing)
			cpm_uart_wait_until_send(pinfo);

		/* Stop uarts */
		if (IS_SMC(pinfo)) {
			smc_t __iomem *smcp = pinfo->smcp;
			clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
			clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX);
		} else {
			scc_t __iomem *sccp = pinfo->sccp;
			clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
			clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
		}

		/* Shut them really down and reinit buffer descriptors */
		if (IS_SMC(pinfo)) {
			out_be16(&pinfo->smcup->smc_brkcr, 0);
			cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
		} else {
			out_be16(&pinfo->sccup->scc_brkcr, 0);
			cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
		}

		cpm_uart_initbd(pinfo);
	}
}

/**
 * t1042rdb_set_monitor_port: switch the output to a different monitor port
 */
static void t1042rdb_set_monitor_port(enum fsl_diu_monitor_port port)
{
	struct device_node *cpld_node;
	static void __iomem *cpld_base;

	cpld_node = of_find_matching_node_and_match(NULL, corenet_cpld_matches,
						    NULL);
	if (!cpld_node) {
		pr_err("%s: Missing CPLD node\n", __func__);
		return;
	}

	cpld_base = of_iomap(cpld_node, 0);
	if (!cpld_base) {
		pr_err("%s: Could not map cpld registers\n", __func__);
		goto exit;
	}

	switch (port) {
	case FSL_DIU_PORT_DVI:
		/* Enable the DVI(HDMI) port, disable the DFP and
		 * the backlight
		 */
		clrbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_DVIEN);
		break;
	case FSL_DIU_PORT_LVDS:
		/*
		 * LVDS also needs backlight enabled, otherwise the display
		 * will be blank.
		 */
		/* Enable the DFP port, disable the DVI*/
		setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 8);
		setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 4);
		setbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_BACKLIGHT);
		break;
	default:
		pr_err("%s: Unsupported monitor port %i\n", __func__, port);
	}

	iounmap(cpld_base);
exit:
	of_node_put(cpld_node);
}