C++ clocksource_register函数代码示例

__init void plat_time_init(void)
{
	unsigned int configPR;
	unsigned int n;
	unsigned int m;
	unsigned int p;
	unsigned int pow2p;

	pnx8xxx_clockevent.cpumask = cpu_none_mask;
	clockevents_register_device(&pnx8xxx_clockevent);
	clocksource_register(&pnx_clocksource);

	/* Timer 1 start */
	configPR = read_c0_config7();
	configPR &= ~0x00000008;
	write_c0_config7(configPR);

	/* Timer 2 start */
	configPR = read_c0_config7();
	configPR &= ~0x00000010;
	write_c0_config7(configPR);

	/* Timer 3 stop */
	configPR = read_c0_config7();
	configPR |= 0x00000020;
	write_c0_config7(configPR);


        /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */
        /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1:  FIXME) */

        n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16;
        m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8;
        p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2;
	pow2p = (1 << p);

	db_assert(m != 0 && pow2p != 0);

        /*
	 * Compute the frequency as in the PNX8550 User Manual 1.0, p.186
	 * (a.k.a. 8-10).  Divide by HZ for a timer offset that results in
	 * HZ timer interrupts per second.
	 */
	mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p));
	cpj = (mips_hpt_frequency + HZ / 2) / HZ;
	write_c0_count(0);
	timer_ack();

	/* Setup Timer 2 */
	write_c0_count2(0);
	write_c0_compare2(0xffffffff);

	setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq);
	setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
}

static void __init ns9360_timer_init(void)
{
	int tc;

	tc = __raw_readl(SYS_TC(TIMER_CLOCKSOURCE));
	if (REGGET(tc, SYS_TCx, TEN)) {
		REGSET(tc, SYS_TCx, TEN, DIS);
		__raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
	}

	__raw_writel(0, SYS_TRC(TIMER_CLOCKSOURCE));

	REGSET(tc, SYS_TCx, TEN, EN);
	REGSET(tc, SYS_TCx, TDBG, STOP);
	REGSET(tc, SYS_TCx, TLCS, CPU);
	REGSET(tc, SYS_TCx, TM, IEE);
	REGSET(tc, SYS_TCx, INTS, DIS);
	REGSET(tc, SYS_TCx, UDS, UP);
	REGSET(tc, SYS_TCx, TSZ, 32);
	REGSET(tc, SYS_TCx, REN, EN);

	__raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));

	ns9360_clocksource.mult = clocksource_hz2mult(ns9360_cpuclock(),
			ns9360_clocksource.shift);

	clocksource_register(&ns9360_clocksource);

	latch = SH_DIV(ns9360_cpuclock(), HZ, 0);

	tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
	REGSET(tc, SYS_TCx, TEN, DIS);
	REGSET(tc, SYS_TCx, TDBG, STOP);
	REGSET(tc, SYS_TCx, TLCS, CPU);
	REGSET(tc, SYS_TCx, TM, IEE);
	REGSET(tc, SYS_TCx, INTS, DIS);
	REGSET(tc, SYS_TCx, UDS, DOWN);
	REGSET(tc, SYS_TCx, TSZ, 32);
	REGSET(tc, SYS_TCx, REN, EN);
	__raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));

	ns9360_clockevent_device.mult = div_sc(ns9360_cpuclock(),
			NSEC_PER_SEC, ns9360_clockevent_device.shift);
	ns9360_clockevent_device.max_delta_ns =
		clockevent_delta2ns(-1, &ns9360_clockevent_device);
	ns9360_clockevent_device.min_delta_ns =
		clockevent_delta2ns(1, &ns9360_clockevent_device);

	ns9360_clockevent_device.cpumask = cpumask_of(0);
	clockevents_register_device(&ns9360_clockevent_device);

	setup_irq(IRQ_NS9360_TIMER0 + TIMER_CLOCKEVENT,
			&ns9360_clockevent_action);
}

static int __init bfin_clocksource_init(void)
{
    set_cyc2ns_scale(get_cclk() / 1000);

    clocksource_bfin.mult = clocksource_hz2mult(get_cclk(), clocksource_bfin.shift);

    if (clocksource_register(&clocksource_bfin))
        panic("failed to register clocksource");

    return 0;
}

static void __init meson_clocksource_init(void)
{
    CLEAR_CBUS_REG_MASK(ISA_TIMER_MUX, TIMER_E_INPUT_MASK);
    SET_CBUS_REG_MASK(ISA_TIMER_MUX, TIMERE_UNIT_1ms << TIMER_E_INPUT_BIT);
    WRITE_CBUS_REG(ISA_TIMERE, 0);

    clocksource_timer_e.shift = clocksource_hz2shift(24, 1000);
    clocksource_timer_e.mult =
    clocksource_khz2mult(1, clocksource_timer_e.shift);
    clocksource_register(&clocksource_timer_e);
}

/*!
 * This function is used to initialize the GPT as a clocksource and clockevent.
 * It is called by the start_kernel() during system startup.
 */
void __init mxc_init_time(void)
{
	int ret;
	unsigned long rate;
	u32 reg, div;

	/* Reset GPT */
	__raw_writel(GPTCR_SWR, MXC_GPT_GPTCR);
	while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0)
		mb();

	/* Normal clk api are not yet initialized, so use early verion */
	rate = clk_early_get_timer_rate();
	if (rate == 0)
		panic("MXC GPT: Can't get timer clock rate\n");

#ifdef CLOCK_TICK_RATE
	div = rate / CLOCK_TICK_RATE;
	WARN_ON((div * CLOCK_TICK_RATE) != rate);
#else				/* Hopefully CLOCK_TICK_RATE will go away soon */
	div = 1;
	while ((rate / div) > 20000000) {
		div++;
	}
#endif
	rate /= div;
	__raw_writel(div - 1, MXC_GPT_GPTPR);

	reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_ENABLE;
	__raw_writel(reg, MXC_GPT_GPTCR);

	gpt_clocksrc.mult = clocksource_hz2mult(rate, gpt_clocksrc.shift);
	ret = clocksource_register(&gpt_clocksrc);
	if (ret < 0) {
		goto err;
	}

	gpt_clockevent.mult = div_sc(rate, NSEC_PER_SEC, gpt_clockevent.shift);
	gpt_clockevent.max_delta_ns = clockevent_delta2ns(-1, &gpt_clockevent);
	gpt_clockevent.min_delta_ns = clockevent_delta2ns(1, &gpt_clockevent);

	gpt_clockevent.cpumask = cpumask_of_cpu(0);
	clockevents_register_device(&gpt_clockevent);

	ret = setup_irq(MXC_INT_GPT, &timer_irq);
	if (ret < 0) {
		goto err;
	}

	pr_info("MXC GPT timer initialized, rate = %lu\n", rate);
	return;
      err:
	panic("Unable to initialize timer\n");
}

static int __init mxc_clocksource_init(void)
{
	unsigned int clock;

	clock = clk_get_rate(timer_clk);

	clocksource_mxc.mult = clocksource_hz2mult(clock,
					clocksource_mxc.shift);
	clocksource_register(&clocksource_mxc);

	return 0;
}

static void __init meson_clocksource_init(void)
{
	CLEAR_CBUS_REG_MASK(ISA_TIMER_MUX, TIMER_E_INPUT_MASK);
	SET_CBUS_REG_MASK(ISA_TIMER_MUX, TIMERE_UNIT_1us << TIMER_E_INPUT_BIT);
	WRITE_CBUS_REG(ISA_TIMERE, 0);

	clocksource_timer_e.shift = clocksource_hz2shift(24, 1000000);
	clocksource_timer_e.mult  = clocksource_hz2mult(1000000, clocksource_timer_e.shift);
    
    clocksource_timer_f.shift = clocksource_timer_e.shift;
    //clocksource_timer_f.mult = ((clocksource_timer_e.mult)>>6)*64;
    clocksource_timer_f.mult = ((clocksource_timer_e.mult)>>6)*40;
    /*printk("Timer-E=%x,%x, Timer-F=%x,%x",
    clocksource_timer_e.shift,
    clocksource_timer_e.mult,
    clocksource_timer_f.shift,
    clocksource_timer_f.mult
     );*/
    clocksource_register(&clocksource_timer_e);
    clocksource_register(&clocksource_timer_f);
}

int __init ra_systick_clocksource_init(void)
{
	ra_systick_clocksource.rating = 350;
#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,13)
	clocksource_register_hz(&ra_systick_clocksource, 50000);
#else
    clocksource_set_clock(&ra_systick_clocksource, 50000);
    clocksource_register(&ra_systick_clocksource);
#endif    

	return 0;
}

static int __init bfin_cs_cycles_init(void)
{
	set_cyc2ns_scale(get_cclk() / 1000);

	bfin_cs_cycles.mult = \
		clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift);

	if (clocksource_register(&bfin_cs_cycles))
		panic("failed to register clocksource");

	return 0;
}

/*
 * timer_device_init()
 * 	Create and init a generic clock driver for Ubicom32.
 */
void timer_device_init(void)
{
	int i;
	const cpumask_t mask = (CPU_MASK_ALL);
	/*
	 * Get the frequency from the processor device tree node or use
	 * the default if not available. We will store this as the frequency
	 * of the timer to avoid future calculations.
	 */
	frequency = processor_frequency();
	if (frequency == 0) {
		frequency = CLOCK_TICK_RATE;
	}

	/*
	 * Setup the primary clock source around sysval.  Linux does not
	 * supply a Mhz multiplier so convert down to khz.
	 */
	timer_device_clockbase.mult =
		clocksource_khz2mult(frequency / 1000,
			timer_device_clockbase.shift);
	if (clocksource_register(&timer_device_clockbase)) {
		printk(KERN_ERR "timer: clocksource failed to register\n");
		return;
	}

	/*
	 * Always allocate a primary timer.
	 */
	timer_device_alloc_event("timer-primary", -1, &mask);

	/*
	 * Initialize the high resolution interface.
	 */
	timer_device_lock_acquire();
	timer_device_high_res = 0;
	timer_device_last_sysval = UBICOM32_IO_TIMER->sysval;
	timer_device_lock_release();

#if defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
	/*
	 * If BROADCAST is selected we need to add a broadcast timer.
	 */
	timer_device_alloc_event("timer-broadcast", -1, CPU_MASK_ALL);
#endif

	/*
	 * Allocate extra timers that are requested.
	 */
	for (i = 0; i < CONFIG_TIMER_EXTRA_ALLOC; i++) {
		timer_device_alloc_event("timer-extra", -1, &mask);
	}
}

static int __init bfin_cs_gptimer0_init(void)
{
	setup_gptimer0();

	bfin_cs_gptimer0.mult = \
		clocksource_hz2mult(get_sclk(), bfin_cs_gptimer0.shift);

	if (clocksource_register(&bfin_cs_gptimer0))
		panic("failed to register clocksource");

	return 0;
}

void __init mtu_timer_init(void)
{
	unsigned long rate;
	struct clk *clk0;

	clk0 = clk_get_sys("mtu0", NULL);
	BUG_ON(IS_ERR(clk0));

	rate = clk_get_rate(clk0);

	clk_enable(clk0);

	/*
	 * Set scale and timer for sched_clock
	 */
	setup_sched_clock(rate);
	u8500_cycle = (rate + HZ/2) / HZ;

	/* Save global pointer to mtu, used by functions above */
	if (cpu_is_u5500()) {
		mtu0_base = ioremap(U5500_MTU0_BASE, SZ_4K);
	} else if (cpu_is_u8500()) {
		mtu0_base = ioremap(U8500_MTU0_BASE, SZ_4K);
	} else {
		ux500_unknown_soc();
	}

	/* Restart clock source */
	mtu_clocksource_reset();

	/* Now the scheduling clock is ready */
	u8500_clksrc.read = u8500_read_timer;
	u8500_clksrc.mult = clocksource_hz2mult(rate, u8500_clksrc.shift);

	clocksource_register(&u8500_clksrc);

	/* Register irq and clockevents */

	/* We can sleep for max 10s (actually max is longer) */
	clockevents_calc_mult_shift(&u8500_mtu_clkevt, rate, 10);

	u8500_mtu_clkevt.max_delta_ns = clockevent_delta2ns(0xffffffff,
							    &u8500_mtu_clkevt);
	u8500_mtu_clkevt.min_delta_ns = clockevent_delta2ns(0xff,
							    &u8500_mtu_clkevt);

	setup_irq(IRQ_MTU0, &u8500_timer_irq);
	clockevents_register_device(&u8500_mtu_clkevt);
#ifdef ARCH_HAS_READ_CURRENT_TIMER
	set_delay_fn(mtu_timer_delay_loop);
#endif
}

static int __init mxc_clocksource_init(struct clk *timer_clk)
{
	unsigned int c = clk_get_rate(timer_clk);

	if (timer_is_v2())
		clocksource_mxc.read = v2_get_cycles;

	clocksource_mxc.mult = clocksource_hz2mult(c,
					clocksource_mxc.shift);
	clocksource_register(&clocksource_mxc);

	return 0;
}

static void __init realview_clocksource_init(void)
{
	/* setup timer 0 as free-running clocksource */
	writel(0, timer3_va_base + TIMER_CTRL);
	writel(0xffffffff, timer3_va_base + TIMER_LOAD);
	writel(0xffffffff, timer3_va_base + TIMER_VALUE);
	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
		timer3_va_base + TIMER_CTRL);

	clocksource_realview.mult =
		clocksource_khz2mult(1000, clocksource_realview.shift);
	clocksource_register(&clocksource_realview);
}

static void __init sec_init_clocksource(unsigned long rate)
{
	static char err[] __initdata = KERN_ERR
			"%s: can't register clocksource!\n";

	clocksource_sec.mult
		= clocksource_khz2mult(rate/1000, clocksource_sec.shift);

	sec_sched_timer_start(~0, 1);

	if (clocksource_register(&clocksource_sec))
		printk(err, clocksource_sec.name);
}