C++ clk_register_clkdev函数代码示例

/*
 * These are fixed clocks. They're probably not all root clocks and it may
 * be possible to turn them on and off but until this is mapped out better
 * it's the only way they can be used.
 */
void __init bcm2835_init_clocks(void)
{
	struct clk *clk;
	int ret;

	clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT,
					126000000);
	if (IS_ERR(clk))
		pr_err("apb_pclk not registered\n");

	clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, CLK_IS_ROOT,
					3000000);
	if (IS_ERR(clk))
		pr_err("uart0_pclk not registered\n");
	ret = clk_register_clkdev(clk, NULL, "20201000.uart");
	if (ret)
		pr_err("uart0_pclk alias not registered\n");

	clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, CLK_IS_ROOT,
					125000000);
	if (IS_ERR(clk))
		pr_err("uart1_pclk not registered\n");
	ret = clk_register_clkdev(clk, NULL, "20215000.uart");
	if (ret)
		pr_err("uart1_pclk alias not registered\n");
}

/*
 * ccu_osc_clk_init
 * ccu is in same PCI device with PMU. CCU address is at offset 0x800.
 * ccu's inialization is called from PMU init.
 */
int ccu_osc_clk_init(void __iomem *ccubase)
{
	struct clk *clk;
	int i, ret;
	char name[12];

	pr_debug("%s entry\n", __func__);

	clk = clk_register_fixed_rate(NULL, "clk-osc", NULL,
			CLK_IS_ROOT, OSC_CLOCK_RATE);
	if (IS_ERR(clk)) {
		pr_err("%s:clk register fail.\n", __func__);
		return -1;
	}
	clk_register_clkdev(clk, "clk-osc", NULL);

	for (i = 0; i < OSC_CLOCK_COUNT; i++) {
		memset(name, 0, sizeof(name));
		sprintf(name, "osc.%d", i);
		clk = ccu_osc_clk_register(name, "clk-osc", ccubase
				+ CCU_OSC_CTL_OFF + i * 4, i);
		if (!IS_ERR(clk))
			ret = clk_register_clkdev(clk, name, NULL);
	}

	return 0;
}

static void __init v2m_dt_timer_init(void)
{
	struct device_node *node = NULL;

	of_clk_init(NULL);

	do {
		node = of_find_compatible_node(node, NULL, "arm,sp804");
	} while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB);
	if (node) {
		pr_info("Using SP804 '%s' as a clock & events source\n",
				node->full_name);
		WARN_ON(clk_register_clkdev(of_clk_get_by_name(node,
				"timclken1"), "v2m-timer0", "sp804"));
		WARN_ON(clk_register_clkdev(of_clk_get_by_name(node,
				"timclken2"), "v2m-timer1", "sp804"));
		v2m_sp804_init(of_iomap(node, 0),
				irq_of_parse_and_map(node, 0));
	}

	if (arch_timer_of_register() != 0)
		twd_local_timer_of_register();

	if (arch_timer_sched_clock_init() != 0)
		versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
				24000000);
}

void __init vexpress_clk_of_init(void)
{
    struct device_node *node;
    struct clk *clk;
    struct clk *refclk, *timclk;

    of_clk_init(NULL);

    node = of_find_compatible_node(NULL, NULL, "arm,sp810");
    vexpress_sp810_init(of_iomap(node, 0));
    of_clk_add_provider(node, vexpress_sp810_of_get, NULL);

    /* Select "better" (faster) parent for SP804 timers */
    refclk = of_clk_get_by_name(node, "refclk");
    timclk = of_clk_get_by_name(node, "timclk");
    if (!WARN_ON(IS_ERR(refclk) || IS_ERR(timclk))) {
        int i = 0;

        if (clk_get_rate(refclk) > clk_get_rate(timclk))
            clk = refclk;
        else
            clk = timclk;

        for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++)
            WARN_ON(clk_set_parent(vexpress_sp810_timerclken[i],
                                   clk));
    }

    WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[0],
                                "v2m-timer0", "sp804"));
    WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[1],
                                "v2m-timer1", "sp804"));
}

void __init vexpress_clk_init(void __iomem *sp810_base)
{
    struct clk *clk;
    int i;

    clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
                                  CLK_IS_ROOT, 0);
    WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));

    clk = clk_register_fixed_rate(NULL, "v2m:clk_24mhz", NULL,
                                  CLK_IS_ROOT, 24000000);
    for (i = 0; i < ARRAY_SIZE(vexpress_clk_24mhz_periphs); i++)
        WARN_ON(clk_register_clkdev(clk, NULL,
                                    vexpress_clk_24mhz_periphs[i]));

    clk = clk_register_fixed_rate(NULL, "v2m:refclk32khz", NULL,
                                  CLK_IS_ROOT, 32768);
    WARN_ON(clk_register_clkdev(clk, NULL, "v2m:wdt"));

    clk = clk_register_fixed_rate(NULL, "v2m:refclk1mhz", NULL,
                                  CLK_IS_ROOT, 1000000);

    vexpress_sp810_init(sp810_base);

    for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++)
        WARN_ON(clk_set_parent(vexpress_sp810_timerclken[i], clk));

    WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[0],
                                "v2m-timer0", "sp804"));
    WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[1],
                                "v2m-timer1", "sp804"));
}

static void __init atlas6_clk_init(struct device_node *np)
{
	struct device_node *rscnp;
	int i;

	rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
	sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
	if (!sirfsoc_rsc_vbase)
		panic("unable to map rsc registers\n");
	of_node_put(rscnp);

	sirfsoc_clk_vbase = of_iomap(np, 0);
	if (!sirfsoc_clk_vbase)
		panic("unable to map clkc registers\n");

	/* These are always available (RTC and 26MHz OSC)*/
	atlas6_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL,
		CLK_IS_ROOT, 32768);
	atlas6_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL,
		CLK_IS_ROOT, 26000000);

	for (i = pll1; i < maxclk; i++) {
		atlas6_clks[i] = clk_register(NULL, atlas6_clk_hw_array[i]);
		BUG_ON(!atlas6_clks[i]);
	}
	clk_register_clkdev(atlas6_clks[cpu], NULL, "cpu");
	clk_register_clkdev(atlas6_clks[io],  NULL, "io");
	clk_register_clkdev(atlas6_clks[mem],  NULL, "mem");
	clk_register_clkdev(atlas6_clks[mem],  NULL, "osc");

	clk_data.clks = atlas6_clks;
	clk_data.clk_num = maxclk;

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}

static int bcm2835_clk_init(void)
{
	int ret;

	clks[dummy] = clk_fixed("dummy", 0);
	clks[clk_ref_3] = clk_fixed("ref3", 3 * 1000 * 1000);
	clks[clk_ref_1] = clk_fixed("ref1", 1 * 1000 * 1000);

	ret = clk_register_clkdev(clks[dummy], "apb_pclk", NULL);
	if (ret)
		goto clk_err;

	ret = clk_register_clkdev(clks[clk_ref_3], NULL, "uart0-pl0110");
	if (ret)
		goto clk_err;

	ret = clk_register_clkdev(clks[clk_ref_1], NULL, "bcm2835-cs");
	if (ret)
		goto clk_err;

	return 0;

clk_err:
	return ret;

}

void __init tegra_pmc_clk_init(void __iomem *pmc_base,
				struct tegra_clk *tegra_clks)
{
	struct clk *clk;
	struct clk **dt_clk;
	int i;

	for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {
		struct pmc_clk_init_data *data;

		data = pmc_clks + i;

		dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);
		if (!dt_clk)
			continue;

		clk = clk_register_mux(NULL, data->mux_name, data->parents,
				data->num_parents, CLK_SET_RATE_NO_REPARENT,
				pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
				3, 0, &clk_out_lock);
		*dt_clk = clk;


		dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);
		if (!dt_clk)
			continue;

		clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
					0, pmc_base + PMC_CLK_OUT_CNTRL,
					data->gate_shift, 0, &clk_out_lock);
		*dt_clk = clk;
		clk_register_clkdev(clk, data->dev_name, data->gate_name);
	}

	/* blink */
	writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
	clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
				pmc_base + PMC_DPD_PADS_ORIDE,
				PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);

	dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);
	if (!dt_clk)
		return;

	clk = clk_register_gate(NULL, "blink", "blink_override", 0,
				pmc_base + PMC_CTRL,
				PMC_CTRL_BLINK_ENB, 0, NULL);
	clk_register_clkdev(clk, "blink", NULL);
	*dt_clk = clk;
}

void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
{
	int i;

	for (i = 0; i < num; i++, dev_clks++)
		clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id,
				dev_clks->dev_id);

	for (i = 0; i < clk_num; i++) {
		if (!IS_ERR_OR_NULL(clks[i]))
			clk_register_clkdev(clks[i], __clk_get_name(clks[i]),
				"tegra-clk-debug");
	}
}

void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,
				  int nums, struct hisi_clock_data *data)
{
	struct clk *clk;
	void __iomem *base = data->base;
	int i;

	for (i = 0; i < nums; i++) {
		u32 mask = BIT(clks[i].width) - 1;

		clk = clk_register_mux_table(NULL, clks[i].name,
					clks[i].parent_names,
					clks[i].num_parents, clks[i].flags,
					base + clks[i].offset, clks[i].shift,
					mask, clks[i].mux_flags,
					clks[i].table, &hisi_clk_lock);
		if (IS_ERR(clk)) {
			pr_err("%s: failed to register clock %s\n",
			       __func__, clks[i].name);
			continue;
		}

		if (clks[i].alias)
			clk_register_clkdev(clk, clks[i].alias, NULL);

		data->clk_data.clks[clks[i].id] = clk;
	}
}

static void v2m_clk_init(void)
{
	struct clk *clk;
	int i;

	clk = clk_fixed("dummy_apb_pclk", 0);
	clk_register_clkdev(clk, "apb_pclk", NULL);

	clk = clk_fixed("mb:sp804_clk", 1000000);
	clk_register_clkdev(clk, NULL, "sp804");

	clk = clk_fixed("mb:osc2", 24000000);
	for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
		clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]);

}

void __init gem5_clk_of_register_energy_ctrl(void)
{
	char name[14] = "cpu-cluster.";
	struct device_node *node = NULL;
	struct clk *clk;
	const u32 *val;
	int cluster_id = 0, len;

	if (!of_find_compatible_node(NULL, NULL, "arm,gem5-energy-ctrl")) {
		pr_debug("%s: No EC found, Exiting!!\n", __func__);
		return;
	}

	while ((node = of_find_node_by_name(node, "cluster"))) {
		val = of_get_property(node, "reg", &len);
		if (val && len == 4)
			cluster_id = be32_to_cpup(val);

		name[12] = cluster_id + '0';
		clk = gem5_clk_register_energy_ctrl(name, cluster_id);
		if (IS_ERR(clk))
			return;

		pr_debug("Registered clock '%s'\n", name);
		clk_register_clkdev(clk, NULL, name);
	}
}

/**
 * of_fixed_clk_setup() - Setup function for simple fixed rate clock
 */
void of_fixed_clk_setup(struct device_node *node)
{
	struct clk *clk;
	const char *clk_name = node->name;
	u32 rate = 0;

	if (of_property_read_u32(node, "clock-frequency", &rate)) {
		pr_err("%s Fixed rate clock <%s> must have a clock rate property\n",
			__func__, node->name);
		return;
	}

	if (of_property_read_string(node, "clock-output-names", &clk_name)) {
		pr_err("%s Fixed rate clock <%s> must have a clock name property\n",
			__func__, node->name);
		return;
	}

	clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate);
	if (!IS_ERR(clk))
		of_clk_add_provider(node, of_clk_src_simple_get, clk);
#ifdef CONFIG_HI3630_CLK
	clk_register_clkdev(clk, clk_name, NULL);
#endif
}

int hisi_clk_register_gate(const struct hisi_gate_clock *clks,
				       int nums, struct hisi_clock_data *data)
{
	struct clk *clk;
	void __iomem *base = data->base;
	int i;

	for (i = 0; i < nums; i++) {
		clk = clk_register_gate(NULL, clks[i].name,
						clks[i].parent_name,
						clks[i].flags,
						base + clks[i].offset,
						clks[i].bit_idx,
						clks[i].gate_flags,
						&hisi_clk_lock);
		if (IS_ERR(clk)) {
			pr_err("%s: failed to register clock %s\n",
			       __func__, clks[i].name);
			goto err;
		}

		if (clks[i].alias)
			clk_register_clkdev(clk, clks[i].alias, NULL);

		data->clk_data.clks[clks[i].id] = clk;
	}

	return 0;

err:
	while (i--)
		clk_unregister_gate(data->clk_data.clks[clks[i].id]);

	return PTR_ERR(clk);
}

/* register a list of fixed clocks */
void __init amlogic_clk_register_fixed_rate(
		struct amlogic_fixed_rate_clock *list, unsigned int nr_clk)
{
	struct clk *clk;
	unsigned int idx, ret;

	for (idx = 0; idx < nr_clk; idx++, list++) {
		clk = clk_register_fixed_rate(NULL, list->name,
			list->parent_name, list->flags, list->fixed_rate);
		if (IS_ERR(clk)) {
			pr_err("%s: failed to register clock %s\n", __func__,
				list->name);
			continue;
		}

		amlogic_clk_add_lookup(clk, list->id);

		/*
		 * Unconditionally add a clock lookup for the fixed rate clocks.
		 * There are not many of these on any of Amlogic platforms.
		 */
		ret = clk_register_clkdev(clk, list->name, NULL);
		if (ret)
			pr_err("%s: failed to register clock lookup for %s",
				__func__, list->name);
	}
}