C++ bus_write_1函数代码示例

int
ichsmb_writeb(device_t dev, u_char slave, char cmd, char byte)
{
	const sc_p sc = device_get_softc(dev);
	int smb_error;

	DBG("slave=0x%02x cmd=0x%02x byte=0x%02x\n",
	    slave, (u_char)cmd, (u_char)byte);
	KASSERT(sc->ich_cmd == -1,
	    ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
	mtx_lock(&sc->mutex);
	sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE_DATA;
	bus_write_1(sc->io_res, ICH_XMIT_SLVA,
	    slave | ICH_XMIT_SLVA_WRITE);
	bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
	bus_write_1(sc->io_res, ICH_D0, byte);
	bus_write_1(sc->io_res, ICH_HST_CNT,
	    ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
	smb_error = ichsmb_wait(sc);
	mtx_unlock(&sc->mutex);
	DBG("smb_error=%d\n", smb_error);
	return (smb_error);
}

/* Counterpart of smbtx_smb_free(). */
static int
intsmb_free(struct intsmb_softc *sc)
{

	INTSMB_LOCK_ASSERT(sc);
	if ((bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) ||
#ifdef ENABLE_ALART
	    (bus_read_1(sc->io_res, PIIX4_SMBSLVSTS) & PIIX4_SMBSLVSTS_BUSY) ||
#endif
	    sc->isbusy)
		return (SMB_EBUSY);

	sc->isbusy = 1;
	/* Disable Interrupt in slave part. */
#ifndef ENABLE_ALART
	bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0);
#endif
	/* Reset INTR Flag to prepare INTR. */
	bus_write_1(sc->io_res, PIIX4_SMBHSTSTS,
	    PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
	    PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL);
	return (0);
}

void
macgpio_write(device_t dev, uint8_t val)
{
	struct macgpio_softc *sc;
	struct macgpio_devinfo *dinfo;

	sc = device_get_softc(device_get_parent(dev));
	dinfo = device_get_ivars(dev);

	if (dinfo->gpio_num < 0)
		return;

	bus_write_1(sc->sc_gpios,dinfo->gpio_num,val);
}

int
ichsmb_writew(device_t dev, u_char slave, char cmd, short word)
{
	const sc_p sc = device_get_softc(dev);
	int smb_error;

	DBG("slave=0x%02x cmd=0x%02x word=0x%04x\n",
	    slave, (u_char)cmd, (u_int16_t)word);
	KASSERT(sc->ich_cmd == -1,
	    ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
	mtx_lock(&sc->mutex);
	sc->ich_cmd = ICH_HST_CNT_SMB_CMD_WORD_DATA;
	bus_write_1(sc->io_res, ICH_XMIT_SLVA,
	    slave | ICH_XMIT_SLVA_WRITE);
	bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
	bus_write_1(sc->io_res, ICH_D0, word & 0xff);
	bus_write_1(sc->io_res, ICH_D1, word >> 8);
	bus_write_1(sc->io_res, ICH_HST_CNT,
	    ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
	smb_error = ichsmb_wait(sc);
	mtx_unlock(&sc->mutex);
	DBG("smb_error=%d\n", smb_error);
	return (smb_error);
}

/*
 * Wait for completion and return result.
 */
static int
intsmb_stop(struct intsmb_softc *sc)
{
	int error, status;

	INTSMB_LOCK_ASSERT(sc);

	if (sc->poll || cold)
		/* So that it can use device during device probe on SMBus. */
		return (intsmb_stop_poll(sc));

	error = msleep(sc, &sc->lock, PWAIT | PCATCH, "SMBWAI", hz / 8);
	if (error == 0) {
		status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
		if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
			error = intsmb_error(sc->dev, status);
			if (error == 0 && !(status & PIIX4_SMBHSTSTAT_INTR))
				device_printf(sc->dev, "unknown cause why?\n");
#ifdef ENABLE_ALART
			bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
			    PIIX4_SMBSLVCNT_ALTEN);
#endif
			return (error);
		}
	}

	/* Timeout Procedure. */
	sc->isbusy = 0;

	/* Re-enable suppressed interrupt from slave part. */
	bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
	if (error == EWOULDBLOCK)
		return (SMB_ETIMEOUT);
	else
		return (SMB_EABORT);
}

static void
le_lebuffer_copytodesc(struct lance_softc *sc, void *fromv, int off, int len)
{
	struct le_lebuffer_softc *lesc = (struct le_lebuffer_softc *)sc;
	caddr_t from = fromv;

	for (; len >= 8; len -= 8, off += 8, from += 8)
		bus_write_8(lesc->sc_bres, off, be64dec(from));
	for (; len >= 4; len -= 4, off += 4, from += 4)
		bus_write_4(lesc->sc_bres, off, be32dec(from));
	for (; len >= 2; len -= 2, off += 2, from += 2)
		bus_write_2(lesc->sc_bres, off, be16dec(from));
	if (len == 1)
		bus_write_1(lesc->sc_bres, off, *from);
}

static int
rb_nand_send_address(device_t dev, uint8_t addr)
{
	struct rb_nand_softc *sc;

	nand_debug(NDBG_DRV,"rb_nand: send address %x", addr);

	sc = device_get_softc(dev);
	GPIO_PIN_SET(sc->sc_gpio, sc->sc_cle_pin, 0);
	GPIO_PIN_SET(sc->sc_gpio, sc->sc_ale_pin, 1);
	GPIO_PIN_SET(sc->sc_gpio, sc->sc_nce_pin, 0);
	bus_write_1(sc->sc_mem, RB_NAND_DATA, addr);
	GPIO_PIN_SET(sc->sc_gpio, sc->sc_ale_pin, 0);
	return (0);
}

static void
intsmb_start(struct intsmb_softc *sc, unsigned char cmd, int nointr)
{
	unsigned char tmp;

	INTSMB_LOCK_ASSERT(sc);
	tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
	tmp &= 0xe0;
	tmp |= cmd;
	tmp |= PIIX4_SMBHSTCNT_START;

	/* While not in autoconfiguration enable interrupts. */
	if (!sc->poll && !cold && !nointr)
		tmp |= PIIX4_SMBHSTCNT_INTREN;
	bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp);
}

static int
intsmb_slvintr(struct intsmb_softc *sc)
{
	int status;

	status = bus_read_1(sc->io_res, PIIX4_SMBSLVSTS);
	if (status & PIIX4_SMBSLVSTS_BUSY)
		return (1);
	if (status & PIIX4_SMBSLVSTS_ALART)
		intsmb_alrintr(sc);
	else if (status & ~(PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2
		| PIIX4_SMBSLVSTS_SDW1)) {
	}

	/* Reset Status Register */
	bus_write_1(sc->io_res, PIIX4_SMBSLVSTS,
	    PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2 |
	    PIIX4_SMBSLVSTS_SDW1 | PIIX4_SMBSLVSTS_SLV);
	return (0);
}

static void
rb_nand_write_buf(device_t dev, void* buf, uint32_t len)
{
	struct rb_nand_softc *sc;
	int i;
	uint8_t *b = (uint8_t*)buf;

	sc = device_get_softc(dev);

	for (i = 0; i < len; i++) {
#ifdef NAND_DEBUG
		if (!(i % 16))
			printf("%s", i == 0 ? "rb_nand:\n" : "\n");
		printf(" %x", b[i]);
		if (i == len - 1)
			printf("\n");
#endif
		bus_write_1(sc->sc_mem, RB_NAND_DATA, b[i]);
	}
}

int
macio_enable_wireless(device_t dev, bool enable)
{
	struct macio_softc *sc = device_get_softc(dev);
	uint32_t x;

	if (enable) {
		x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2);
		x |= 0x4;
		bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x);

		/* Enable card slot. */
		bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0f, 5);
		DELAY(1000);
		bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0f, 4);
		DELAY(1000);
		x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2);
		x &= ~0x80000000;

		bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x);
		/* out8(gpio + 0x10, 4); */

		bus_write_1(sc->sc_memr, KEYLARGO_EXTINT_GPIO_REG_BASE + 0x0b, 0);
		bus_write_1(sc->sc_memr, KEYLARGO_EXTINT_GPIO_REG_BASE + 0x0a, 0x28);
		bus_write_1(sc->sc_memr, KEYLARGO_EXTINT_GPIO_REG_BASE + 0x0d, 0x28);
		bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0d, 0x28);
		bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0e, 0x28);
		bus_write_4(sc->sc_memr, 0x1c000, 0);

		/* Initialize the card. */
		bus_write_4(sc->sc_memr, 0x1a3e0, 0x41);
		x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2);
		x |= 0x80000000;
		bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x);
	} else {
		x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2);
		x &= ~0x4;
		bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x);
		/* out8(gpio + 0x10, 0); */
	}

	return (0);
}

static int
macgpio_deactivate_resource(device_t bus, device_t child, int type, int rid,
			  struct resource *res)
{
	struct macgpio_softc *sc;
	struct macgpio_devinfo *dinfo;
	u_char val;

	sc = device_get_softc(bus);
	dinfo = device_get_ivars(child);

	if (type != SYS_RES_IRQ)
		return ENXIO;

	if (dinfo->gpio_num >= 0) {
		val = bus_read_1(sc->sc_gpios,dinfo->gpio_num);
		val &= ~0x80;
		bus_write_1(sc->sc_gpios,dinfo->gpio_num,val);
	}

	return (bus_deactivate_resource(bus, type, rid, res));
}

/*
 * Handle attach-time duties that are independent of the bus
 * our device lives on.
 */
int
ichsmb_attach(device_t dev)
{
	const sc_p sc = device_get_softc(dev);
	int error;

	/* Create mutex */
	mtx_init(&sc->mutex, device_get_nameunit(dev), "ichsmb", MTX_DEF);

	/* Add child: an instance of the "smbus" device */
	if ((sc->smb = device_add_child(dev, DRIVER_SMBUS, -1)) == NULL) {
		device_printf(dev, "no \"%s\" child found\n", DRIVER_SMBUS);
		error = ENXIO;
		goto fail;
	}

	/* Clear interrupt conditions */
	bus_write_1(sc->io_res, ICH_HST_STA, 0xff);

	/* Set up interrupt handler */
	error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
	    NULL, ichsmb_device_intr, sc, &sc->irq_handle);
	if (error != 0) {
		device_printf(dev, "can't setup irq\n");
		goto fail;
	}

	/* Attach "smbus" child */
	if ((error = bus_generic_attach(dev)) != 0) {
		device_printf(dev, "failed to attach child: %d\n", error);
		goto fail;
	}

	return (0);

fail:
	mtx_destroy(&sc->mutex);
	return (error);
}

static int
intsmb_intr(struct intsmb_softc *sc)
{
	int status, tmp;

	status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
	if (status & PIIX4_SMBHSTSTAT_BUSY)
		return (1);

	if (status & (PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
	    PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL)) {

		tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
		bus_write_1(sc->io_res, PIIX4_SMBHSTCNT,
		    tmp & ~PIIX4_SMBHSTCNT_INTREN);
		if (sc->isbusy) {
			sc->isbusy = 0;
			wakeup(sc);
		}
		return (0);
	}
	return (1); /* Not Completed */
}

static int
s3c2xx0_rtc_attach(device_t dev)
{
	struct s3c2xx0_rtc_softc *sc;
	int error, rid;

	sc = device_get_softc(dev);
 	error = 0;

	rid = 0;
	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
	    RF_ACTIVE);
	if (sc->mem_res == NULL) {
		error = ENOMEM;
		goto out;
	}

	bus_write_1(sc->mem_res, RTC_RTCCON, RTCCON_RTCEN);
	clock_register(dev, 1000000);

out:
	return (error);
}