本文整理汇总了C++中bus_space_write_4函数的典型用法代码示例。如果您正苦于以下问题:C++ bus_space_write_4函数的具体用法?C++ bus_space_write_4怎么用?C++ bus_space_write_4使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了bus_space_write_4函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: omapmputmr_attach
void
omapmputmr_attach(device_t parent, device_t self, void *aux)
{
struct omapmputmr_softc *sc = device_private(self);
struct tipb_attach_args *tipb = aux;
int ints_per_sec;
sc->sc_iot = tipb->tipb_iot;
sc->sc_intr = tipb->tipb_intr;
if (bus_space_map(tipb->tipb_iot, tipb->tipb_addr, tipb->tipb_size, 0,
&sc->sc_ioh))
panic("%s: Cannot map registers", device_xname(self));
switch (device_unit(self)) {
case 0:
clock_sc = sc;
ints_per_sec = hz;
break;
case 1:
stat_sc = sc;
ints_per_sec = profhz = stathz = STATHZ;
break;
case 2:
ref_sc = sc;
ints_per_sec = hz; /* Same rate as clock */
break;
default:
ints_per_sec = hz; /* Better value? */
break;
}
aprint_normal(": OMAP MPU Timer\n");
aprint_naive("\n");
/* Stop the timer from counting, but keep the timer module working. */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, MPU_CNTL_TIMER,
MPU_CLOCK_ENABLE);
timer_factors tf;
calc_timer_factors(ints_per_sec, &tf);
switch (device_unit(self)) {
case 0:
counts_per_hz = tf.reload + 1;
counts_per_usec = tf.counts_per_usec;
break;
case 2:
/*
* The microtime reference clock for all practical purposes
* just wraps around as an unsigned int.
*/
tf.reload = 0xffffffff;
break;
default:
break;
}
/* Set the reload value. */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, MPU_LOAD_TIMER, tf.reload);
/* Set the PTV and the other required bits and pieces. */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, MPU_CNTL_TIMER,
( MPU_CLOCK_ENABLE
| (tf.ptv << MPU_PTV_SHIFT)
| MPU_AR
| MPU_ST));
/* The clock is now running, but is not generating interrupts. */
}
示例2: platform_mp_start_ap
void
platform_mp_start_ap(void)
{
bus_space_handle_t scu;
bus_space_handle_t src;
uint32_t val;
int i;
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
panic("Couldn't map the SCU\n");
if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0)
panic("Couldn't map the system reset controller (SRC)\n");
/*
* Invalidate SCU cache tags. The 0x0000ffff constant invalidates all
* ways on all cores 0-3. Per the ARM docs, it's harmless to write to
* the bits for cores that are not present.
*/
bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff);
/*
* Erratum ARM/MP: 764369 (problems with cache maintenance).
* Setting the "disable-migratory bit" in the undocumented SCU
* Diagnostic Control Register helps work around the problem.
*/
val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL,
val | SCU_DIAG_DISABLE_MIGBIT);
/*
* Enable the SCU, then clean the cache on this core. After these two
* operations the cache tag ram in the SCU is coherent with the contents
* of the cache on this core. The other cores aren't running yet so
* their caches can't contain valid data yet, but we've initialized
* their SCU tag ram above, so they will be coherent from startup.
*/
val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
val | SCU_CONTROL_ENABLE);
cpu_idcache_wbinv_all();
/*
* For each AP core, set the entry point address and argument registers,
* and set the core-enable and core-reset bits in the control register.
*/
val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG);
for (i=1; i < mp_ncpus; i++) {
bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i,
pmap_kextract((vm_offset_t)mpentry));
bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR1_C1ARG + 8*i, 0);
val |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + i )) |
( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + i)));
}
bus_space_write_4(fdtbus_bs_tag, src, 0, val);
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE);
}
示例3: WR4
static __inline void
WR4(struct ixpwdog_softc *sc, bus_size_t off, uint32_t val)
{
bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, off, val);
}
示例4: be_mcreset
void
be_mcreset(struct be_softc *sc)
{
struct ethercom *ec = &sc->sc_ethercom;
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t br = sc->sc_br;
uint32_t v;
uint32_t crc;
uint16_t hash[4];
struct ether_multi *enm;
struct ether_multistep step;
if (ifp->if_flags & IFF_PROMISC) {
v = bus_space_read_4(t, br, BE_BRI_RXCFG);
v |= BE_BR_RXCFG_PMISC;
bus_space_write_4(t, br, BE_BRI_RXCFG, v);
return;
}
if (ifp->if_flags & IFF_ALLMULTI) {
hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
goto chipit;
}
hash[3] = hash[2] = hash[1] = hash[0] = 0;
ETHER_FIRST_MULTI(step, ec, enm);
while (enm != NULL) {
if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
/*
* We must listen to a range of multicast
* addresses. For now, just accept all
* multicasts, rather than trying to set only
* those filter bits needed to match the range.
* (At this time, the only use of address
* ranges is for IP multicast routing, for
* which the range is big enough to require
* all bits set.)
*/
hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
ifp->if_flags |= IFF_ALLMULTI;
goto chipit;
}
crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
/* Just want the 6 most significant bits. */
crc >>= 26;
hash[crc >> 4] |= 1 << (crc & 0xf);
ETHER_NEXT_MULTI(step, enm);
}
ifp->if_flags &= ~IFF_ALLMULTI;
chipit:
/* Enable the hash filter */
bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]);
bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]);
bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]);
bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]);
v = bus_space_read_4(t, br, BE_BRI_RXCFG);
v &= ~BE_BR_RXCFG_PMISC;
v |= BE_BR_RXCFG_HENABLE;
bus_space_write_4(t, br, BE_BRI_RXCFG, v);
}
示例5: giopci_attach
static void
giopci_attach(struct device *parent, struct device *self, void *aux)
{
struct giopci_softc *sc = (void *)self;
pci_chipset_tag_t pc = &sc->sc_pc;
struct gio_attach_args *ga = aux;
uint32_t pci_off, pci_len, arb;
struct pcibus_attach_args pba;
u_long m_start, m_end;
#ifdef PCI_NETBSD_CONFIGURE
extern int pci_conf_debug;
pci_conf_debug = giopci_debug;
#endif
sc->sc_iot = ga->ga_iot;
sc->sc_slot = ga->ga_slot;
sc->sc_gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product);
if (mach_type == MACH_SGI_IP22 &&
mach_subtype == MACH_SGI_IP22_FULLHOUSE)
arb = GIO_ARB_RT | GIO_ARB_MST | GIO_ARB_PIPE;
else
arb = GIO_ARB_RT | GIO_ARB_MST;
if (gio_arb_config(ga->ga_slot, arb)) {
printf(": failed to configure GIO bus arbiter\n");
return;
}
#if (NIMC > 0)
imc_disable_sysad_parity();
#endif
switch (sc->sc_gprid) {
case PHOBOS_G100:
case PHOBOS_G130:
case PHOBOS_G160:
pci_off = PHOBOS_PCI_OFFSET;
pci_len = PHOBOS_PCI_LENGTH;
m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_START);
m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_END);
break;
case SETENG_GFE:
/*
* NB: The SetEng board does not allow the ThunderLAN's DMA
* engine to properly transfer segments that span page
* boundaries. See sgimips/autoconf.c where we catch a
* tl(4) device attachment and create an appropriate
* proplib entry to enable the workaround.
*/
pci_off = SETENG_PCI_OFFSET;
pci_len = SETENG_PCI_LENGTH;
m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_START);
m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_END);
bus_space_write_4(ga->ga_iot, ga->ga_ioh,
SETENG_MAGIC_OFFSET, SETENG_MAGIC_VALUE);
break;
default:
panic("giopci_attach: unsupported GIO product id 0x%02x",
sc->sc_gprid);
}
if (bus_space_subregion(ga->ga_iot, ga->ga_ioh, pci_off, pci_len,
&sc->sc_ioh)) {
printf("%s: unable to map PCI registers\n",sc->sc_dev.dv_xname);
return;
}
sc->sc_pci_len = pci_len;
pc->pc_bus_maxdevs = giopci_bus_maxdevs;
pc->pc_conf_read = giopci_conf_read;
pc->pc_conf_write = giopci_conf_write;
pc->pc_conf_hook = giopci_conf_hook;
pc->pc_intr_map = giopci_intr_map;
pc->pc_intr_string = giopci_intr_string;
pc->intr_establish = giopci_intr_establish;
pc->intr_disestablish = giopci_intr_disestablish;
pc->iot = ga->ga_iot;
pc->ioh = ga->ga_ioh;
pc->cookie = sc;
printf(": %s\n", gio_product_string(sc->sc_gprid));
#ifdef PCI_NETBSD_CONFIGURE
pc->pc_memext = extent_create("giopcimem", m_start, m_end,
M_DEVBUF, NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, NULL, pc->pc_memext, NULL, 0, mips_dcache_align);
#endif
memset(&pba, 0, sizeof(pba));
pba.pba_memt = SGIMIPS_BUS_SPACE_MEM;
pba.pba_dmat = ga->ga_dmat;
pba.pba_pc = pc;
pba.pba_flags = PCI_FLAGS_MEM_ENABLED;
/* NB: do not set PCI_FLAGS_{MRL,MRM,MWI}_OKAY -- true ?! */
config_found_ia(self, "pcibus", &pba, pcibusprint);
//.........这里部分代码省略.........
示例6: fimd_attach
static int
fimd_attach(device_t dev)
{
struct panel_info panel;
struct fimd_softc *sc;
device_t gpio_dev;
int reg;
sc = device_get_softc(dev);
sc->dev = dev;
if (bus_alloc_resources(dev, fimd_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
/* Memory interface */
sc->bst = rman_get_bustag(sc->res[0]);
sc->bsh = rman_get_bushandle(sc->res[0]);
sc->bst_disp = rman_get_bustag(sc->res[1]);
sc->bsh_disp = rman_get_bushandle(sc->res[1]);
sc->bst_sysreg = rman_get_bustag(sc->res[2]);
sc->bsh_sysreg = rman_get_bushandle(sc->res[2]);
if (get_panel_info(sc, &panel)) {
device_printf(dev, "Can't get panel info\n");
return (ENXIO);
}
panel.fixvclk = 0;
panel.ivclk = 0;
panel.clkval_f = 2;
sc->panel = &panel;
/* Get the GPIO device, we need this to give power to USB */
gpio_dev = devclass_get_device(devclass_find("gpio"), 0);
if (gpio_dev == NULL) {
/* TODO */
}
reg = bus_space_read_4(sc->bst_sysreg, sc->bsh_sysreg, 0x214);
reg |= FIMDBYPASS_DISP1;
bus_space_write_4(sc->bst_sysreg, sc->bsh_sysreg, 0x214, reg);
sc->sc_info.fb_width = panel.width;
sc->sc_info.fb_height = panel.height;
sc->sc_info.fb_stride = sc->sc_info.fb_width * 2;
sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 16;
sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride;
sc->sc_info.fb_vbase = (intptr_t)kmem_alloc_contig(kernel_arena,
sc->sc_info.fb_size, M_ZERO, 0, ~0, PAGE_SIZE, 0, VM_MEMATTR_UNCACHEABLE);
sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase);
#if 0
printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height,
sc->sc_info.fb_stride);
printf("pbase == 0x%08x\n", sc->sc_info.fb_pbase);
#endif
memset((int8_t *)sc->sc_info.fb_vbase, 0x0, sc->sc_info.fb_size);
fimd_init(sc);
sc->sc_info.fb_name = device_get_nameunit(dev);
/* Ask newbus to attach framebuffer device to me. */
sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev));
if (sc->sc_fbd == NULL)
device_printf(dev, "Can't attach fbd device\n");
if (device_probe_and_attach(sc->sc_fbd) != 0) {
device_printf(sc->dev, "Failed to attach fbd device\n");
}
return (0);
}
示例7: amptimer_intr
int
amptimer_intr(void *frame)
{
struct amptimer_softc *sc = amptimer_cd.cd_devs[0];
struct amptimer_pcpu_softc *pc = &sc->sc_pstat[CPU_INFO_UNIT(curcpu())];
uint64_t now;
uint64_t nextevent;
uint32_t r, reg;
#if defined(USE_GTIMER_CMP)
int skip = 1;
#else
int64_t delay;
#endif
int rc = 0;
/*
* DSR - I know that the tick timer is 64 bits, but the following
* code deals with rollover, so there is no point in dealing
* with the 64 bit math, just let the 32 bit rollover
* do the right thing
*/
now = amptimer_readcnt64(sc);
while (pc->pc_nexttickevent <= now) {
pc->pc_nexttickevent += sc->sc_ticks_per_intr;
pc->pc_ticks_err_sum += sc->sc_ticks_err_cnt;
/* looping a few times is faster than divide */
while (pc->pc_ticks_err_sum > hz) {
pc->pc_nexttickevent += 1;
pc->pc_ticks_err_sum -= hz;
}
#ifdef AMPTIMER_DEBUG
sc->sc_clk_count.ec_count++;
#endif
rc = 1;
hardclock(frame);
}
while (pc->pc_nextstatevent <= now) {
do {
r = random() & (sc->sc_statvar -1);
} while (r == 0); /* random == 0 not allowed */
pc->pc_nextstatevent += sc->sc_statmin + r;
/* XXX - correct nextstatevent? */
#ifdef AMPTIMER_DEBUG
sc->sc_stat_count.ec_count++;
#endif
rc = 1;
statclock(frame);
}
if (pc->pc_nexttickevent < pc->pc_nextstatevent)
nextevent = pc->pc_nexttickevent;
else
nextevent = pc->pc_nextstatevent;
#if defined(USE_GTIMER_CMP)
again:
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTIMER_CTRL);
reg &= ~GTIMER_CTRL_COMP;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIMER_CTRL, reg);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIMER_CMP_LOW,
nextevent & 0xffffffff);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIMER_CMP_HIGH,
nextevent >> 32);
reg |= GTIMER_CTRL_COMP;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIMER_CTRL, reg);
now = amptimer_readcnt64(sc);
if (now >= nextevent) {
nextevent = now + skip;
skip += 1;
goto again;
}
#else
/* clear old status */
bus_space_write_4(sc->sc_iot, sc->sc_pioh, PTIMER_STATUS,
PTIMER_STATUS_EVENT);
delay = nextevent - now;
if (delay < 0)
delay = 1;
reg = bus_space_read_4(sc->sc_iot, sc->sc_pioh, PTIMER_CTRL);
if ((reg & (PTIMER_CTRL_ENABLE | PTIMER_CTRL_IRQEN)) !=
(PTIMER_CTRL_ENABLE | PTIMER_CTRL_IRQEN))
bus_space_write_4(sc->sc_iot, sc->sc_pioh, PTIMER_CTRL,
(PTIMER_CTRL_ENABLE | PTIMER_CTRL_IRQEN));
bus_space_write_4(sc->sc_iot, sc->sc_pioh, PTIMER_LOAD, delay);
#endif
return (rc);
}
示例8: lbc_banks_enable
static int
lbc_banks_enable(struct lbc_softc *sc)
{
uint32_t size;
uint32_t regval;
int error, i;
for (i = 0; i < LBC_DEV_MAX; i++) {
size = sc->sc_banks[i].size;
if (size == 0)
continue;
/*
* Compute and program BR value.
*/
regval = sc->sc_banks[i].addr;
switch (sc->sc_banks[i].width) {
case 8:
regval |= (1 << 11);
break;
case 16:
regval |= (2 << 11);
break;
case 32:
regval |= (3 << 11);
break;
default:
error = EINVAL;
goto fail;
}
regval |= (sc->sc_banks[i].decc << 9);
regval |= (sc->sc_banks[i].wp << 8);
regval |= (sc->sc_banks[i].msel << 5);
regval |= (sc->sc_banks[i].atom << 2);
regval |= 1;
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
LBC85XX_BR(i), regval);
/*
* Compute and program OR value.
*/
regval = lbc_address_mask(size);
switch (sc->sc_banks[i].msel) {
case LBCRES_MSEL_GPCM:
/* TODO Add flag support for option registers */
regval |= 0x0ff7;
break;
case LBCRES_MSEL_FCM:
/* TODO Add flag support for options register */
regval |= 0x0796;
break;
case LBCRES_MSEL_UPMA:
case LBCRES_MSEL_UPMB:
case LBCRES_MSEL_UPMC:
printf("UPM mode not supported yet!");
error = ENOSYS;
goto fail;
}
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
LBC85XX_OR(i), regval);
}
return (0);
fail:
lbc_banks_unmap(sc);
return (error);
}
示例9: lbc_attach
static int
lbc_attach(device_t dev)
{
struct lbc_softc *sc;
struct lbc_devinfo *di;
struct rman *rm;
uintmax_t offset, size;
vm_paddr_t start;
device_t cdev;
phandle_t node, child;
pcell_t *ranges, *rangesptr;
int tuple_size, tuples;
int par_addr_cells;
int bank, error, i, j;
sc = device_get_softc(dev);
sc->sc_dev = dev;
sc->sc_mrid = 0;
sc->sc_mres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_mrid,
RF_ACTIVE);
if (sc->sc_mres == NULL)
return (ENXIO);
sc->sc_bst = rman_get_bustag(sc->sc_mres);
sc->sc_bsh = rman_get_bushandle(sc->sc_mres);
for (bank = 0; bank < LBC_DEV_MAX; bank++) {
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_BR(bank), 0);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_OR(bank), 0);
}
/*
* Initialize configuration register:
* - enable Local Bus
* - set data buffer control signal function
* - disable parity byte select
* - set ECC parity type
* - set bus monitor timing and timer prescale
*/
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LBCR, 0);
/*
* Initialize clock ratio register:
* - disable PLL bypass mode
* - configure LCLK delay cycles for the assertion of LALE
* - set system clock divider
*/
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LCRR, 0x00030008);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LTEDR, 0);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LTESR, ~0);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LTEIR, 0x64080001);
sc->sc_irid = 0;
sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
RF_ACTIVE | RF_SHAREABLE);
if (sc->sc_ires != NULL) {
error = bus_setup_intr(dev, sc->sc_ires,
INTR_TYPE_MISC | INTR_MPSAFE, NULL, lbc_intr, sc,
&sc->sc_icookie);
if (error) {
device_printf(dev, "could not activate interrupt\n");
bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
sc->sc_ires);
sc->sc_ires = NULL;
}
}
sc->sc_ltesr = ~0;
rangesptr = NULL;
rm = &sc->sc_rman;
rm->rm_type = RMAN_ARRAY;
rm->rm_descr = "Local Bus Space";
error = rman_init(rm);
if (error)
goto fail;
error = rman_manage_region(rm, rm->rm_start, rm->rm_end);
if (error) {
rman_fini(rm);
goto fail;
}
/*
* Process 'ranges' property.
*/
node = ofw_bus_get_node(dev);
if ((fdt_addrsize_cells(node, &sc->sc_addr_cells,
&sc->sc_size_cells)) != 0) {
error = ENXIO;
goto fail;
}
par_addr_cells = fdt_parent_addr_cells(node);
if (par_addr_cells > 2) {
device_printf(dev, "unsupported parent #addr-cells\n");
error = ERANGE;
//.........这里部分代码省略.........
示例10: igma_reg_write
static void
igma_reg_write(const struct igma_chip *cd, int r, u_int32_t v)
{
bus_space_write_4(cd->mmiot, cd->mmioh, r, v);
}
示例11: imxahci_attach
void
imxahci_attach(struct device *parent, struct device *self, void *args)
{
struct armv7_attach_args *aa = args;
struct imxahci_softc *imxsc = (struct imxahci_softc *) self;
struct ahci_softc *sc = &imxsc->sc;
uint32_t timeout = 0x100000;
sc->sc_iot = aa->aa_iot;
sc->sc_ios = aa->aa_dev->mem[0].size;
sc->sc_dmat = aa->aa_dmat;
if (bus_space_map(sc->sc_iot, aa->aa_dev->mem[0].addr,
aa->aa_dev->mem[0].size, 0, &sc->sc_ioh))
panic("imxahci_attach: bus_space_map failed!");
sc->sc_ih = arm_intr_establish(aa->aa_dev->irq[0], IPL_BIO,
ahci_intr, sc, sc->sc_dev.dv_xname);
if (sc->sc_ih == NULL) {
printf(": unable to establish interrupt\n");
goto unmap;
}
imxsc->sc_clk = clk_get("ahb");
if (imxsc->sc_clk == NULL) {
printf(": can't get clock\n");
goto unmap;
}
clk_enable(imxsc->sc_clk);
/* power it up */
clk_enable(clk_get("sata_ref_100m"));
clk_enable(clk_get("sata"));
delay(100);
/* power phy up */
imxiomuxc_enable_sata();
/* setup */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_P0PHYCR,
bus_space_read_4(sc->sc_iot, sc->sc_ioh, SATA_P0PHYCR) & ~SATA_P0PHYCR_TEST_PDDQ);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_GHC, SATA_GHC_HR);
while (!bus_space_read_4(sc->sc_iot, sc->sc_ioh, SATA_VERSIONR));
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_CAP,
bus_space_read_4(sc->sc_iot, sc->sc_ioh, SATA_CAP) | SATA_CAP_SSS);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_PI, 1);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SATA_TIMER1MS, clk_get_rate(imxsc->sc_clk));
while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SATA_P0SSTS) & 0xF) && timeout--);
if (ahci_attach(sc) != 0) {
/* error printed by ahci_attach */
goto irq;
}
return;
irq:
arm_intr_disestablish(sc->sc_ih);
unmap:
bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
}
示例12: ptx_detach
static int
ptx_detach (device_t device)
{
struct ptx_softc *scp = (struct ptx_softc *) device_get_softc(device);
uint32_t val;
int lp;
if (scp->cardtype == PT3) {
pt3_exit(scp);
if (scp->res_memory) {
bus_release_resource(device, SYS_RES_MEMORY,
scp->rid_memory, scp->res_memory);
scp->res_memory = 0;
}
if (scp->pt3_res_memory) {
bus_release_resource(device, SYS_RES_MEMORY,
scp->pt3_rid_memory, scp->pt3_res_memory);
scp->pt3_res_memory = 0;
}
if (scp->dmat) {
bus_dma_tag_destroy(scp->dmat);
}
if (scp->pt3_dmat) {
bus_dma_tag_destroy(scp->pt3_dmat);
}
return 0;
}
if (scp->ptxdaemon) {
ptx_proc_stop(scp);
}
// DMA終了
if (scp->bh) {
bus_space_write_4(scp->bt, scp->bh, 0x0, 0x08080000);
for (lp = 0; lp < 10; lp++){
val = bus_space_read_4(scp->bt, scp->bh, 0x0);
if (!(val & (1 << 6))) {
break;
}
ptx_pause("ptxdet", MSTOTICK(1));
}
}
ptx_dma_free(scp);
for (lp = 0; lp < MAX_STREAM; ++lp) {
struct ptx_stream *s = &scp->stream[lp];
if (mtx_initialized(&s->lock)) {
mtx_destroy(&s->lock);
cv_destroy(&s->not_full);
cv_destroy(&s->not_empty);
}
if (s->buf != NULL) {
free(s->buf, M_DEVBUF);
s->buf = NULL;
}
if (scp->dev[lp]) {
destroy_dev(scp->dev[lp]);
}
}
if (scp->bh) {
bus_space_write_4(scp->bt, scp->bh, 0x0, 0xb0b0000);
bus_space_write_4(scp->bt, scp->bh, CFG_REGS_ADDR, 0x0);
}
settuner_reset(scp, LNB_OFF, TUNER_POWER_OFF);
if (scp->dmat) {
bus_dma_tag_destroy(scp->dmat);
}
if (mtx_initialized(&scp->lock)) {
mtx_destroy(&scp->lock);
}
if (scp->res_memory) {
bus_release_resource(device, SYS_RES_MEMORY,
scp->rid_memory, scp->res_memory);
scp->res_memory = 0;
}
return 0;
}
示例13: npe_reg_write
static void
npe_reg_write(struct ixpnpe_softc *sc, bus_size_t off, uint32_t val)
{
DPRINTFn(9, sc->sc_dev, "%s(0x%lx, 0x%x)\n", __func__, off, val);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
}
示例14: malo_hal_write4
static __inline void
malo_hal_write4(struct malo_hal *mh, bus_size_t off, uint32_t val)
{
bus_space_write_4(mh->mh_iot, mh->mh_ioh, off, val);
}
示例15: iof_attach
void
iof_attach(struct device *parent, struct device *self, void *aux)
{
struct iof_softc *sc = (struct iof_softc *)self;
struct pci_attach_args *pa = aux;
pci_intr_handle_t ih;
bus_space_tag_t memt;
bus_space_handle_t memh;
bus_size_t memsize;
const char *intrstr;
printf(": ");
if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_MEM, 0,
&memt, &memh, NULL, &memsize, 0)) {
printf("can't map mem space\n");
return;
}
sc->sc_pc = pa->pa_pc;
sc->sc_tag = pa->pa_tag;
sc->sc_dmat = pa->pa_dmat;
/*
* Build a suitable bus_space_handle by restoring the original
* non-swapped subword access methods.
*
* XXX This is horrible and will need to be rethought if
* XXX IOC4 exist as real, removable PCI cards and
* XXX we ever support them cards not plugged to xbridges.
*/
sc->sc_mem_bus_space = malloc(sizeof (*sc->sc_mem_bus_space),
M_DEVBUF, M_NOWAIT);
if (sc->sc_mem_bus_space == NULL) {
printf("can't allocate bus_space\n");
goto unmap;
}
bcopy(memt, sc->sc_mem_bus_space, sizeof(*sc->sc_mem_bus_space));
sc->sc_mem_bus_space->_space_read_1 = xbow_read_1;
sc->sc_mem_bus_space->_space_read_2 = xbow_read_2;
sc->sc_mem_bus_space->_space_read_raw_2 = xbow_read_raw_2;
sc->sc_mem_bus_space->_space_write_1 = xbow_write_1;
sc->sc_mem_bus_space->_space_write_2 = xbow_write_2;
sc->sc_mem_bus_space->_space_write_raw_2 = xbow_write_raw_2;
sc->sc_memt = sc->sc_mem_bus_space;
sc->sc_memh = memh;
sc->sc_mcr = bus_space_read_4(sc->sc_memt, sc->sc_memh, IOC4_MCR);
/*
* Acknowledge all pending interrupts, and disable them.
*/
bus_space_write_4(sc->sc_memt, sc->sc_memh, IOC4_SIO_IEC, ~0x0);
bus_space_write_4(sc->sc_memt, sc->sc_memh, IOC4_SIO_IES, 0x0);
bus_space_write_4(sc->sc_memt, sc->sc_memh, IOC4_SIO_IR,
bus_space_read_4(sc->sc_memt, sc->sc_memh, IOC4_SIO_IR));
bus_space_write_4(sc->sc_memt, sc->sc_memh, IOC4_OTHER_IEC, ~0x0);
bus_space_write_4(sc->sc_memt, sc->sc_memh, IOC4_OTHER_IES, 0x0);
bus_space_write_4(sc->sc_memt, sc->sc_memh, IOC4_OTHER_IR,
bus_space_read_4(sc->sc_memt, sc->sc_memh, IOC4_OTHER_IR));
if (pci_intr_map(pa, &ih) != 0) {
printf("failed to map interrupt!\n");
goto unmap;
}
intrstr = pci_intr_string(sc->sc_pc, ih);
sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_TTY, iof_intr,
sc, self->dv_xname);
if (sc->sc_ih == NULL) {
printf("failed to establish interrupt at %s\n", intrstr);
goto unmap;
}
printf("%s\n", intrstr);
/*
* Attach other sub-devices.
*/
iof_attach_child(self, "com", IOC4_UARTA_BASE, IOC4DEV_SERIAL_A);
iof_attach_child(self, "com", IOC4_UARTB_BASE, IOC4DEV_SERIAL_B);
iof_attach_child(self, "com", IOC4_UARTC_BASE, IOC4DEV_SERIAL_C);
iof_attach_child(self, "com", IOC4_UARTD_BASE, IOC4DEV_SERIAL_D);
iof_attach_child(self, "iockbc", IOC4_KBC_BASE, IOC4DEV_KBC);
iof_attach_child(self, "dsrtc", IOC4_BYTEBUS_0, IOC4DEV_RTC);
return;
unmap:
bus_space_unmap(memt, memh, memsize);
}