C++ bus函数代码示例

/**
 * iwl_irq_handle_error - called for HW or SW error interrupt from card
 */
static void iwl_irq_handle_error(struct iwl_trans *trans)
{
	struct iwl_priv *priv = priv(trans);
	/* W/A for WiFi/WiMAX coex and WiMAX own the RF */
	if (priv->cfg->internal_wimax_coex &&
	    (!(iwl_read_prph(bus(trans), APMG_CLK_CTRL_REG) &
			APMS_CLK_VAL_MRB_FUNC_MODE) ||
	     (iwl_read_prph(bus(trans), APMG_PS_CTRL_REG) &
			APMG_PS_CTRL_VAL_RESET_REQ))) {
		/*
		 * Keep the restart process from trying to send host
		 * commands by clearing the ready bit.
		 */
		clear_bit(STATUS_READY, &trans->shrd->status);
		clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
		wake_up(&priv->shrd->wait_command_queue);
		IWL_ERR(trans, "RF is used by WiMAX\n");
		return;
	}

	IWL_ERR(trans, "Loaded firmware version: %s\n",
		priv->hw->wiphy->fw_version);

	iwl_dump_nic_error_log(trans);
	iwl_dump_csr(trans);
	iwl_dump_fh(trans, NULL, false);
	iwl_dump_nic_event_log(trans, false, NULL, false);
#ifdef CONFIG_IWLWIFI_DEBUG
	if (iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS)
		iwl_print_rx_config_cmd(priv(trans), IWL_RXON_CTX_BSS);
#endif

	iwlagn_fw_error(priv, false);
}

int i2c_write_bytes(i2c_t dev, uint16_t addr, const void *data, size_t len,
                    uint8_t flags)
{
    int ret;
    assert(dev < I2C_NUMOF);

    /* Check for unsupported operations */
    if (flags & I2C_ADDR10) {
        return -EOPNOTSUPP;
    }
    /* Check for wrong arguments given */
    if (data == NULL || len == 0) {
        return -EINVAL;
    }

    if (!(flags & I2C_NOSTART)) {
        ret = _start(bus(dev), (addr<<1));
        if (ret < 0) {
            DEBUG("Start command failed\n");
            return ret;
        }
    }
    ret = _write(bus(dev), data, len, (flags & I2C_NOSTOP) ? 0 : 1);
    if (ret < 0) {
        DEBUG("Write command failed\n");
        return ret;
    }

    return 0;
}

/* Device is going up inform it about using ICT interrupt table,
 * also we need to tell the driver to start using ICT interrupt.
 */
int iwl_reset_ict(struct iwl_trans *trans)
{
	u32 val;
	unsigned long flags;
	struct iwl_trans_pcie *trans_pcie =
		IWL_TRANS_GET_PCIE_TRANS(trans);

	if (!trans_pcie->ict_tbl_vir)
		return 0;

	spin_lock_irqsave(&trans->shrd->lock, flags);
	iwl_disable_interrupts(trans);

	memset(&trans_pcie->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);

	val = trans_pcie->aligned_ict_tbl_dma >> PAGE_SHIFT;

	val |= CSR_DRAM_INT_TBL_ENABLE;
	val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;

	IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%X "
			"aligned dma address %Lx\n",
			val,
			(unsigned long long)trans_pcie->aligned_ict_tbl_dma);

	iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
	trans_pcie->use_ict = true;
	trans_pcie->ict_index = 0;
	iwl_write32(bus(trans), CSR_INT, trans_pcie->inta_mask);
	iwl_enable_interrupts(trans);
	spin_unlock_irqrestore(&trans->shrd->lock, flags);

	return 0;
}

/**
 * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 */
void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
			struct iwl_rx_queue *q)
{
	unsigned long flags;
	u32 reg;

	spin_lock_irqsave(&q->lock, flags);

	if (q->need_update == 0)
		goto exit_unlock;

	if (hw_params(trans).shadow_reg_enable) {
		/* shadow register enabled */
		/* Device expects a multiple of 8 */
		q->write_actual = (q->write & ~0x7);
		iwl_write32(bus(trans), FH_RSCSR_CHNL0_WPTR, q->write_actual);
	} else {
		/* If power-saving is in use, make sure device is awake */
		if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
			reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);

			if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
				IWL_DEBUG_INFO(trans,
					"Rx queue requesting wakeup,"
					" GP1 = 0x%x\n", reg);
				iwl_set_bit(bus(trans), CSR_GP_CNTRL,
					CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
				goto exit_unlock;
			}

			q->write_actual = (q->write & ~0x7);
			iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
					q->write_actual);

		/* Else device is assumed to be awake */
		} else {
			/* Device expects a multiple of 8 */
			q->write_actual = (q->write & ~0x7);
			iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
				q->write_actual);
		}
	}
	q->need_update = 0;

 exit_unlock:
	spin_unlock_irqrestore(&q->lock, flags);
}

/* Device is going up inform it about using ICT interrupt table,
 * also we need to tell the driver to start using ICT interrupt.
 */
int iwl_reset_ict(struct iwl_trans *trans)
{
	u32 val;
	unsigned long flags;
	struct iwl_trans_pcie *trans_pcie =
		IWL_TRANS_GET_PCIE_TRANS(trans);

	if (!trans_pcie->ict_tbl)
		return 0;

	spin_lock_irqsave(&trans->shrd->lock, flags);
	iwl_disable_interrupts(trans);

	memset(trans_pcie->ict_tbl, 0, ICT_SIZE);

	val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;

	val |= CSR_DRAM_INT_TBL_ENABLE;
	val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;

	IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);

	iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
	trans_pcie->use_ict = true;
	trans_pcie->ict_index = 0;
	iwl_write32(bus(trans), CSR_INT, trans_pcie->inta_mask);
	iwl_enable_interrupts(trans);
	spin_unlock_irqrestore(&trans->shrd->lock, flags);

	return 0;
}

int i2c_read_bytes(i2c_t dev, uint16_t addr,
                   void *data, size_t len, uint8_t flags)
{
    int ret;
    assert(dev < I2C_NUMOF);

    /* Check for unsupported operations */
    if (flags & I2C_ADDR10) {
        return -EOPNOTSUPP;
    }
    /* Check for wrong arguments given */
    if (data == NULL || len == 0) {
        return -EINVAL;
    }

    if (!(flags & I2C_NOSTART)) {
        /* start transmission and send slave address */
        ret = _start(bus(dev), (addr << 1) | I2C_READ);
        if (ret < 0) {
            DEBUG("Start command failed\n");
            return ret;
        }
    }
    /* read data to register and issue stop if needed */
    ret = _read(bus(dev), data, len, (flags & I2C_NOSTOP) ? 0 : 1);
    if (ret < 0) {
        DEBUG("Read command failed\n");
        return ret;
    }
    /* Ensure all bytes has been read */
    while ((bus(dev)->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk)
           != BUSSTATE_IDLE) {}
    /* return number of bytes sent */
    return 0;
}

void _i2c_poweroff(i2c_t dev)
{
    assert(dev < I2C_NUMOF);

    if (bus(dev) == NULL) {
        return;
    }
    bus(dev)->CTRLA.bit.ENABLE = 0;
    while (bus(dev)->SYNCBUSY.bit.ENABLE) {}
}

/* NIC configuration for 1000 series */
static void iwl1000_nic_config(struct iwl_priv *priv)
{
	/* set CSR_HW_CONFIG_REG for uCode use */
	iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
		    CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
		    CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);

	/* Setting digital SVR for 1000 card to 1.32V */
	/* locking is acquired in iwl_set_bits_mask_prph() function */
	iwl_set_bits_mask_prph(bus(priv), APMG_DIGITAL_SVR_REG,
				APMG_SVR_DIGITAL_VOLTAGE_1_32,
				~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);
}

/*
 * allocate dram shared table, it is an aligned memory
 * block of ICT_SIZE.
 * also reset all data related to ICT table interrupt.
 */
int iwl_alloc_isr_ict(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie =
		IWL_TRANS_GET_PCIE_TRANS(trans);

	trans_pcie->ict_tbl =
		dma_alloc_coherent(bus(trans)->dev, ICT_SIZE,
				   &trans_pcie->ict_tbl_dma,
				   GFP_KERNEL);
	if (!trans_pcie->ict_tbl)
		return -ENOMEM;

	/* just an API sanity check ... it is guaranteed to be aligned */
	if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
		iwl_free_isr_ict(trans);
		return -EINVAL;
	}

	IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
		      (unsigned long long)trans_pcie->ict_tbl_dma);

	IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);

	/* reset table and index to all 0 */
	memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
	trans_pcie->ict_index = 0;

	/* add periodic RX interrupt */
	trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
	return 0;
}

// Bus-panning command method.
bool qtractorBusPanningCommand::redo (void)
{
	qtractorBus *pBus = bus();
	if (pBus == NULL)
		return false;

	// Set Bus panning (repective monitor gets set too...)
	const float fPanning = m_fPrevPanning;

	qtractorMeter *pMeter = meter();
	if (pMeter)
		pMeter->setPanning(m_fPanning);

	// MIDI buses are special...
	if (pBus->busType() == qtractorTrack::Midi) {
		// Now we gotta make sure of proper MIDI bus...
		qtractorMidiBus *pMidiBus
			= static_cast<qtractorMidiBus *> (pBus);
		if (pMidiBus)
			pMidiBus->setMasterPanning(m_fPanning);
	}

	// Set undo value...
	m_fPrevPanning = m_fPanning;
	m_fPanning     = fPanning;

	return true;
}

zx_status_t PlatformBus::Create(zx_device_t* parent, const char* name, zx::vmo zbi) {
    // This creates the "sys" device.
    sys_device_proto.version = DEVICE_OPS_VERSION;

    device_add_args_t args = {};
    args.version = DEVICE_ADD_ARGS_VERSION;
    args.name = "sys";
    args.ops = &sys_device_proto;
    args.flags = DEVICE_ADD_NON_BINDABLE;

    // Add child of sys for the board driver to bind to.
    auto status = device_add(parent, &args, &parent);
    if (status != ZX_OK) {
        return status;
    }

    fbl::AllocChecker ac;
    fbl::unique_ptr<platform_bus::PlatformBus> bus(new (&ac) platform_bus::PlatformBus(parent));
    if (!ac.check()) {
        return ZX_ERR_NO_MEMORY;
    }

    status = bus->Init(std::move(zbi));
    if (status != ZX_OK) {
        return status;
    }

    // devmgr is now in charge of the device.
    __UNUSED auto* dummy = bus.release();
    return ZX_OK;
}

FileReceiver::FileReceiver(QObject *parent)
    : QObject(parent)
{
    QDBusConnection bus(QDBusConnection::sessionBus());

    AccountFactoryPtr accountFactory = AccountFactory::create(bus);
    ConnectionFactoryPtr connectionFactory = ConnectionFactory::create(bus);
    ChannelFactoryPtr channelFactory = ChannelFactory::create(bus);
    channelFactory->addCommonFeatures(Channel::FeatureCore);
    channelFactory->addFeaturesForIncomingFileTransfers(IncomingFileTransferChannel::FeatureCore);

    mCR = ClientRegistrar::create(accountFactory, connectionFactory,
            channelFactory);

    qDebug() << "Registering incoming file transfer handler";
    mHandler = FileReceiverHandler::create();
    QString handlerName(QLatin1String("TpQtExampleFileReceiverHandler"));
    if (!mCR->registerClient(AbstractClientPtr::dynamicCast(mHandler), handlerName)) {
        qWarning() << "Unable to register incoming file transfer handler, aborting";
        QCoreApplication::exit(1);
        return;
    }

    qDebug() << "Awaiting file transfers";
}

void VCSlider::setSliderMode(SliderMode mode)
{
    Q_ASSERT(mode >= Bus && mode <= Submaster);

    /* Disconnect these to prevent double callbacks and non-needes signals */
    disconnect(Bus::instance(), SIGNAL(nameChanged(quint32, const QString&)),
               this, SLOT(slotBusNameChanged(quint32, const QString&)));
    disconnect(Bus::instance(), SIGNAL(valueChanged(quint32, quint32)),
               this, SLOT(slotBusValueChanged(quint32, quint32)));

    /* Unregister this as a DMX source if the new mode is not "Level" */
    if (m_sliderMode == Level && mode != Level)
        _app->masterTimer()->unregisterDMXSource(this);

    m_sliderMode = mode;

    if (mode == Bus)
    {
        /* Set the slider range */
        m_slider->setRange(busLowLimit() * MasterTimer::frequency(),
                           busHighLimit() * MasterTimer::frequency());
        setSliderValue(Bus::instance()->value(bus()));
        slotSliderMoved(sliderValue());

        /* Reconnect to bus emitter */
        connect(Bus::instance(), SIGNAL(nameChanged(quint32, const QString&)),
                this, SLOT(slotBusNameChanged(quint32, const QString&)));
        connect(Bus::instance(), SIGNAL(valueChanged(quint32, quint32)),
                this, SLOT(slotBusValueChanged(quint32, quint32)));

        m_bottomLabel->hide();
        m_tapButton->show();

        m_time->start();
    }

// Any time a connection or disconnection happens on any of our inputs, we potentially need to change the
// number of channels of our output.
void ChannelMergerNode::checkNumberOfChannelsForInput(ContextRenderLock& r, AudioNodeInput* input)
{
    // Count how many channels we have all together from all of the inputs.
    uint32_t numberOfOutputChannels = 0;
    
    for (uint32_t i = 0; i < numberOfInputs(); ++i)
    {
        auto input = this->input(i);
        
        if (input->isConnected())
        {
           numberOfOutputChannels += input->bus(r)->numberOfChannels();
        }
    }

    // Set the correct number of channels on the output
    auto output = this->output(0);
    output->setNumberOfChannels(r, numberOfOutputChannels);
    
    // Note * There can in rare cases be a slight delay before the output bus is updated to the new number of
    // channels because of tryLocks() in the context's updating system. So record the new number of
    // output channels here.
    m_desiredNumberOfOutputChannels = numberOfOutputChannels;

    AudioNode::checkNumberOfChannelsForInput(r, input);
}

MacWidget::~MacWidget()
{
    // No longer listen to synchronous messages.
    Gst::ScopedObject<GstBus> bus(gst_pipeline_get_bus(GST_PIPELINE(mPipeline)));
    gst_bus_disable_sync_message_emission(bus.get());
    g_signal_handlers_disconnect_by_func(bus.get(), (void*)G_CALLBACK(&MacWidget::OnSyncMessage), gpointer(this));
}