C++ USB_OTG_READ_REG32函数代码示例

/**
* @brief  DCD_HandleRxStatusQueueLevel_ISR
*         Handles the Rx Status Queue Level Interrupt
* @param  pdev: device instance
* @retval status
*/
static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev)
{
  USB_OTG_GINTMSK_TypeDef  int_mask;
  USB_OTG_DRXSTS_TypeDef   status;
  USB_OTG_EP *ep;
  
  /* Disable the Rx Status Queue Level interrupt */
  int_mask.d32 = 0;
  int_mask.b.rxstsqlvl = 1;
  USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0);
  
  /* Get the Status from the top of the FIFO */
  status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP );
  
  ep = &pdev->dev.out_ep[status.b.epnum];
  
  switch (status.b.pktsts)
  {
  case STS_GOUT_NAK:
    break;
  case STS_DATA_UPDT:
    if (status.b.bcnt)
    {
      USB_OTG_ReadPacket(pdev,ep->xfer_buff, status.b.bcnt);
      ep->xfer_buff += status.b.bcnt;
      ep->xfer_count += status.b.bcnt;
    }
    break;
  case STS_XFER_COMP:
    break;
  case STS_SETUP_COMP:
    break;
  case STS_SETUP_UPDT:
    /* Copy the setup packet received in FIFO into the setup buffer in RAM */
    USB_OTG_ReadPacket(pdev , pdev->dev.setup_packet, 8);
    ep->xfer_count += status.b.bcnt;
    break;
  default:
    break;
  }
  
  /* Enable the Rx Status Queue Level interrupt */
  USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32);
  
  return 1;
}

/**
* @brief  USBD_SetFeature
*         Handle Set device feature request
* @param  pdev: device instance
* @param  req: usb request
* @retval status
*/
static void USBD_SetFeature(USB_OTG_CORE_HANDLE  *pdev, 
                            USB_SETUP_REQ *req)
{

  USB_OTG_DCTL_TypeDef     dctl;
  uint8_t test_mode = 0;
 
  if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
  {
    pdev->dev.DevRemoteWakeup = 1;  
    pdev->dev.class_cb->Setup (pdev, req);   
    USBD_CtlSendStatus(pdev);
  }

  else if ((req->wValue == USB_FEATURE_TEST_MODE) && 
           ((req->wIndex & 0xFF) == 0))
  {
    dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL);
    
    test_mode = req->wIndex >> 8;
    switch (test_mode) 
    {
    case 1: // TEST_J
      dctl.b.tstctl = 1;
      break;
      
    case 2: // TEST_K	
      dctl.b.tstctl = 2;
      break;
      
    case 3: // TEST_SE0_NAK
      dctl.b.tstctl = 3;
      break;
      
    case 4: // TEST_PACKET
      dctl.b.tstctl = 4;
      break;
      
    case 5: // TEST_FORCE_ENABLE
      dctl.b.tstctl = 5;
      break;
    }
    SET_TEST_MODE = dctl;
    pdev->dev.test_mode = 1;
    USBD_CtlSendStatus(pdev);
  }

//--------------------------------------------------------------
USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
{
  USB_OTG_STS               status = USB_OTG_OK;
  USB_OTG_HCCHAR_TypeDef    hcchar;
  USB_OTG_HCTSIZn_TypeDef   hctsiz;  
  
  hctsiz.d32 = 0;
  hctsiz.b.dopng = 1;
  hctsiz.b.pktcnt = 1;
  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32);
  
  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
  hcchar.b.chen = 1;
  hcchar.b.chdis = 0;
  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
  return status;  
}

/*******************************************************************************
* Function Name  : OTGD_FS_ReadPacket
* Description    : Reads a packet from the Rx FIFO
* Input          : None
* Output         : None
* Return         : status
*******************************************************************************/
void* OTGD_FS_ReadPacket(uint8_t *dest, uint16_t bytes)
{
  uint32_t i = 0;
  uint32_t word_count = (bytes + 3) / 4;

  __IO uint32_t *fifo = USB_OTG_FS_regs.FIFO[0];
  uint32_t *data_buff = (uint32_t *)dest;

  for (i = 0; i < word_count; i++, data_buff++)
  {
    *data_buff = USB_OTG_READ_REG32(fifo);
  }

  /* Return the buffer pointer because if the transfer is composed of several packets,
     the data of the next packet must be stored following the previous packet's data         */
  return ((void *)data_buff);
}

/*******************************************************************************
* Function Name  : OTGD_FS_SetDeviceMode
* Description    : Set device mode
* Input          : None
* Output         : None
* Return         : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_SetDeviceMode(void)
{

  USB_OTG_Status status = USB_OTG_OK;
  USB_OTG_GUSBCFG_TypeDef usbcfg ;
  
  usbcfg.d32 = 0;

  usbcfg.d32 = USB_OTG_READ_REG32(&USB_OTG_FS_regs.GREGS->GUSBCFG);

  usbcfg.b.force_dev = 1;

  USB_OTG_WRITE_REG32(&USB_OTG_FS_regs.GREGS->GUSBCFG, usbcfg.d32);

  mDELAY(50);

  return status;
}

/*******************************************************************************
* Function Name  : OTGD_FS_EP0Activate
* Description    : enables EP0 OUT to receive SETUP packets and configures EP0
                   IN for transmitting packets
* Input          : None
* Output         : None
* Return         : status
*******************************************************************************/
USB_OTG_Status  OTGD_FS_EP0Activate(void)
{
  USB_OTG_Status          status = USB_OTG_OK;
  USB_OTG_DEPCTLx_TypeDef diepctl;
  USB_OTG_DCTL_TypeDef    dctl;

  diepctl.d32 = 0;
  dctl.d32 = 0;
  
  diepctl.d32 = USB_OTG_READ_REG32(&USB_OTG_FS_regs.DINEPS[0]->DIEPCTLx);
  diepctl.b.mps = DEP0CTL_MPS_64;
  USB_OTG_WRITE_REG32(&USB_OTG_FS_regs.DINEPS[0]->DIEPCTLx, diepctl.d32);

  dctl.b.cgnpinnak = 1;
  USB_OTG_MODIFY_REG32(&USB_OTG_FS_regs.DEV->DCTL, dctl.d32, dctl.d32);
  
  return status;
}

static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR(USB_OTG_CORE_HANDLE *pdev)
{

	USB_OTG_HPTXSTS_TypeDef hptxsts;
	uint32_t write_len;
	char *write_buff;

	hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);


	write_len = (pdev->host.hc[hptxsts.b.chnum].xfer_len + 3) / 4;

	if (hptxsts.b.ptxfspcavail <= write_len)
	{
		write_len = hptxsts.b.ptxfspcavail * 4;
		write_buff = (char*)pdev->host.hc[hptxsts.b.chnum].xfer_buff;
		pdev->host.hc[hptxsts.b.chnum].xfer_len -= write_len;
		pdev->host.hc[hptxsts.b.chnum].xfer_buff += write_len;
	}
	else
	{
		USB_OTG_GINTMSK_TypeDef intmsk;
		intmsk.d32 = 0;
		intmsk.b.ptxfempty = 1;
		USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);

		write_buff = (char*)pdev->host.hc[hptxsts.b.chnum].xfer_buff;
		write_len = pdev->host.hc[hptxsts.b.chnum].xfer_len;

		pdev->host.hc[hptxsts.b.chnum].xfer_len = 0;
		pdev->host.hc[hptxsts.b.chnum].xfer_buff += write_len;
	}


	USB_OTG_WritePacket(pdev, (uint8_t*)write_buff, hptxsts.b.chnum, write_len);

	if (pdev->host.hc[hptxsts.b.chnum].xfer_len < 0)
	{
		pdev->host.hc[hptxsts.b.chnum].xfer_len = 0;
	}

	return 1;
}

// Handles the incomplete Periodic transfer Interrupt
static void USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev)
{
  
  USB_OTG_GINTSTS_TypeDef       gintsts;
  USB_OTG_HCCHAR_TypeDef        hcchar; 
  
  
  
  
  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[0]->HCCHAR);
  hcchar.b.chen = 1;
  hcchar.b.chdis = 1;
  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[0]->HCCHAR, hcchar.d32);  
  
  gintsts.d32 = 0;
  /* Clear interrupt */
  gintsts.b.incomplisoout = 1;
  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
}

/*******************************************************************************
* Function Name  : OTGD_FS_GetEPStatus
* Description    : returns the EP Status 
* Input          : - ep: pointer to the EP structure
* Output         : None
* Return         : status: DEV_EP_TX_STALL, DEV_EP_TX_VALID, DEV_EP_TX_NAK, 
*                  DEV_EP_RX_STALL, DEV_EP_RX_VALID or DEV_EP_RX_NAK,
*******************************************************************************/
uint32_t OTGD_FS_GetEPStatus(USB_OTG_EP *ep)
{
  USB_OTG_DEPCTLx_TypeDef depctl;
  __IO uint32_t *depctl_addr;
  uint32_t Status = 0;
  
  depctl.d32 = 0;

  if (ep->is_in == 1)
  {
    depctl_addr = &(USB_OTG_FS_regs.DINEPS[ep->num]->DIEPCTLx);
  }
  else
  {
    depctl_addr = &(USB_OTG_FS_regs.DOUTEPS[ep->num]->DOEPCTLx);
  }

  depctl.d32 = USB_OTG_READ_REG32(depctl_addr);

  /* Process for IN endpoint */
  if (ep->is_in == 1)
  {
    if (depctl.b.stall == 1)  
      Status = DEV_EP_TX_STALL;
    else if (depctl.b.naksts == 1)
      Status = DEV_EP_TX_NAK;
    else 
      Status = DEV_EP_TX_VALID; 
  } 
  /* Process for OUT endpoint */
  else 
  {
    if (depctl.b.stall == 1)  
      Status = DEV_EP_RX_STALL;
    else if (depctl.b.naksts == 1)
      Status = DEV_EP_RX_NAK;
    else 
      Status = DEV_EP_RX_VALID; 
  }
  
  /* Return the current status */
  return Status;
}

static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR(USB_OTG_CORE_HANDLE*pdev)
{
	int free_space;
	USB_OTG_HNPTXSTS_TypeDef hnptxsts;
	uint32_t write_len;
	char *write_buff;

	hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
	hnptxsts.b.chnum = pdev->cur_bulk_out_ch;


	write_len = (pdev->host.hc[hnptxsts.b.chnum].xfer_len + 3) / 4;

	free_space = hnptxsts.b.nptxfspcavail - 16;

	if (free_space < write_len)
	{
		write_len = free_space * 4;
		write_buff = (char*)pdev->host.hc[hnptxsts.b.chnum].xfer_buff;
		pdev->host.hc[hnptxsts.b.chnum].xfer_len -= write_len;
		pdev->host.hc[hnptxsts.b.chnum].xfer_buff += write_len;
	}
	else
	{
		USB_OTG_GINTMSK_TypeDef intmsk;
		intmsk.d32 = 0;
		intmsk.b.nptxfempty = 1;
		USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);

		write_buff = (char*)pdev->host.hc[hnptxsts.b.chnum].xfer_buff;
		write_len = write_len * 4;
		pdev->host.hc[hnptxsts.b.chnum].xfer_len = 0;
		pdev->bulk_out_irq_pending = 0;
	}
	USB_OTG_WritePacket(pdev, (uint8_t*)write_buff, hnptxsts.b.chnum, write_len);

	if (pdev->host.hc[hnptxsts.b.chnum].xfer_len < 0)
	{
		pdev->host.hc[hnptxsts.b.chnum].xfer_len = 0;
	}

	return 1;
}

//--------------------------------------------------------------
USB_OTG_STS USB_OTG_FlushRxFifo(USB_OTG_CORE_HANDLE * pdev)
{
    USB_OTG_STS status = USB_OTG_OK;
    __IO USB_OTG_GRSTCTL_TypeDef greset;
    uint32_t count = 0;

    greset.d32 = 0;
    greset.b.rxfflsh = 1;
    USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRSTCTL, greset.d32);
    do {
        greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL);
        if (++count > 200000) {
            break;
        }
    }
    while (greset.b.rxfflsh == 1);
    /* Wait for 3 PHY Clocks */
    USB_OTG_BSP_uDelay(3);
    return status;
}

//--------------------------------------------------------------
USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE * pdev, uint8_t mode)
{
    USB_OTG_STS status = USB_OTG_OK;
    USB_OTG_GUSBCFG_TypeDef usbcfg;

    usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);

    usbcfg.b.force_host = 0;
    usbcfg.b.force_dev = 0;

    if (mode == HOST_MODE) {
        usbcfg.b.force_host = 1;
    } else if (mode == DEVICE_MODE) {
        usbcfg.b.force_dev = 1;
    }

    USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
    USB_OTG_BSP_mDelay(50);
    return status;
}

/*******************************************************************************
* Function Name  : OTGD_FS_EPActivate
* Description    : Activates an EP
* Input          : ep
* Output         : None
* Return         : num_in_ep
*******************************************************************************/
USB_OTG_Status OTGD_FS_EPActivate(USB_OTG_EP *ep)
{

  USB_OTG_Status status = USB_OTG_OK;
  USB_OTG_DEPCTLx_TypeDef depctl;
  USB_OTG_DAINT_TypeDef   daintmsk;
  __IO uint32_t *addr;


  depctl.d32 = 0;
  daintmsk.d32 = 0;
  
  /* Read DEPCTLn register */
  if (ep->is_in == 1)
  {
    addr = &USB_OTG_FS_regs.DINEPS[ep->num]->DIEPCTLx;
    daintmsk.ep.in = 1 << ep->num;
  }
  else
  {
    addr = &USB_OTG_FS_regs.DOUTEPS[ep->num]->DOEPCTLx;
    daintmsk.ep.out = 1 << ep->num;
  }

  /* If the EP is already active don't change the EP Control
   * register. */
  depctl.d32 = USB_OTG_READ_REG32(addr);
  if (!depctl.b.usbactep)
  {
    depctl.b.mps    = ep->maxpacket;
    depctl.b.eptype = ep->type;
    depctl.b.txfnum = ep->tx_fifo_num;
    depctl.b.setd0pid = 1;
    depctl.b.usbactep = 1;
    USB_OTG_WRITE_REG32(addr, depctl.d32);
  }

  /* Enable the Interrupt for this EP */
  USB_OTG_MODIFY_REG32(&USB_OTG_FS_regs.DEV->DAINTMSK, 0, daintmsk.d32);
  return status;
}

//--------------------------------------------------------------
void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE * pdev)
{
    USB_OTG_DEP0XFRSIZ_TypeDef doeptsize0;
    doeptsize0.d32 = 0;
    doeptsize0.b.supcnt = 3;
    doeptsize0.b.pktcnt = 1;
    doeptsize0.b.xfersize = 8 * 3;
    USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32);

    if (pdev->cfg.dma_enable == 1) {
        USB_OTG_DEPCTL_TypeDef doepctl;
        doepctl.d32 = 0;
        USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPDMA, (uint32_t) & pdev->dev.setup_packet);

        /* EP enable */
        doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL);
        doepctl.b.epena = 1;
        doepctl.d32 = 0x80008000;
        USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL, doepctl.d32);
    }
}

//--------------------------------------------------------------
USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE * pdev, USB_OTG_EP * ep)
{
    USB_OTG_STS status = USB_OTG_OK;
    USB_OTG_DEPCTL_TypeDef depctl;
    __IO uint32_t *depctl_addr;

    depctl.d32 = 0;

    if (ep->is_in == 1) {
        depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
    } else {
        depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
    }
    depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
    /* clear the stall bits */
    depctl.b.stall = 0;
    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) {
        depctl.b.setd0pid = 1;  /* DATA0 */
    }
    USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
    return status;
}