C++ UDATA函数代码示例

int
sf_proto_end(sf_instance_t *inst, sf_session_t *session)
{
    sf_protocb_t *pcb = PCB(session);

    if (pcb == NULL || pcb->pc_session_end == NULL)
        return 0;

    return pcb->pc_session_end(&session->se_sf, UDATA(session));
}

int
sf_proto_input(sf_instance_t *inst, sf_session_t *session, sf_pbuf_t *pbuf, int msglen)
{
    sf_protocb_t *pcb = PCB(session);

    if (pcb == NULL || pcb->pc_msg_input == NULL)
        return -1;

    return pcb->pc_msg_input(&session->se_sf, sf_pbuf_head(pbuf), msglen, UDATA(session));
}

int
sf_proto_msglen(sf_instance_t *inst, sf_session_t *session, sf_pbuf_t *pbuf)
{
    int len;
    sf_protocb_t *pcb = PCB(session);

    if ((len = sf_pbuf_data_len(pbuf)) <= 0)
        return -1;
    if ((pcb = PCB(session)) == NULL || pcb->pc_msg_length == NULL)
        return len;

    return pcb->pc_msg_length(&session->se_sf, sf_pbuf_head(pbuf), len, UDATA(session));
}

t_stat i8272_reset (DEVICE *dptr, uint16 base);
void i8272_reset1(uint8 devnum);
uint8 i8272_get_dn(void);
uint8 i8251s(t_bool io, uint8 data);
uint8 i8251d(t_bool io, uint8 data);

/* globals */

int32 i8272_devnum = 0;             //initially, no 8272 instances
uint16 i8272_port[4];               //base port assigned to each 8272 instance

/* i8272 Standard I/O Data Structures */
/* up to 4 i8282 devices */

UNIT i8272_unit[4] = { 
    { UDATA (&i8272_svc, 0, 0), KBD_POLL_WAIT },
    { UDATA (&i8272_svc, 0, 0), KBD_POLL_WAIT },
    { UDATA (&i8272_svc, 0, 0), KBD_POLL_WAIT },
    { UDATA (&i8272_svc, 0, 0), KBD_POLL_WAIT }
};

REG i8272_reg[4] = {
    { HRDATA (DATA, i8272_unit[0].buf, 8) },
    { HRDATA (STAT, i8272_unit[0].u3, 8) },
    { HRDATA (MODE, i8272_unit[0].u4, 8) },
    { HRDATA (CMD, i8272_unit[0].u5, 8) }
};

DEBTAB i8272_debug[] = {
    { "ALL", DEBUG_all },
    { "FLOW", DEBUG_flow },

uint32 I_delay (uint32 opc, uint32 ea, uint32 op);
uint32 shift_in (uint32 a, uint32 dat, uint32 sh4);

extern t_stat op_p (uint32 dev, uint32 ch);
extern t_stat op_i (uint32 dev, uint32 ch, uint32 sh4);
extern void lgp_vm_init (void);

/* CPU data structures

   cpu_dev      CPU device descriptor
   cpu_unit     CPU unit descriptor
   cpu_reg      CPU register list
   cpu_mod      CPU modifiers list
*/

UNIT cpu_unit = { UDATA (NULL, UNIT_FIX+UNIT_IN4B+UNIT_TTSS_D, MEMSIZE) };

REG cpu_reg[] = {
    { DRDATA (C, PC, 12), REG_VMAD },
    { HRDATA (A, A, 32), REG_VMIO },
    { HRDATA (IR, IR, 32), REG_VMIO },
    { FLDATA (OVF, OVF, 0) },
    { FLDATA (TSW, t_switch, 0) },
    { FLDATA (BP32, bp32, 0) },
    { FLDATA (BP16, bp16, 0) },
    { FLDATA (BP8, bp8, 0) },
    { FLDATA (BP4, bp4, 0) },
    { FLDATA (INPST, inp_strt, 0) },
    { FLDATA (INPDN, inp_done, 0) },
    { FLDATA (OUTST, out_strt, 0) },
    { FLDATA (OUTDN, out_done, 0) },

t_stat rp_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat rp_set_bad (UNIT *uptr, int32 val, char *cptr, void *desc);
int32 rp_abort (void);

/* RP data structures

   rp_dev       RP device descriptor
   rp_unit      RP unit list
   rp_reg       RP register list
   rp_mod       RP modifier list
*/

DIB rp_dib = { MBA_RP, 0, &rp_mbrd, &rp_mbwr, 0, 0, 0, { &rp_abort } };

UNIT rp_unit[] = {
    { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_AUTO+
             UNIT_ROABLE+(INIT_DTYPE << UNIT_V_DTYPE), INIT_SIZE) },
    { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_AUTO+
             UNIT_ROABLE+(INIT_DTYPE << UNIT_V_DTYPE), INIT_SIZE) },
    { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_AUTO+
             UNIT_ROABLE+(INIT_DTYPE << UNIT_V_DTYPE), INIT_SIZE) },
    { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_AUTO+
             UNIT_ROABLE+(INIT_DTYPE << UNIT_V_DTYPE), INIT_SIZE) },
    { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_AUTO+
             UNIT_ROABLE+(INIT_DTYPE << UNIT_V_DTYPE), INIT_SIZE) },
    { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_AUTO+
             UNIT_ROABLE+(INIT_DTYPE << UNIT_V_DTYPE), INIT_SIZE) },
    { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_AUTO+
             UNIT_ROABLE+(INIT_DTYPE << UNIT_V_DTYPE), INIT_SIZE) },
    { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_AUTO+
             UNIT_ROABLE+(INIT_DTYPE << UNIT_V_DTYPE), INIT_SIZE) }
    };

extern uint32 PCX;

extern int32 sio0d(const int32 port, const int32 io, const int32 data);
extern int32 sio0s(const int32 port, const int32 io, const int32 data);

static t_stat set_if3_connect(UNIT *uptr, int32 val, char *cptr, void *desc);

static t_stat if3_reset(DEVICE *if3_dev);
static t_stat if3_svc (UNIT *uptr);
static uint8 IF3_Read(const uint32 Addr);
static uint8 IF3_Write(const uint32 Addr, uint8 cData);
static int32 if3dev(const int32 port, const int32 io, const int32 data);
static t_stat update_rx_tx_isr (UNIT *uptr);

static UNIT if3_unit[] = {
    { UDATA (&if3_svc, UNIT_FIX | UNIT_DISABLE | UNIT_ROABLE | UNIT_IF3_CONNECT, 0) },
    { UDATA (&if3_svc, UNIT_FIX | UNIT_DISABLE | UNIT_ROABLE, 0) },
    { UDATA (&if3_svc, UNIT_FIX | UNIT_DISABLE | UNIT_ROABLE, 0) },
    { UDATA (&if3_svc, UNIT_FIX | UNIT_DISABLE | UNIT_ROABLE, 0) }
};

static uint8 if3_user = 0;
static uint8 if3_board = 0;
static uint8 if3_rimr[IF3_MAX_BOARDS] = { 0, 0, 0, 0 };
static uint8 if3_timr[IF3_MAX_BOARDS] = { 0, 0, 0, 0 };
static uint8 if3_risr[IF3_MAX_BOARDS] = { 0, 0, 0, 0 };
static uint8 if3_tisr[IF3_MAX_BOARDS] = { 0, 0, 0, 0 };

static REG if3_reg[] = {
    { HRDATA (USER,     if3_user,       3), },
    { HRDATA (BOARD,    if3_board,      2), },

int32 dco_iack(void);
void dcx_reset_ln(int32 ln);

/* DCI data structures

   dci_dev      DCI device descriptor
   dci_unit     DCI unit descriptor
   dci_reg      DCI register list
*/

DIB dci_dib = {
	IOBA_DC, IOLN_DC, &dcx_rd, &dcx_wr,
	2, IVCL(DCI), VEC_DCI, {&dci_iack, &dco_iack}
};

UNIT dci_unit = { UDATA(&dci_svc, 0, 0), KBD_POLL_WAIT };

REG dci_reg[] = {
	{BRDATA(BUF, dci_buf, DEV_RDX, 8, DCX_LINES)},
	{BRDATA(CSR, dci_csr, DEV_RDX, 16, DCX_LINES)},
	{GRDATA(IREQ, dci_ireq, DEV_RDX, DCX_LINES, 0)},
	{DRDATA(LINES, dcx_desc.lines, 6), REG_HRO},
	{GRDATA(DEVADDR, dci_dib.ba, DEV_RDX, 32, 0), REG_HRO},
	{GRDATA(DEVIOLN, dci_dib.lnt, DEV_RDX, 32, 0), REG_HRO},
	{GRDATA(DEVVEC, dci_dib.vec, DEV_RDX, 16, 0), REG_HRO},
	{NULL}
};

MTAB dci_mod[] = {
	{MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
	 &tmxr_dscln, NULL, &dcx_desc},

void mt_clr_rwi (uint32 un);

/* MT data structures

   mt_dev       MT device descriptor
   mt_unit      MT unit descriptors
   mt_reg       MT register list
   mt_mod       MT modifiers list
*/

dib_t mt_dib = { DVA_MT, mt_disp };

/* First 'n' units are tape drives; second 'n' are rewind threads */

UNIT mt_unit[] = {
    { UDATA (&mtu_svc, UNIT_ATTABLE+UNIT_ROABLE+UNIT_DISABLE, 0) },
    { UDATA (&mtu_svc, UNIT_ATTABLE+UNIT_ROABLE+UNIT_DISABLE, 0) },
    { UDATA (&mtu_svc, UNIT_ATTABLE+UNIT_ROABLE+UNIT_DISABLE, 0) },
    { UDATA (&mtu_svc, UNIT_ATTABLE+UNIT_ROABLE+UNIT_DISABLE, 0) },
    { UDATA (&mtu_svc, UNIT_ATTABLE+UNIT_ROABLE+UNIT_DISABLE, 0) },
    { UDATA (&mtu_svc, UNIT_ATTABLE+UNIT_ROABLE+UNIT_DISABLE, 0) },
    { UDATA (&mtu_svc, UNIT_ATTABLE+UNIT_ROABLE+UNIT_DISABLE, 0) },
    { UDATA (&mtu_svc, UNIT_ATTABLE+UNIT_ROABLE+UNIT_DISABLE, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) }

extern t_bool conv_old;

int32 inq_char = 033;                                   /* request inq */
t_stat inq_svc (UNIT *uptr);
t_stat inq_reset (DEVICE *dptr);

void inq_puts (char *cptr);

/* INQ data structures

   inq_dev      INQ device descriptor
   inq_unit     INQ unit descriptor
   inq_reg      INQ register list
*/

UNIT inq_unit = { UDATA (&inq_svc, 0, 0), KBD_POLL_WAIT };

REG inq_reg[] = {
    { ORDATA (INQC, inq_char, 7) },
    { FLDATA (INR, ind[IN_INR], 0) },
    { FLDATA (INC, ind[IN_INC], 0) },
    { DRDATA (TIME, inq_unit.wait, 24), REG_NZ + PV_LEFT },
    { NULL }
    };

MTAB inq_mod[] = {
    { UNIT_PCH, 0,        "business set", "BUSINESS" },
    { UNIT_PCH, UNIT_PCH, "Fortran set", "FORTRAN" },
    { 0 }
    };

#define HDC1001_CAPACITY          (77*2*16*256)   /* Default Micropolis Disk Capacity         */
#define IMAGE_TYPE_DSK          1               /* Flat binary "DSK" image file.            */
#define IMAGE_TYPE_IMD          2               /* ImageDisk "IMD" image file.              */
#define IMAGE_TYPE_CPT          3               /* CP/M Transfer "CPT" image file.          */

static t_stat hdc1001_reset(DEVICE *hdc1001_dev);
static t_stat hdc1001_attach(UNIT *uptr, char *cptr);
static t_stat hdc1001_detach(UNIT *uptr);

static int32 hdc1001dev(const int32 port, const int32 io, const int32 data);

static uint8 HDC1001_Read(const uint32 Addr);
static uint8 HDC1001_Write(const uint32 Addr, uint8 cData);

static UNIT hdc1001_unit[] = {
    { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, HDC1001_CAPACITY) },
    { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, HDC1001_CAPACITY) },
    { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, HDC1001_CAPACITY) },
    { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, HDC1001_CAPACITY) }
};

static REG hdc1001_reg[] = {
    { NULL }
};

static MTAB hdc1001_mod[] = {
    { MTAB_XTD|MTAB_VDV,    0,                  "IOBASE",   "IOBASE",   &set_iobase, &show_iobase, NULL },
    { UNIT_HDC1001_WLK,       0,                  "WRTENB",   "WRTENB",   NULL  },
    { UNIT_HDC1001_WLK,       UNIT_HDC1001_WLK,     "WRTLCK",   "WRTLCK",   NULL  },
    /* quiet, no warning messages       */
    { UNIT_HDC1001_VERBOSE,   0,                  "QUIET",    "QUIET",    NULL   },

extern uint8 isbc064_get_mbyte(uint16 addr);
extern void isbc064_put_mbyte(uint16 addr, uint8 val);
extern void set_cpuint(int32 int_num);
extern t_stat SBC_reset (DEVICE *dptr);
extern t_stat isbc064_reset (DEVICE *dptr);
extern t_stat isbc208_reset (DEVICE *dptr);

/* external globals */

extern uint8 xack;                          /* XACK signal */
extern int32 int_req;                       /* i8080 INT signal */

/* multibus Standard SIMH Device Data Structures */

UNIT multibus_unit = { 
    UDATA (&multibus_svc, 0, 0), 20 
};

REG multibus_reg[] = { 
    { HRDATA (MBIRQ, mbirq, 32) }, 
    { HRDATA (XACK, xack, 8) }
};

DEBTAB multibus_debug[] = {
    { "ALL", DEBUG_all },
    { "FLOW", DEBUG_flow },
    { "READ", DEBUG_read },
    { "WRITE", DEBUG_write },
    { "LEV1", DEBUG_level1 },
    { "LEV2", DEBUG_level2 },
    { NULL }

int32 tmxr_poll = 5000;

extern int32 stop_inst;

t_stat clk_svc (UNIT *uptr);
t_stat clk_reset (DEVICE *dptr);

/* CLK data structures

   clk_dev      CLK device descriptor
   clk_unit     CLK unit
   clk_reg      CLK register list
*/

UNIT clk_unit = {
    UDATA (&clk_svc, 0, 0), 5000
    };

REG clk_reg[] = {
    { ORDATA (CNTR, clk_cntr, 16) },
    { DRDATA (SBS32LVL, clk32ms_sbs, 4), REG_HRO },
    { DRDATA (SBS1MLVL, clk1min_sbs, 4), REG_HRO },
    { NULL }
    };

MTAB clk_mod[] = {
    { MTAB_XTD|MTAB_VDV, 0, "SBS32MSLVL", "SBS32MSLVL",
      &dev_set_sbs, &dev_show_sbs, (void *) &clk32ms_sbs },
    { MTAB_XTD|MTAB_VDV, 0, "SBS1MINLVL", "SBS1MINLVL",
      &dev_set_sbs, &dev_show_sbs, (void *) &clk1min_sbs },
    { 0 }

int32 icr_rd (t_bool interp);
void tmr_incr (uint32 inc);
void tmr_sched (void);
t_stat todr_resync (void);
t_stat fl_wr_txdb (int32 data);
t_bool fl_test_xfr (UNIT *uptr, t_bool wr);
void fl_protocol_error (void);

/* TTI data structures

   tti_dev      TTI device descriptor
   tti_unit     TTI unit descriptor
   tti_reg      TTI register list
*/

UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 };

REG tti_reg[] = {
    { HRDATA (RXDB, tti_buf, 16) },
    { HRDATA (RXCS, tti_csr, 16) },
    { FLDATA (INT, tti_int, 0) },
    { FLDATA (DONE, tti_csr, CSR_V_DONE) },
    { FLDATA (IE, tti_csr, CSR_V_IE) },
    { DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
    { DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
    { NULL }
    };

MTAB tti_mod[] = {
    { TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
    { TT_MODE, TT_MODE_8B, "8b", "8B", NULL },

char *sbia_description (DEVICE *dptr);
void sbi_set_tmo (int32 pa);
t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md);
t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md);

extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
extern int32 eval_int (void);

/* SBIA data structures

   sbia_dev     SBIA device descriptor
   sbia_unit    SBIA unit
   sbia_reg     SBIA register list
*/

UNIT sbia_unit = { UDATA (NULL, 0, 0) };

REG sbia_reg[] = {
    { HRDATA (NREQ14, nexus_req[0], 16) },
    { HRDATA (NREQ15, nexus_req[1], 16) },
    { HRDATA (NREQ16, nexus_req[2], 16) },
    { HRDATA (NREQ17, nexus_req[3], 16) },
    { HRDATA (SBIFS, sbi_fs, 32) },
    { HRDATA (SBISC, sbi_sc, 32) },
    { HRDATA (SBIMT, sbi_mt, 32) },
    { HRDATA (SBIER, sbi_er, 32) },
    { HRDATA (SBITMO, sbi_tmo, 32) },
    { HRDATA (SBICSR, sbi_csr, 32) },
    { NULL }
    };