C++ SystemCoreClockUpdate函数代码示例

//.........这里部分代码省略.........
    DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
    DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
    DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
    DMA_Init(DMA2_Stream0, &DMA_InitStructure);
    DMA_Cmd(DMA2_Stream0, ENABLE);



    /* TIM3_CH1(PB4-LED) configuration */
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_Init(GPIOB, &GPIO_InitStructure);

    GPIO_PinAFConfig(GPIOB, GPIO_PinSource4, GPIO_AF_TIM3);



    /* ADC Common Init */
    ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
    ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4;     // ADC clock = PCLK2/prescaler. ADC freq = typical 30MHz, Max 36MHz. PCLK2 = 168/2=84MHz.
    ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
    ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
    ADC_CommonInit(&ADC_CommonInitStructure);


    /* ADC channel 10 (PC0) configuration */
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
    GPIO_Init(GPIOC, &GPIO_InitStructure);


    /* ADC channel configuration */
    ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;
    ADC_InitStructure.ADC_ScanConvMode = DISABLE;
    ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
    ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_Rising;
    ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T3_TRGO;  // TIM3의 트리거 발생시 ADC 수행
    ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
    ADC_InitStructure.ADC_NbrOfConversion = 1;
    ADC_Init(ADC1, &ADC_InitStructure);


    /* ADC1 regular channel10 configuration */
    ADC_RegularChannelConfig(ADC1, ADC_Channel_10, 1, ADC_SampleTime_3Cycles);


    /* Enable ADC1 DMA */
    ADC_DMACmd(ADC1, ENABLE);

    /* Enable ADC1 */
    ADC_Cmd(ADC1, ENABLE);

    /* Enable DMA request after last transfer (Single-ADC mode) */
    ADC_DMARequestAfterLastTransferCmd(ADC1, ENABLE);





    /* Compute the prescaler value */
    SystemCoreClockUpdate();
    PrescalerValue = (uint16_t) (SystemCoreClock / 2 / TIMER_PRESCALER_FREQ) - 1;           // timer base counter에 1MHz 입력

    /* Time base configuration */
    TIM_TimeBaseStructure.TIM_Period = PWM_WIDTH - 1;
    TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
    TIM_TimeBaseStructure.TIM_ClockDivision = 0;
    TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;

    TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);

    // TIM3 update 이벤트에서 트리거 발생하도록 설정 -> ADC trigger로 사용
    TIM_SelectOutputTrigger(TIM3, TIM_TRGOSource_Update);


    TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
    TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
    TIM_OCInitStructure.TIM_Pulse = DUTY_IDLE;          // default 50%
    TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
    TIM_OC1Init(TIM3, &TIM_OCInitStructure);
    TIM_OC1PreloadConfig(TIM3, TIM_OCPreload_Disable);


    /* TIM3 enable counter */
    TIM_Cmd(TIM3, ENABLE);





    while(1)
    {
        __WFI();
    }

}

/**
* application main entry point
*/
int main(void) {

	int n=0;
	int button = 0;
	int oldButton = 0;
	int targetBlocking = 0;	//!< debounce SysTicker target time
	volatile	int exercisePart=3;
	int timestart=0;
	int timestop=0;
  volatile	int time=0;
	
SystemCoreClockUpdate();
SysTick_Config(SystemCoreClock/1000);			/* Generate interrupt each 1 ms	*/

		RCC_GetClocksFreq(&clocks);	

	
RCC_Configuration();
GPIO_Configuration();
	
printf("Debug printf starting with GPIO\n\n");	
	
while(1) {
	button = GPIOC->IDR & (1 << 13); 
	switch (exercisePart)
	{
		case 0:
			if (!oldButton && button && (ticks > targetBlocking))	{	
				n++;
				targetBlocking = ticks + 500;
				GPIOA->ODR ^= (1 << 5);	//! toggle bit #5 which is the LED
				printf("pressed %d\n",n);	
			}
			oldButton = button;
		break;
	
		case 1:
			timestart = ticks;
			printf("12345678901234567890\n");	
			timestop = ticks;
			time=timestop-timestart; // Debuger shows less than 1 ms
		break;

		case 2:
			timestart = ticks;
			printf("Global Time: %u",msTic);	
			timestop = ticks;
			time=timestop-timestart; // Debuger shows approx 1ms
		break;
		
		case 3:		
			if (!oldButton && button )	{	
					time=ticks-timestop;
				timestop=ticks;
				}
				oldButton = button;
			break;

		default:
		__NOP;
			
			
}

}	

}

/**
  * @brief  requests System clock frequency
  *
  * @note   This function should be used only after reset.
  * @param  None
  * @retval None
  */
uint32_t SysCtlClockGet(void)
{
    SystemCoreClockUpdate();
    return SystemCoreClock;
}

/**
  * @brief  Main program.
  * @param  None
  * @retval None
  */
int main(void)
{
	int i = 0, j = 0;
	int addr;

	//usb atjungimo kintamasis
	bool usbDisabled = true;

	//adc variables
	float *result;
	char mockResult[600];
	char UARTTxPacket[100];
	static short ultrasoundPacketTxMultiplier = 0;
    static int ULTRASOUND_PACKET_COUNT = 100;

	//usart state machine switch
	uartSwitch = 'r';

	//USB buffer variables
    uint8_t buf[255],outstrg[100],inchar;
    uint8_t len;

    //dac variables
    uint16_t waveform[32];
    uint8_t continueReading = 1;
    uint8_t intCount = 0;
    uint8_t charCount = 0;
    bool bufferReadSuccessful = false;
	char tempString[4];

    int cs;
    volatile float a,b,elapsedtime,angle,radius,angleinc;

    RCC_ClocksTypeDef RCC_Clocks;

	// Initialize System and Setup clocks.
	SystemInit();
	SystemCoreClockUpdate();

	//ini ADC
	adcConfigure();

	//init USART
	USARTInit();

	USART_puts(USART2, "P_Cmd\n\n");
	//USARTSendByte();
	//USARTReadByte();

	/* SysTick end of count event each 40ms */
	RCC_GetClocksFreq(&RCC_Clocks);
	//SysTick_Config(RCC_Clocks.HCLK_Frequency /100);

	// Initialize FPU
	*((volatile unsigned long*)0xE000ED88) = 0xF << 20;

	// Initialize LEDs and User_Button on STM32F4-Discovery
    STM_EVAL_LEDInit(LED4);
    STM_EVAL_LEDInit(LED3);
    STM_EVAL_LEDInit(LED5);
    STM_EVAL_LEDInit(LED6);

    if(!usbDisabled){
		// USB Device Initialize
		USBD_Init(&USB_OTG_dev,
				USB_OTG_FS_CORE_ID,
				&USR_desc,
				&USBD_CDC_cb,
				&USR_cb);

		// Wait for USB connection goes live
		while (!gbUsbDeviceReady);

		// Clean USB RX buffer
		while(VCP_get_string(&buf[0]) == 0);

		// Output signon
		printf("USB serial DEMO\r\n");
		printf("test\n\r>");
    }
    //  Main loop
    while(1) {
    	//SPI (WITH MSP) STATE MACHINE
    	if(uartSwitchGet() != 'r')
    		switch(uartSwitchGet()){
    		case 't': //cmd tx packet
    			for (i=0;i<600;i++)
    				mockResult[i] = i;
    			for(i=0;i<100;i++)
    				UARTTxPacket[i] = mockResult[i+ultrasoundPacketTxMultiplier];
    			txDataArrayToMsp(UARTTxPacket);
    			uartSwitchSet('r');
    			break;
    		case 'e':
    			//Delay(1000);
//.........这里部分代码省略.........

/**
  * @brief  This function get CPU frequency. The frequency unit is Hz.
  * @return CPU frequency
  */
uint32_t CLK_GetCPUFreq(void)
{
    SystemCoreClockUpdate();
    return SystemCoreClock;
}

void SystemInit (void)
{
    SystemCoreClockUpdate();
}

void sysclk_init(void)
{
    /* Set flash wait state to max in case the below clock switching. */
    system_init_flash(CHIP_FREQ_CPU_MAX);

    /* Config system clock setting */
    if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) {
        osc_enable(OSC_SLCK_32K_RC);
        osc_wait_ready(OSC_SLCK_32K_RC);
        pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
    }

    else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) {
        osc_enable(OSC_SLCK_32K_XTAL);
        osc_wait_ready(OSC_SLCK_32K_XTAL);
        pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
    }

    else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) {
        osc_enable(OSC_SLCK_32K_BYPASS);
        osc_wait_ready(OSC_SLCK_32K_BYPASS);
        pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
    }

    else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) {
        /* Already running from SYSCLK_SRC_MAINCK_4M_RC */
    }

    else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) {
        osc_enable(OSC_MAINCK_8M_RC);
        osc_wait_ready(OSC_MAINCK_8M_RC);
        pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
    }

    else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) {
        osc_enable(OSC_MAINCK_12M_RC);
        osc_wait_ready(OSC_MAINCK_12M_RC);
        pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
    }

    else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) {
        osc_enable(OSC_MAINCK_XTAL);
        osc_wait_ready(OSC_MAINCK_XTAL);
        pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
    }

    else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) {
        osc_enable(OSC_MAINCK_BYPASS);
        osc_wait_ready(OSC_MAINCK_BYPASS);
        pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
    }

#ifdef CONFIG_PLL0_SOURCE
    else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) {
        struct pll_config pllcfg;

        pll_enable_source(CONFIG_PLL0_SOURCE);
        pll_config_defaults(&pllcfg, 0);
        pll_enable(&pllcfg, 0);
        pll_wait_for_lock(0);
        pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES);
    }
#endif

#ifdef CONFIG_PLL1_SOURCE
    else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLBCK) {
        struct pll_config pllcfg;

        pll_enable_source(CONFIG_PLL1_SOURCE);
        pll_config_defaults(&pllcfg, 1);
        pll_enable(&pllcfg, 1);
        pll_wait_for_lock(1);
        pmc_switch_mck_to_pllbck(CONFIG_SYSCLK_PRES);
    }
#endif

    /* Update the SystemFrequency variable */
    SystemCoreClockUpdate();

    /* Set a flash wait state depending on the new cpu frequency */
    system_init_flash(sysclk_get_cpu_hz());

#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
    /* Signal that the internal frequencies are setup */
    sysclk_initialized = 1;
#endif

#ifdef CONFIG_CPCLK_ENABLE
    /* Enable coprocessor clock */
    sysclk_configure_cpclk();
#endif
}

// Initialize the system tick 
void InitSystick(void){
	SystemCoreClockUpdate();                      
	if (SysTick_Config(SystemCoreClock / 1000)) { 
		while (1);                             
	}
}

/**
 * @brief	Main UART/DMA program body
 * @return	Does not exit
 */
int main(void)
{
	int bytes = 0, idx;
	uint8_t buff[UARTRXBUFFSIZE];

	SystemCoreClockUpdate();
	Board_Init();
	Init_UART_PinMux();
	Board_LED_Set(0, false);

#if defined(USE_INTEGER_CLOCK)
	/* Use main clock rate as base for UART baud rate divider */
	Chip_Clock_SetUARTBaseClockRate(Chip_Clock_GetMainClockRate(), false);

#else
	/* Use 128x expected UART baud rate for fractional baud mode. */
	Chip_Clock_SetUARTBaseClockRate((115200 * 128), true);
#endif
	/* Setup UART */
	Chip_UART_Init(LPC_USART0);
	Chip_UART_ConfigData(LPC_USART0, UART_CFG_DATALEN_8 | UART_CFG_PARITY_NONE | UART_CFG_STOPLEN_1);
	Chip_UART_SetBaud(LPC_USART0, 115200);
	/* Optional for low clock rates only: Chip_UART_SetBaudWithRTC32K(LPC_USART, 300); */
	Chip_UART_Enable(LPC_USART0);
	Chip_UART_TXEnable(LPC_USART0);

	/* DMA initialization - enable DMA clocking and reset DMA if needed */
	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_DMA);
	Chip_SYSCTL_PeriphReset(RESET_DMA);
	/* Initialize ROM API pointer */
	pDMAApi = LPC_DMAD_API;
	size_in_bytes = pDMAApi->dma_get_mem_size();
	if (size_in_bytes > RAMBLOCK) {
		/* Adjust RAMBLOCK size in this case */
		return 1;
	}
	/* Setup DMA ROM driver, provided RAM blocks for DMA Handle */
	dma_handle = pDMAApi->dma_setup(LPC_DMA_BASE, dma_ram_block);

	/* Init UART 0 TX descriptor */
	countTXDescUsed = 0;

	/* Enable the DMA IRQ */
	NVIC_EnableIRQ(DMA_IRQn);

	/* Enqueue a bunch of strings in DMA transmit descriptors and start
	   transmit. In this use of DMA, the descriptors aren't chained, so
	     the DMA restarts the next queued descriptor in the DMA interrupt
	     handler. */
	for (idx = 0; idx < DMASENDSTRCNT; idx++) {
		sprintf(dmaSendStr[idx], "DMA send string (unlinked) #%d\r\n", idx);
		dmaTXSend((uint8_t *) dmaSendStr[idx], strlen(dmaSendStr[idx]));
	}

	/* Wait for UART TX DMA channel to go inactive */
	while (1) {
		__WFI();
		if (countTXDescUsed == 0) {
			break;
		}
	}

	/* Receive buffers are queued. The DMA interrupt will only trigger on a
	   full DMA buffer receive, so if the UART is idle, but the DMA is only
	   partially complete, the DMA interrupt won't fire. For UART data
	   receive where data is not continuous, a timeout method will be
	   required to flush the DMA when the DMA has pending data and no
	   data has been received on the UART in a specified timeout */
	dmaRXQueue();

	/* Get RX data via DMA and send it out on TX via DMA */
	while (1) {
		/* Sleep until something happens */
		__WFI();

		/* Did any data come in? */
		bytes = checkRxData(buff);
		if (bytes > 0) {
			/* RX data received, send it via TX DMA */
			dmaTXSend(buff, bytes);
		}
	}

	return 1;
}

int main()
{

    initialize_stk();
    
    /* Chip errata */
    CHIP_Init();
    /* Ensure core frequency has been updated */
    SystemCoreClockUpdate();
    
    IO_Init();
    
    UART1->ROUTE = UART_ROUTE_LOCATION_LOC3
    | UART_ROUTE_TXPEN | UART_ROUTE_RXPEN;
    
    static const uint32_t baud = 9600;
    static const uint32_t ovs = 16;
    static const uint32_t refclk = 14060000;
    
    UART1->CLKDIV = (256 * refclk) / ((ovs * baud) - 1);
    UART1->CMD = UART_CMD_TXEN | UART_CMD_RXEN;
    UART1->IEN = UART_IEN_RXDATAV;

    
    //TIMER_IntClear(TIMER0, TIMER_IF_OF);
    //InitRGBLEDPWM();
    //TIMER_IntClear(TIMER0, TIMER_IF_OF);
  
    clockAppDisplay();
    float time0 = atoi(&displayStringBuf);
    for (;;){
        
        
        clockAppDisplay();
        float time1 = atoi(&displayStringBuf);

        if(time1-time0>=1){
             printf("%.3f",time1);
             printf(" ");
             printf("%.4f",5556.5404+(distance*SPEEDLAT));
             printf(" ");
             printf("%0010.4f",311.4366+(distance*SPEEDLONG));
             printf("\n");
            if((distancef < DIS1 && fw) || STRAIGHT){
                distanceb=0;
                distance+=FINC;
                distancef+=FINC;
            }
            else{
                fw =0;
                distancef=0;
                distance-=BINC;
                distanceb+=BINC;
                if (distanceb >= DIS2){
                    fw = 1;
                }
            }
             time0 = time1;
        }
        
          
    }
    
}

/**
 * @brief	main routine for ADC example
 * @return	Function should not exit
 */
int main(void)
{
	SystemCoreClockUpdate();
	Board_Init();
	DEBUGSTR("ADC ROM sequencer demo\r\n");

	/* Power up, enable clock and reset ADC0 */
	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_ADC0_PD);
	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ADC0);
	Chip_SYSCTL_PeriphReset(RESET_ADC0);
	/* Power up, enable clock and reset ADC1 */
	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_ADC1_PD);
	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ADC1);
	Chip_SYSCTL_PeriphReset(RESET_ADC1);
	/* Power up the internal temperature sensor */
	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_TS_PD);

#if defined(BOARD_NXP_LPCXPRESSO_1549)
	/* Disables pullups/pulldowns and disable digital mode */
	Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 9, (IOCON_MODE_INACT | IOCON_ADMODE_EN));

	/* Assign ADC1_1 to PIO0_9 via SWM (fixed pin) */
	Chip_SWM_EnableFixedPin(SWM_FIXED_ADC1_1);

#else
#warning "No ADC setup for this example"
#endif
	/* Initialize ROM API base address for ADC */
	pAdcApi = LPC_ADCD_API;
	size_in_bytes = pAdcApi->adc_get_mem_size();
	if (size_in_bytes / 4 > RAMBLOCK_H) {
		/* Adjust RAMBLOCK size in this case */
		return 1;
	}
	/* ADC Handle Setup*/
	adc_handle[0] = pAdcApi->adc_setup(LPC_ADC0_BASE, (uint8_t *) start_of_ram_block[0]);
	adc_handle[1] = pAdcApi->adc_setup(LPC_ADC1_BASE, (uint8_t *) start_of_ram_block[1]);
	/* ADC0 Config */
	adc_cfg[0].system_clock = SystemCoreClock;	/* System clock */
	adc_cfg[0].adc_clock = 500000;	/* ADC clock set to 500KHz for calibration*/
	/* ADC1 Config */
	adc_cfg[1].system_clock = SystemCoreClock;	/* System clock */
	adc_cfg[1].adc_clock = 500000;	/* ADC clock set to 500KHz for calibration*/
	pAdcApi->adc_calibration(adc_handle[0], &adc_cfg[0]);
	pAdcApi->adc_calibration(adc_handle[1], &adc_cfg[1]);

	/* ADC0 Config for Init */
	adc_cfg[0].system_clock = SystemCoreClock;	/* System clock */
	adc_cfg[0].adc_clock = ADC_CLOCK_RATE;	/* ADC clock */
	adc_cfg[0].async_mode = 0;	/* Synchronous mode */
	adc_cfg[0].tenbit_mode = 0;	/* 12 Bit ADC mode */
	adc_cfg[0].lpwr_mode = 0;	/* Disable low power mode */
	adc_cfg[0].input_sel = ADC_INSEL_TS;
	adc_cfg[0].seqa_ctrl = (ADC_SEQ_CTRL_CHANSEL(0) | ADC_SEQ_CTRL_MODE_EOS);
	adc_cfg[0].channel_num = 1;	/* Channel number is one higher than the maximum channel number used */
	/* ADC1 Config for Init */
	adc_cfg[1].system_clock = SystemCoreClock;	/* System clock */
	adc_cfg[1].adc_clock = ADC_CLOCK_RATE;	/* ADC clock */
	adc_cfg[1].async_mode = 0;	/* Synchronous mode */
	adc_cfg[1].tenbit_mode = 0;	/* 12 Bit ADC mode */
	adc_cfg[1].lpwr_mode = 0;	/* Disable low power mode */
	adc_cfg[1].seqa_ctrl = (ADC_SEQ_CTRL_CHANSEL(BOARD_ADC_CH) | ADC_SEQ_CTRL_MODE_EOS);
	adc_cfg[1].thrsel = 0;
	adc_cfg[1].thr0_low = ((1 * 0xFFF) / 4) << 4;
	adc_cfg[1].thr0_high = ((3 * 0xFFF) / 4) << 4;
	adc_cfg[1].thcmp_en = ADC_INTEN_CMP_ENABLE(ADC_INTEN_CMP_CROSSTH, BOARD_ADC_CH);
	adc_cfg[1].channel_num = BOARD_ADC_CH + 1;	/* Channel number is one higher than the maximum channel number used */
	pAdcApi->adc_init(adc_handle[0], &adc_cfg[0]);
	pAdcApi->adc_init(adc_handle[1], &adc_cfg[1]);
	
	/* When using ADC ROM API's lower the priority of ADC Sequence completion interrupt when compared to the threshold interrupt*/
	NVIC_SetPriority(ADC1_SEQA_IRQn, 1);
	/* Enable related ADC NVIC interrupts */
	NVIC_EnableIRQ(ADC0_SEQA_IRQn);
	NVIC_EnableIRQ(ADC1_SEQA_IRQn);
	NVIC_EnableIRQ(ADC1_THCMP);

	/* This example uses the periodic sysTick to manually trigger the ADC,
	   but a periodic timer can be used in a match configuration to start
	   an ADC sequence without software intervention. */
	SysTick_Config(Chip_Clock_GetSysTickClockRate() / TICKRATE_HZ);

	/* Endless loop */
	while (1) {
		/* Sleep until something happens */
		__WFI();

		if (threshold1Crossed) {
			threshold1Crossed = false;
			DEBUGSTR("********ADC1 threshold event********\r\n");
		}

		/* Is a conversion sequence complete? */
		if (sequence0Complete) {
			sequence0Complete = false;
			showValudeADC(LPC_ADC0);
//.........这里部分代码省略.........

/**
 * @brief	Main entry point
 * @return	Nothing
 */
int main(void) {
	SystemCoreClockUpdate();
	Board_Init();
	setupClock();
	SystemCoreClockUpdate();

	On = true;
	enableOut = false;
	controlFlag = false;

	Board_LED_Set(0, On);
	DEBUGOUT("Starting\n");
	/* Initialize RITimer */
	Chip_RIT_Init(LPC_RITIMER);

	LPC_IOCON->PINSEL[4] |= 0x00000555; //Change this after you know which pwm outputs are needed.
	LPC_IOCON->PINMODE[3] |= (3 << 6);
	LPC_IOCON->PINMODE[3] |= (3 << 12);

	LPC_IOCON->PINSEL[1] |= (1 << 14);
	LPC_IOCON->PINSEL[1] |= (1 << 16);
	LPC_IOCON->PINSEL[1] |= (1 << 18);
	LPC_IOCON->PINSEL[1] |= (1 << 20);
	LPC_IOCON->PINMODE[1] |= (2 << 14);
	LPC_IOCON->PINMODE[1] |= (2 << 16);
	LPC_IOCON->PINMODE[1] |= (2 << 18);
	LPC_IOCON->PINMODE[1] |= (2 << 20);

	LPC_SYSCTL->PCLKSEL[0] |= (1 << 12); //PCLK_PWM1 = CCLK
	LPC_IOCON->PINMODE[4] |= (3 << 26);
	LPC_SYSCTL->PCONP |= (1 << 17); //Enable clock
	LPC_SYSCTL->PCLKSEL[1] |= (1 << 30); //PCLKMPWM = CCLK
	LPC_SYSCTL->PCLKSEL[0] |= (1 << 24);

	Chip_PWM_Init(LPC_PWM1);
	LPC_PWM1->PR = 0;
	Chip_PWM_SetMatch(LPC_PWM1, 0, 3000);
	Chip_PWM_SetMatch(LPC_PWM1, 1, 1500);
	Chip_PWM_SetMatch(LPC_PWM1, 2, 1500);
	Chip_PWM_SetMatch(LPC_PWM1, 3, 1500);

	Chip_PWM_ResetOnMatchEnable(LPC_PWM1, 0);
	Chip_PWM_SetCountClockSrc(LPC_PWM1, PWM_CAPSRC_RISING_PCLK, 0);
	Chip_PWM_SetControlMode(LPC_PWM1, 0, PWM_SINGLE_EDGE_CONTROL_MODE, PWM_OUT_ENABLED);
	Chip_PWM_SetControlMode(LPC_PWM1, 1, PWM_SINGLE_EDGE_CONTROL_MODE, PWM_OUT_ENABLED);
	Chip_PWM_SetControlMode(LPC_PWM1, 2, PWM_SINGLE_EDGE_CONTROL_MODE, PWM_OUT_ENABLED);

	Chip_PWM_LatchEnable(LPC_PWM1, 0, PWM_OUT_ENABLED);
	Chip_PWM_LatchEnable(LPC_PWM1, 1, PWM_OUT_ENABLED);
	Chip_PWM_LatchEnable(LPC_PWM1, 2, PWM_OUT_ENABLED);
	Chip_PWM_LatchEnable(LPC_PWM1, 3, PWM_OUT_ENABLED);

	Chip_PWM_Enable(LPC_PWM1);
	Chip_PWM_Reset(LPC_PWM1);

	Chip_GPIO_Init(LPC_GPIO);

	LPC_MCPWM->CON_SET |= (1 <<3);
	DCACSetFreq(1074);
	LPC_MCPWM->DT = 12;
	LPC_MCPWM->INTEN_SET |= 1;
	LPC_MCPWM->INTF_SET |= 1;
	LPC_MCPWM->CON_SET |= 1;
	freq = 1074;
	NVIC_EnableIRQ(RITIMER_IRQn);

	Chip_ADC_Init(LPC_ADC, &ADCSetup);
	Chip_ADC_SetBurstCmd(LPC_ADC, DISABLE);

	/* Configure RIT for a 1s interrupt tick rate */
	Chip_RIT_SetTimerInterval(LPC_RITIMER, TIME_INTERVAL);


	/* LED is toggled in interrupt handler */
	vout = 0;
	voutOldest = 0;
	voutOld = 0;
	while (1) {
		if(controlFlag) {
			bool emergency = !Chip_GPIO_GetPinState(LPC_GPIO,2,13);
			emergency |= !Chip_GPIO_GetPinState(LPC_GPIO,2,13);
			emergency |= !Chip_GPIO_GetPinState(LPC_GPIO,2,13);
			emergency |= !Chip_GPIO_GetPinState(LPC_GPIO,2,13);
			emergency |= !Chip_GPIO_GetPinState(LPC_GPIO,2,13);
			emergency |= !Chip_GPIO_GetPinState(LPC_GPIO,2,13);
			emergency = !emergency;
			if(emergency) {
				enableOut = false;
				vout = 0;
			} else {
			#ifdef enableLoad
				enableOut = Chip_GPIO_GetPinState(LPC_GPIO,0,28);
			#else
				enableOut = true;
			#endif
			}
//.........这里部分代码省略.........

// This function is called after RAM initialization and before main.
void mbed_sdk_init() {
    // Update the SystemCoreClock variable.
    SystemCoreClockUpdate();
}

//.........这里部分代码省略.........
   } while ((MCGSC & MCGSC_OSCINIT_MASK) == 0);
#endif

   // Wait for S_IREFST to indicate FLL Reference has switched
   do {
      __asm__("nop");
   } while ((MCGSC & MCGSC_IREFST_MASK) != (MCGC1_IREFS_V?MCGSC_IREFST_MASK:0));

   // Wait for S_CLKST to indicating that OUTCLK has switched to bypass PLL/FLL
   do {
      __asm__("nop");
   } while ((MCGSC & MCGSC_CLKST_MASK) != (BYPASS<<MCGSC_CLKST_BITNUM));

   // Set FLL Parameters
   MCGC4 = (MCGC4&~(MCGC4_DMX32_MASK|MCGC4_DRST_DRS_MASK))|MCGC4_DMX32_M|MCGC4_DRS_M;
#endif

#if ((CLOCK_MODE == CLOCK_MODE_PBE) || (CLOCK_MODE == CLOCK_MODE_PEE))

   // Transition via PBE
   // =============================================================
   MCGC3 = MCGC3_LOLIE_M    |
            MCGC3_PLLS_M    |  // PLLS  = 0,1 -> Enable PLL
            MCGC3_CME_M     |  // CME0  = 0,1 -> Disable/enable clock monitor
            MCGC3_VDIV_M;      // VDIV0 = N   -> PLL Multiplication factor

   // Wait for PLL to lock
   do {
      __asm__("nop");
   } while((MCGSC & MCGSC_LOCK_MASK) == 0);

   // Wait until PLLS clock source changes to the PLL clock out
   do {
      __asm__("nop");
   } while((MCGSC & MCGSC_PLLST_MASK) == 0);

#endif

#if ((CLOCK_MODE == CLOCK_MODE_FEI) || (CLOCK_MODE == CLOCK_MODE_FEE))
   // Wait for FLL to lock
   do {
      __asm__("nop");
   } while ((MCGC4&MCGC4_DRST_DRS_MASK) != MCGC4_DRS_M);
#endif


   // Select FEI/FBI/FEE/FBE/PBE/PEE clock mode
   MCGC1 =  MCGC1_CLKS_M        | // CLKS     = 0,1,2 -> Select FLL/IRCSCLK/ERCLK
            MCGC1_RDIV_M       | // RDIV    = N     -> XTAL/2^n ~ 31.25 kHz
            MCGC1_IREFS_M      | // IREFS    = 0,1   -> External/Slow IRC for FLL source
            MCGC1_IRCLKEN_M    | // IRCLKEN  = 0,1   -> IRCLK disable/enable
            MCGC1_IREFSTEN_M;    // IREFSTEN = 0,1   -> Internal reference enabled in STOP mode

   // Wait for mode change
   do {
      __asm__("nop");
   } while ((MCGSC & MCGSC_IREFST_MASK) != (MCGC1_IREFS_V?MCGSC_IREFST_MASK:0));

#if defined (MCGC3_PLLS_V) && (MCGC1_CLKS_V == 0) // FLL or PLL
#define MCGSC_CLKST_M ((MCGC3_PLLS_V?3:0)<<MCGSC_CLKST_BITNUM)
#else
   #define MCGSC_CLKST_M (MCGC1_CLKS_V<<MCGSC_CLKST_BITNUM)
#endif

   // Wait for S_CLKST to indicating that OUTCLK has switched
   do {
      __asm__("nop");
   } while ((MCGSC & MCGSC_CLKST_MASK) != MCGSC_CLKST_M);

#if (CLOCK_MODE == CLOCK_MODE_BLPE) || (CLOCK_MODE == CLOCK_MODE_BLPI)
   // Select BLPE/BLPI clock mode
   MCGC2 =
            MCGC2_LOCRE_M      | // LOCRE0 = 0,1   -> Loss of clock reset
            MCGC2_RANGE_M      | // RANGE0 = 0,1,2 -> Oscillator low/high/very high clock range
            MCGC2_HGO_M        | // HGO0   = 0,1   -> Oscillator low power/high gain
            MCGC2_EREFS_M      | // EREFS0 = 0,1   -> Select external clock/crystal oscillator
            MCGC2_LP_M         | // LP     = 0,1   -> Select FLL enabled/disabled in bypass mode
            MCGC2_IRCS_M;        // IRCS   = 0,1   -> Select slow/fast internal clock for internal reference

#endif // (CLOCK_MODE == CLOCK_MODE_BLPE) || (CLOCK_MODE == CLOCK_MODE_BLPI)
#endif // (CLOCK_MODE == CLOCK_MODE_RESET)

   // Basic clock multiplexing
#if defined(MCU_mcf51jm128)
//   SIM_SOPT2 = SIM_SOPT2_UART0SRC_M      | // UART0 clock - 0,1,2,3 -> Disabled, (MCGFLLCLK, MCGPLLCLK/2),  OSCERCLK, MCGIRCLK
//               SIM_SOPT2_TPMSRC_M ;        // TPM2 source
#else
   #error "Modify as required"
#endif

#ifdef SIM_CLKDIV1_USBFRAC_MASK
   SIM_CLKDIV1 = SIM_CLKDIV1_USBDIV_M | SIM_CLKDIV1_USBFRAC_M | SIM_CLKDIV1_USBSRC_M;
#endif

#ifdef SIM_CLKDIV0
   SIM_CLKDIV0 = SIM_CLKDIV0_M;
#endif

   SystemCoreClockUpdate();
}

/**
 * Initializes the system.
 * System control registers must be unlocked.
 */
void SYS_Init() {
    // TODO: why is SYS_UnlockReg() needed? Should be already unlocked.
    SYS_UnlockReg();

    // HIRC clock (internal RC 22.1184MHz)
    CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);

    // HCLK clock source: HIRC, HCLK source divider: 1
    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));

    // HXT clock (external XTAL 12MHz)
    CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
    CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);

    // Enable 72MHz optimization
    FMC_EnableFreqOptimizeMode(FMC_FTCTL_OPTIMIZE_72MHZ);

    // Core clock: PLL
    CLK_SetCoreClock(PLL_CLOCK);
    CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);

    // SPI0 clock: PCLK0
    CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK0, 0);
    CLK_EnableModuleClock(SPI0_MODULE);

    // TMR0-3 clock: HXT
    CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0);
    CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_HXT, 0);
    CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_HXT, 0);
    CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_HXT, 0);
    CLK_EnableModuleClock(TMR0_MODULE);
    CLK_EnableModuleClock(TMR1_MODULE);
    CLK_EnableModuleClock(TMR2_MODULE);
    CLK_EnableModuleClock(TMR3_MODULE);

    // PWM clock: PCLK0
    CLK_SetModuleClock(PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0);
    CLK_EnableModuleClock(PWM0_MODULE);

    // USBD clock
    CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV0_USB(3));
    CLK_EnableModuleClock(USBD_MODULE);

    // Enable USB 3.3V LDO
    SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk;

    // EADC clock: 72Mhz / 8
    CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));
    CLK_EnableModuleClock(EADC_MODULE);

    // Enable BOD (reset, 2.2V)
    SYS_EnableBOD(SYS_BODCTL_BOD_RST_EN, SYS_BODCTL_BODVL_2_2V);

    // Update system core clock
    SystemCoreClockUpdate();

    // Initialize dataflash
    Dataflash_Init();

    // Initialize I/O
    Display_SetupSPI();
    Button_Init();
    ADC_Init();
    Atomizer_Init();

    // Initialize display
    Display_Init();
}