C++ SetBits16函数代码示例

void nvds_read_bdaddr_from_otp()
{
    const uint16_t BDADDR_OFFSET = 0x7fd4; // offset of BD address in OTP header
    uint8_t *otp_bdaddr;

    if (!APP_BOOT_FROM_OTP)    
    {
        int cnt = 100000;
        #define XPMC_MODE_MREAD   0x1
        otp_bdaddr = (uint8_t *)0x40000 + BDADDR_OFFSET;   //where in OTP header is BDADDR
        
        SetBits16(CLK_AMBA_REG, OTP_ENABLE, 1);		// enable OTP clock	
        while ((GetWord16(ANA_STATUS_REG) & LDO_OTP_OK) != LDO_OTP_OK && cnt--)
            /* Just wait */;
            
        // set OTP in read mode 
        SetWord32(OTPC_MODE_REG, XPMC_MODE_MREAD);
    }
    else
        otp_bdaddr = (uint8_t *)0x20000000 + BDADDR_OFFSET;   //where in OTP header is BDADDR

#if BLE_JWAOO_TOY_SERVER
	memcpy(jwaoo_toy_device_data.bd_addr, otp_bdaddr, sizeof(jwaoo_toy_device_data.bd_addr));
#else
	memcpy(&dev_bdaddr, otp_bdaddr, sizeof(dev_bdaddr));
#endif

    SetBits16(CLK_AMBA_REG, OTP_ENABLE, 0);     //disable OTP clock    
}

/**
 ****************************************************************************************
 * @brief Enable pad's and peripheral clocks assuming that peripherals' power domain is down. The Uart and SPi clocks are set.
 *
 * @return void
 ****************************************************************************************
 */
void periph_init(void)  // set i2c, spi, uart, uart2 serial clks
{
	// Power up peripherals' power domain
    SetBits16(PMU_CTRL_REG, PERIPH_SLEEP, 0);
    while (!(GetWord16(SYS_STAT_REG) & PER_IS_UP)) ; 
    
    SetBits16(CLK_16M_REG,XTAL16_BIAS_SH_DISABLE, 1);
	
	//rom patch
	patch_func();
	
	//Init pads
	set_pad_functions();


#if (BLE_APP_PRESENT)
    
#if BLE_PROX_MONITOR
    app_proxm_port_reinit(XCY_LED0_GPIO);
    app_button_enable();
#elif BLE_FINDME_LOCATOR
    app_button_enable();
#endif //BLE_PROX_REPORTER
#if BLE_BATTERY_SERVER
    app_batt_port_reinit();
#endif //BLE_BATTERY_SERVER

#endif //BLE_APP_PRESENT

    // Enable the pads
	SetBits16(SYS_CTRL_REG, PAD_LATCH_EN, 1);
}

/**
 ****************************************************************************************
 * @brief Function to set the interrupt generated by the GPIO pin 
 *
 * @param[in] port  	    GPIO port
 * @param[in] pin   	    GPIO pin
 * @param[in] irq           GPIO IRQ
 * @param[in] low_input     TRUE generates an IRQ if the input is low
 * @param[in] release_wait  TRUE waits for key release after interrupt was reset
 * @param[in] debounce_ms	duration of a debounce sequence before an IRQ is generated
 *
 * @return void
 ****************************************************************************************
 */
void GPIO_EnableIRQ( GPIO_PORT port, GPIO_PIN pin, IRQn_Type irq, bool low_input,
					 bool release_wait, uint8_t debounce_ms )
{
    #if DEVELOPMENT_DEBUG
        #ifndef GPIO_DRV_PIN_ALLOC_MON_DISABLED
    if ( !(GPIO_status & ( ((uint64_t)1 << pin) << (port * 16) )) )
        __asm("BKPT #0\n"); // this pin has not been previously reserved!        
        #endif //GPIO_DRV_PIN_ALLOC_MON_DISABLED   
    #endif //DEVELOPMENT_DEBUG       
    
    const uint8_t   KBRD_IRQn_SEL_BASE[] = {
        1,
        9,
        15,
        25
    };
    
	SetBits16(GPIO_DEBOUNCE_REG, (DEB_ENABLE0 << (irq-GPIO0_IRQn)), (debounce_ms > 0) );
	SetBits16(GPIO_DEBOUNCE_REG, DEB_VALUE, debounce_ms);
	SetBits16(GPIO_INT_LEVEL_CTRL_REG, EDGE_LEVELn0 << (irq-GPIO0_IRQn), release_wait);
	SetBits16(GPIO_INT_LEVEL_CTRL_REG, INPUT_LEVEL0 << (irq-GPIO0_IRQn), low_input);
	SetBits16(GPIO_IRQ0_IN_SEL_REG + 2*(irq-GPIO0_IRQn), KBRD_IRQn_SEL, KBRD_IRQn_SEL_BASE[port] + pin);
    
	NVIC_SetPriority(irq, 2);
	NVIC_EnableIRQ(irq);
}

void iq_trim_from_otp()
{
#ifdef IQTRIM_FROM_OTP

#ifndef APP_BOOT_FROM_OTP    
    int cnt=100000;
#define XPMC_MODE_MREAD   0x1
    uint16_t *iqtrim = (uint16_t *)(0x40000 + IQTRIM_FROM_OTP);   //where in OTP header is IQ_Trim
    
    SetBits16(CLK_AMBA_REG, OTP_ENABLE, 1);		// enable OTP clock	
    while ((GetWord16(ANA_STATUS_REG) & LDO_OTP_OK) != LDO_OTP_OK && cnt--)
        /* Just wait */;
        
    // set OTP in read mode 
    SetWord32 (OTPC_MODE_REG,XPMC_MODE_MREAD);
#else
    uint16_t *iqtrim = (uint16_t *)(0x20000000 + IQTRIM_FROM_OTP);   //where in OTP header is IQ_Trim
#endif    
    
    iq_trim_bias_ctrl1_reg = *iqtrim++;
    iq_trim_rf_mixer_ctrl1_reg = *iqtrim;
    SetBits16(CLK_AMBA_REG, OTP_ENABLE, 0);     //disable OTP clock    
    #ifdef SUPPORT_1_8_V
        SetBits16(DCDC_CTRL2_REG, DCDC_VBAT3V_LEV, 0x0);   ///--Support 1.8V boot
    #endif
    
#endif    
}

void nvds_read_bdaddr_from_otp()
{
#ifdef BDADDR_FROM_OTP

#ifndef APP_BOOT_FROM_OTP    
    int cnt=100000;
#define XPMC_MODE_MREAD   0x1
    uint8_t *otp_bdaddr = (uint8_t *)0x40000 + BDADDR_FROM_OTP;   //where in OTP header is BDADDR
    
    SetBits16(CLK_AMBA_REG, OTP_ENABLE, 1);		// enable OTP clock	
    while ((GetWord16(ANA_STATUS_REG) & LDO_OTP_OK) != LDO_OTP_OK && cnt--)
        /* Just wait */;
        
    // set OTP in read mode 
    SetWord32 (OTPC_MODE_REG,XPMC_MODE_MREAD);
#else
    uint8_t *otp_bdaddr = (uint8_t *)0x20000000 + BDADDR_FROM_OTP;   //where in OTP header is BDADDR
#endif    
    
    memcpy(&dev_bdaddr, otp_bdaddr, sizeof(dev_bdaddr));
    SetBits16(CLK_AMBA_REG, OTP_ENABLE, 0);     //disable OTP clock    
    #ifdef SUPPORT_1_8_V
        SetBits16(DCDC_CTRL2_REG, DCDC_VBAT3V_LEV, 0x0);   ///--Support 1.8V boot
    #endif

#endif    
}

	/*
 	 *	Init TX and RX buffers, they are in EM but not in the retainable part
 	 *  so the pointers have to be programmed again	*
 	 */
	if(func_check_mem_flag)
	{
		
	  //init TX/RX buffers after DEEPSLEEP	
		co_buf_init_deep_sleep();
		// Set the first RX descriptor pointer into the HW
        ble_currentrxdescptr_set(REG_BLE_EM_RX_ADDR_GET(co_buf_rx_current_get()));
        	
       //INIT NONE RET. HEAP after DEEPSLEEP	
       	ke_mem_init(KE_MEM_NON_RETENTION, (uint8_t*)(jump_table_struct[rwip_heap_non_ret_pos]), jump_table_struct[rwip_heap_non_ret_size]);

		func_check_mem_flag = false;
		
	}
 #endif //RW_BLE_SUPPORT
#endif //DEEP_SLEEP
}

// /*********************************************************************************
//  *** SLP_INT ISR
//  ***/
void BLE_SLP_Handler(void)
//void BLE_SLP_Handler_func(void)
{
	ble_regs_pop();
	//smpc_regs_pop();
    
#if !DEEP_SLEEP_ENABLED
# if  DEVELOPMENT__NO_OTP    
	SetBits16(SYS_CTRL_REG, DEBUGGER_ENABLE, 1);   
# endif	// DEVELOPMENT__NO_OTP
#endif // !DEEP_SLEEP_ENABLED

	SetBits16(GP_CONTROL_REG, BLE_WAKEUP_REQ, 0);   //just to be sure, kostas ninos    

    if(jump_table_struct[0] == TASK_GTL)	
	{
		// UART and pads have already been activated by periph_init() which is called
		// at initialization by main_func() and during wakeup by BLE_WAKEUP_LP_Handler().
		
		gtl_eif_init();
	}

	SetBits32(BLE_INTACK_REG, SLPINTACK, 1);

#if DEEP_SLEEP //Needed only for compilation. Remove when ROM code is ready.
#if RW_BLE_SUPPORT
	rwip_wakeup();
#endif //RW_BLE_SUPPORT
#endif //DEEP_SLEEP
}

/**
 ****************************************************************************************
 * @brief Read low power clock selection from 
 *
 * The Hclk and Pclk are set
 ****************************************************************************************
*/
void select_lp_clk()
{
#if (CFG_LP_CLK == LP_CLK_FROM_OTP)
    int cnt = 100000;

# ifndef APP_BOOT_FROM_OTP    
#define XPMC_MODE_MREAD   0x1
    uint16_t *lp_clk = (uint16_t *)(0x40000 + LP_CLK_OTP_OFFSET);     //where in OTP header is IQ_Trim
    
    SetBits16(CLK_AMBA_REG, OTP_ENABLE, 1);                           //enable OTP clock	
    while ((GetWord16(ANA_STATUS_REG) & LDO_OTP_OK) != LDO_OTP_OK && cnt--)
        /* Just wait */;
        
    // set OTP in read mode 
    SetWord32(OTPC_MODE_REG, XPMC_MODE_MREAD);
# else
    uint16_t *lp_clk = (uint16_t *)(0x20000000 + LP_CLK_OTP_OFFSET);  //where in OTP header is IQ_Trim
# endif //APP_BOOT_FROM_OTP   

    lp_clk_sel  = (*lp_clk);
    SetBits16(CLK_AMBA_REG, OTP_ENABLE, 0);                           //disable OTP clock     
    
#else //CFG_LP_CLK 
    lp_clk_sel = CFG_LP_CLK; 
#endif    
}

/**
 ****************************************************************************************
 * @brief Enable pad's and peripheral clocks assuming that peripherals' power domain is down. The Uart and SPi clocks are set.
 *
 * @return void
 ****************************************************************************************
 */
void periph_init(void) 
{
	// Power up peripherals' power domain
    SetBits16(PMU_CTRL_REG, PERIPH_SLEEP, 0);
    while (!(GetWord16(SYS_STAT_REG) & PER_IS_UP)) ; 
    
#if ES4_CODE
    SetBits16(CLK_16M_REG,XTAL16_BIAS_SH_DISABLE, 1);
#endif    
	
	//rom patch
	patch_func();
	
	//Init pads
	set_pad_functions();

#if (BLE_APP_PRESENT)
/*
* (Re)Initialize peripherals
i.e.    
    uart_init(UART_BAUDRATE_115K2, 3);
*/        
#endif
    
    // Enable the pads
	SetBits16(SYS_CTRL_REG, PAD_LATCH_EN, 1);
}

/**
 ****************************************************************************************
 * @brief Starts RCX20 calibration. 
 *
 * @param[in]   cal_time. Calibration time in RCX20 cycles. 
 *
 * @return void 
 ****************************************************************************************
 */
void calibrate_rcx20(uint16_t cal_time)
{
    
    SetWord16(CLK_REF_CNT_REG, cal_time);
    SetBits16(CLK_REF_SEL_REG, REF_CLK_SEL, 0x3); //RCX select 
    SetBits16(CLK_REF_SEL_REG, REF_CAL_START, 0x1); //Start Calibration
    cal_enable = 1;
}

/**
 ****************************************************************************************
 * @brief Deactivate communication with the 3-wire SPI
 ****************************************************************************************
 */
void deactivate_3wire_spi(void)
{
    GPIO_SetActive(cs.port, cs.pin);                                            // leave CS high
    GPIO_SetPinFunction( sdio.port, sdio.pin, INPUT, PID_SPI_DI);
    NVIC_DisableIRQ(SPI_IRQn);                                                  // disable SPI interrupt
    SetBits16(SPI_CTRL_REG, SPI_ON, 0);                                         // close SPI block, if opened
    SetBits16(CLK_PER_REG, SPI_ENABLE, 0);                                      // disable clock for SPI
}

/**
 ****************************************************************************************
 * @brief 
 *
 * @param[in]
 *
 * @return 
 ****************************************************************************************
 */
void quad_decoder_enable_irq(uint8_t event_count)
{
    SetBits16(QDEC_CTRL_REG, QD_IRQ_CLR, 1);                               // clear any garbagge
    NVIC_ClearPendingIRQ(WKUP_QUADEC_IRQn);                                // clear it to be on the safe side...
    
    SetBits16(QDEC_CTRL_REG, QD_IRQ_THRES, event_count);                   // Set event counter
    SetBits16(QDEC_CTRL_REG, QD_IRQ_MASK, 1);                              // interrupt not masked                               
    NVIC_EnableIRQ(WKUP_QUADEC_IRQn);                                      // enable the WKUP_QUADEC_IRQn
}    

/**
 ****************************************************************************************
 * @brief Starts RCX20 calibration. 
 *
 * @param[in]   cal_time. Calibration time in RCX20 cycles. 
 *
 * @return void 
 ****************************************************************************************
 */
void calibrate_rcx20(uint16_t cal_time)
{
    if ((CFG_LP_CLK == LP_CLK_FROM_OTP) || (CFG_LP_CLK == LP_CLK_RCX20))
    {
        SetWord16(CLK_REF_CNT_REG, cal_time);
        SetBits16(CLK_REF_SEL_REG, REF_CLK_SEL, 0x3); //RCX select 
        SetBits16(CLK_REF_SEL_REG, REF_CAL_START, 0x1); //Start Calibration
        cal_enable = 1;
    }
}

/**
 ****************************************************************************************
 * @brief Initialize communication with the 3-wire SPI
 * @param[in] spi_sdio_pin_register: Size of the data to be read
 * @param[in] TsradCounterToSet: Counter for the delay between Address and Data phase in reading
 *
 ****************************************************************************************
 */
void initialize_3wire_spi(struct SPI_Config *cfg, bool enable_interrupt,  uint16_t TsradCounterToSet)
{
    sdio.port = cfg->sdio.port;                                   // initialize with param data;
    sdio.pin = cfg->sdio.pin;
    cs.port = cfg->cs.port;
    cs.pin = cfg->cs.pin;

    //configure pins
    GPIO_ConfigurePin( cfg->cs.port, cfg->cs.pin, OUTPUT, PID_SPI_EN, true);
    GPIO_SetPinFunction( cfg->sdio.port, cfg->sdio.pin, INPUT, PID_SPI_DI);
    GPIO_SetPinFunction( cfg->clk.port, cfg->clk.pin, OUTPUT, PID_SPI_CLK);

    TsradCounter = TsradCounterToSet;                             // SPI read address-data delay (refer to sensor datasheet)

    // init SPI
    SetBits16(CLK_PER_REG, SPI_ENABLE, 1);                        // enable  clock for SPI
    SetBits16(SPI_CTRL_REG,SPI_ON,0);                             // close SPI block, if opened
    SetBits16(SPI_CTRL_REG,SPI_WORD, cfg->SPI_Word_Mode);         // SPI word mode
    SetBits16(SPI_CTRL_REG,SPI_SMN, cfg->SPI_Role);               // SPI master mode
    SetBits16(SPI_CTRL_REG,SPI_POL, cfg->SPI_Polarity_Mode);      // SPI mode selection - polarity
    SetBits16(SPI_CTRL_REG,SPI_PHA, cfg->SPI_PHA_Mode);           // SPI mode selection - phase
    SetBits16(SPI_CTRL_REG,SPI_MINT, cfg->SPI_MINT_Mode);         // disable SPI interrupt to the ICU
    SetBits16(SPI_CTRL_REG,SPI_CLK, cfg->SPI_XTAL_Freq);          // SPI block clock divider
    SetBits16(SPI_CTRL_REG,SPI_ON, 1);                            // enable SPI block
    if (enable_interrupt)
        NVIC_EnableIRQ(SPI_IRQn);                                 // enable SPI interrupt, if MINT is '1' and enable_interrupt is set

}

void uart_initialization(void)
{
	SetBits16(CLK_PER_REG, UART1_ENABLE, 1);  	// enable  clock for UART 1

	SetWord16(UART_LCR_REG, 0x80); // set bit to access DLH and DLL register
	SetWord16(UART_IER_DLH_REG,(UART_BAUDRATE_115K2&0xFF>>8));//set high byte
	SetWord16(UART_RBR_THR_DLL_REG,UART_BAUDRATE_115K2&0xFF);//set low byte
	SetWord16(UART_LCR_REG,UART_DATALENGTH|UART_PARITY|UART_STOPBITS);
	SetBits16(UART_MCR_REG, UART_SIRE, 0);  // mode 0 for normal , 1 for IRDA
	SetWord16(UART_IIR_FCR_REG,1);  // enable fifo  
	SetBits16(UART_IER_DLH_REG,ERBFI_dlh0,0);  // IER access, disable interrupt for available data
}

/**
 ****************************************************************************************
 * @brief Initialize I2C controller as a master for EEPROM handling.
 ****************************************************************************************
 */
void i2c_eeprom_init(uint16_t dev_address, uint8_t speed, uint8_t address_mode, uint8_t address_size)
{
    mem_address_size = address_size;
    SetBits16(CLK_PER_REG, I2C_ENABLE, 1);                                        // enable  clock for I2C 
    SetWord16(I2C_ENABLE_REG, 0x0);                                               // Disable the I2C controller	
    SetWord16(I2C_CON_REG, I2C_MASTER_MODE | I2C_SLAVE_DISABLE | I2C_RESTART_EN); // Slave is disabled
    SetBits16(I2C_CON_REG, I2C_SPEED, speed);                                     // Set speed
    SetBits16(I2C_CON_REG, I2C_10BITADDR_MASTER, address_mode);                   // Set addressing mode
    SetWord16(I2C_TAR_REG, dev_address & 0x3FF);                                  // Set Slave device address
    SetWord16(I2C_ENABLE_REG, 0x1);                                               // Enable the I2C controller
    while( (GetWord16(I2C_STATUS_REG) & 0x20) != 0 );                             // Wait for I2C master FSM to be IDLE
    i2c_dev_address = dev_address;
}