本文整理汇总了C++中SStream_concat0函数的典型用法代码示例。如果您正苦于以下问题:C++ SStream_concat0函数的具体用法?C++ SStream_concat0怎么用?C++ SStream_concat0使用的例子?那么, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了SStream_concat0函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: printDstIdx
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
{
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
}
// DI accesses are always ES-based on non-64bit mode
if (MI->csh->mode != CS_MODE_64) {
SStream_concat0(O, "%es:(");
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES;
}
} else
SStream_concat0(O, "(");
set_mem_access(MI, true);
printOperand(MI, Op, O);
SStream_concat0(O, ")");
set_mem_access(MI, false);
}
示例2: printSrcIdx
static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *SegReg;
int reg;
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
}
SegReg = MCInst_getOperand(MI, Op+1);
reg = MCOperand_getReg(SegReg);
// If this has a segment register, print it.
if (reg) {
_printOperand(MI, Op+1, O);
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg;
}
SStream_concat0(O, ":");
}
SStream_concat0(O, "[");
set_mem_access(MI, true);
printOperand(MI, Op, O);
SStream_concat0(O, "]");
set_mem_access(MI, false);
}
示例3: printMemOperand
static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier)
{
MCOperand *MO;
set_mem_access(MI, true);
printOperand(MI, opNum, O);
// If this is an ADD operand, emit it like normal operands.
if (Modifier && !strcmp(Modifier, "arith")) {
SStream_concat0(O, ", ");
printOperand(MI, opNum + 1, O);
set_mem_access(MI, false);
return;
}
MO = MCInst_getOperand(MI, opNum + 1);
if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) {
set_mem_access(MI, false);
return; // don't print "+%g0"
}
if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) {
set_mem_access(MI, false);
return; // don't print "+0"
}
SStream_concat0(O, "+"); // qq
printOperand(MI, opNum + 1, O);
set_mem_access(MI, false);
}
示例4: printf32mem
static void printf32mem(MCInst *MI, unsigned OpNo, SStream *O)
{
switch(MCInst_getOpcode(MI)) {
default:
SStream_concat0(O, "dword ptr ");
MI->x86opsize = 4;
break;
case X86_FBSTPm:
case X86_FBLDm:
// TODO: fix this in tablegen instead
SStream_concat0(O, "tbyte ptr ");
MI->x86opsize = 10;
break;
case X86_FSTENVm:
case X86_FLDENVm:
// TODO: fix this in tablegen instead
switch(MI->csh->mode) {
default: // never reach
break;
case CS_MODE_16:
MI->x86opsize = 14;
break;
case CS_MODE_32:
case CS_MODE_64:
MI->x86opsize = 28;
break;
}
break;
}
printMemReference(MI, OpNo, O);
}
示例5: printMemOffset
static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *DispSpec = MCInst_getOperand(MI, Op);
MCOperand *SegReg = MCInst_getOperand(MI, Op + 1);
int reg;
if (MI->csh->detail) {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
#ifndef CAPSTONE_DIET
get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
#endif
}
// If this has a segment register, print it.
reg = MCOperand_getReg(SegReg);
if (reg) {
_printOperand(MI, Op + 1, O);
SStream_concat0(O, ":");
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg;
}
}
SStream_concat0(O, "[");
if (MCOperand_isImm(DispSpec)) {
int64_t imm = MCOperand_getImm(DispSpec);
if (MI->csh->detail)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
if (imm < 0) {
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm);
} else {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
}
}
SStream_concat0(O, "]");
if (MI->csh->detail)
MI->flat_insn->detail->x86.op_count++;
if (MI->op1_size == 0)
MI->op1_size = MI->x86opsize;
}
示例6: printVectorIndex
static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
{
SStream_concat0(O, "[");
printInt32(O, (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
SStream_concat0(O, "]");
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vector_index = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
}
}
示例7: printRoundingControl
static void printRoundingControl(MCInst *MI, unsigned Op, SStream *O)
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3;
switch (Imm) {
case 0: SStream_concat0(O, "{rn-sae}"); break;
case 1: SStream_concat0(O, "{rd-sae}"); break;
case 2: SStream_concat0(O, "{ru-sae}"); break;
case 3: SStream_concat0(O, "{rz-sae}"); break;
default: break; // nev0er reach
}
}
示例8: printRoundingControl
void printRoundingControl(MCInst *MI, unsigned Op, SStream *O)
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3;
switch (Imm) {
case 0: SStream_concat0(O, "{rn-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RN); break;
case 1: SStream_concat0(O, "{rd-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RD); break;
case 2: SStream_concat0(O, "{ru-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RU); break;
case 3: SStream_concat0(O, "{rz-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RZ); break;
default: break; // never reach
}
}
示例9: printTLSCall
static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O)
{
set_mem_access(MI, true);
//printBranchOperand(MI, OpNo, O);
// On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
// come at the _end_ of the expression.
SStream_concat0(O, "(");
printOperand(MI, OpNo + 1, O);
SStream_concat0(O, ")");
set_mem_access(MI, false);
}
示例10: printMemRegReg
static void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O)
{
// When used as the base register, r0 reads constant zero rather than
// the value contained in the register. For this reason, the darwin
// assembler requires that we print r0 as 0 (no r) when used as the base.
if (MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == PPC_R0)
SStream_concat0(O, "0");
else
printOperand(MI, OpNo, O);
SStream_concat0(O, ", ");
printOperand(MI, OpNo + 1, O);
}
示例11: printVectorList
static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, char *LayoutSuffix, MCRegisterInfo *MRI, arm64_vas vas, arm64_vess vess)
{
#define GETREGCLASS_CONTAIN0(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), _reg)
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
unsigned NumRegs = 1, FirstReg, i;
SStream_concat0(O, "{");
// Work out how many registers there are in the list (if there is an actual
// list).
if (GETREGCLASS_CONTAIN0(AArch64_DDRegClassID , Reg) ||
GETREGCLASS_CONTAIN0(AArch64_QQRegClassID, Reg))
NumRegs = 2;
else if (GETREGCLASS_CONTAIN0(AArch64_DDDRegClassID, Reg) ||
GETREGCLASS_CONTAIN0(AArch64_QQQRegClassID, Reg))
NumRegs = 3;
else if (GETREGCLASS_CONTAIN0(AArch64_DDDDRegClassID, Reg) ||
GETREGCLASS_CONTAIN0(AArch64_QQQQRegClassID, Reg))
NumRegs = 4;
// Now forget about the list and find out what the first register is.
if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_dsub0)))
Reg = FirstReg;
else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_qsub0)))
Reg = FirstReg;
// If it's a D-reg, we need to promote it to the equivalent Q-reg before
// printing (otherwise getRegisterName fails).
if (GETREGCLASS_CONTAIN0(AArch64_FPR64RegClassID, Reg)) {
MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID);
Reg = MCRegisterInfo_getMatchingSuperReg(MRI, Reg, AArch64_dsub, FPR128RC);
}
for (i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg, 1)) {
SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), LayoutSuffix);
if (i + 1 != NumRegs)
SStream_concat0(O, ", ");
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg);
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vas = vas;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vess = vess;
MI->flat_insn->detail->arm64.op_count++;
}
}
SStream_concat0(O, "}");
}
示例12: printMemRegImm
static void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O)
{
set_mem_access(MI, true);
printS16ImmOperand_Mem(MI, OpNo, O);
SStream_concat0(O, "(");
if (MCOperand_getReg(MCInst_getOperand(MI, OpNo + 1)) == PPC_R0)
SStream_concat0(O, "0");
else
printOperand(MI, OpNo + 1, O);
SStream_concat0(O, ")");
set_mem_access(MI, false);
}
示例13: printPostIncOperand
static void printPostIncOperand(MCInst *MI, unsigned OpNo,
unsigned Imm, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned Reg = MCOperand_getReg(Op);
if (Reg == AArch64_XZR) {
printInt32Bang(O, Imm);
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm;
MI->flat_insn->detail->arm64.op_count++;
}
} else {
SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
MI->flat_insn->detail->arm64.op_count++;
}
}
}
//llvm_unreachable("unknown operand kind in printPostIncOperand64");
}
示例14: printDstIdx
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
{
if (MI->csh->detail) {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
#ifndef CAPSTONE_DIET
get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
#endif
}
// DI accesses are always ES-based on non-64bit mode
if (MI->csh->mode != CS_MODE_64) {
SStream_concat(O, "es:[");
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES;
}
} else
SStream_concat(O, "[");
set_mem_access(MI, true);
printOperand(MI, Op, O);
SStream_concat0(O, "]");
set_mem_access(MI, false);
}
示例15: printCCOperand
static void printCCOperand(MCInst *MI, int opNum, SStream *O)
{
int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, opNum)) + 256;
switch (MCInst_getOpcode(MI)) {
default: break;
case SP_FBCOND:
case SP_FBCONDA:
case SP_BPFCC:
case SP_BPFCCA:
case SP_BPFCCNT:
case SP_BPFCCANT:
case SP_MOVFCCrr: case SP_V9MOVFCCrr:
case SP_MOVFCCri: case SP_V9MOVFCCri:
case SP_FMOVS_FCC: case SP_V9FMOVS_FCC:
case SP_FMOVD_FCC: case SP_V9FMOVD_FCC:
case SP_FMOVQ_FCC: case SP_V9FMOVQ_FCC:
// Make sure CC is a fp conditional flag.
CC = (CC < 16+256) ? (CC + 16) : CC;
break;
}
SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC));
if (MI->csh->detail)
MI->flat_insn->detail->sparc.cc = (sparc_cc)CC;
}