C++ SCB_EnableICache函数代码示例

void _core_init(void)
{
	//SystemInit();
	//SystemCoreClockUpdate();
	  /* Enable the CPU Cache */
	  /* Enable I-Cache */
	  SCB_EnableICache();

	  /* Enable D-Cache */
	  SCB_EnableDCache();
	SystemClock_Config(HSI_VALUE, HSE_VALUE, FCPU);
	HAL_Init();
#if (defined(STM32F769xx) || defined(STM32F779xx)) && defined(STM32F769I_DISCO)
#include <driver/stm32769i_discovery_sdram.h>
	BSP_STM32769I_DISCOVERY_SDRAM_Init();
#endif
	//SystemCoreClockUpdate();
	//RCC_PCLK1Config(RCC_HCLK_Div4);
	//RCC_PCLK2Config(RCC_HCLK_Div2);
	gpio.init(0);
	gpio.init(1);
	gpio.init(2);
	gpio.init(3);
	gpio.init(4);
	gpio.init(5);
	gpio.init(6);
	gpio.init(7);
	gpio.init(8);
	gpio.init(9);
	gpio.init(10);
}

/**
  * @brief  CPU L1-Cache enable.
  * @param  None
  * @retval None
  */
static void CPU_CACHE_Enable(void){
  /* Enable I-Cache */
  SCB_EnableICache();

  /* Enable D-Cache */
  SCB_EnableDCache();
}

/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
void __core_init(void) {

#if CORTEX_MODEL == 7
  SCB_EnableICache();
  SCB_EnableDCache();
#endif
}

void Raw32OSInit(void) {
    /* Enable the CPU Cache's */
	SCB_EnableICache();	// Enable I-Cache
	SCB_EnableDCache();	// Enable D-Cache


    /* STM32F7xx HAL library initialization:
         - Configure the Flash ART accelerator on ITCM interface
         - Configure the Systick to generate an interrupt each 1 msec
         - Set NVIC Group Priority to 4
         - Global MSP (MCU Support Package) initialization
       */
    HAL_Init();

    /* Configure the system clock to 216 MHz */
    SystemClock_Config();

#if !GFX_USE_OS_CHIBIOS
    // LED - for testing
	GPIO_InitTypeDef  GPIO_InitStruct;
	GPIO_InitStruct.Pin = GPIO_PIN_1;
	GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
	GPIO_InitStruct.Pull = GPIO_NOPULL;
	GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
    __GPIOI_CLK_ENABLE();
	HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
#endif

}

/**
 * \brief Application entry point for ssc_dam_audio example.
 *
 * \return Unused (ANSI-C compatibility).
 */
int main( void )
{    
    uint16_t data = 0;
    /* Disable watchdog */
    WDT_Disable( WDT ) ;
 
    /* Enable I and D cache */
    SCB_EnableICache();
    SCB_EnableDCache();

    /* Output example information */
    printf("-- SSC DMA Audio Example %s --\n\r", SOFTPACK_VERSION);
    printf("-- %s\n\r", BOARD_NAME);
    printf("-- Compiled: %s %s --\n\r", __DATE__, __TIME__);

    /* Configure systick for 1 ms. */
    printf( "Configure system tick to get 1ms tick period.\n\r" ) ;
    if ( TimeTick_Configure( ) )
    {
        printf("-F- Systick configuration error\n\r" ) ;
    }

    /* Configure all pins */
    PIO_Configure(pinsSsc, PIO_LISTSIZE(pinsSsc));

    /* Configure SSC */
    SSC_Configure(AUDIO_IF , 0 , SSC_MCK );
    SSC_ConfigureReceiver(AUDIO_IF,I2S_SLAVE_RX_SETTING,I2S_SLAVE_RX_FRM_SETTING);
    SSC_DisableReceiver(AUDIO_IF);
    SSC_ConfigureTransmitter(AUDIO_IF,I2S_SLAVE_TX_SETTING,I2S_SLAVE_TX_FRM_SETTING);
    SSC_DisableTransmitter(AUDIO_IF);

    /* Configure DMA */
    Dma_configure();

    /* Configure and enable the TWI (required for accessing the DAC) */
    PMC_EnablePeripheral(ID_TWIHS0);
    TWI_ConfigureMaster(TWIHS0, TWI_CLOCK, BOARD_MCK);
    TWID_Initialize(&twid, TWIHS0);
    /* Configure TWI interrupts */
    NVIC_ClearPendingIRQ(TWIHS0_IRQn);
    NVIC_EnableIRQ(TWIHS0_IRQn);

    /* check that WM8904 is present */
    WM8904_Write(&twid, WM8904_SLAVE_ADDRESS, 22, 0);
    data=WM8904_Read(&twid, WM8904_SLAVE_ADDRESS, 0);
    if( data != 0x8904){
        printf("WM8904 not found!\n\r");
        while(1);
    }
    /* Initialize the audio DAC */
    WM8904_Init(&twid, WM8904_SLAVE_ADDRESS, PMC_MCKR_CSS_SLOW_CLK); 

    /* Enable the DAC master clock */
    PMC_ConfigurePCK2(PMC_MCKR_CSS_SLOW_CLK, PMC_MCKR_PRES_CLK_1 );
    printf("Insert Line-in cable with PC Headphone output\n\r");
    PlayRecording();
    while ( 1 );
}

/**
 *  \brief Application entry point for UART example.
 *
 *  \return Unused (ANSI-C compatibility).
 */
extern int main(void)
{
	uint8_t ucKey;

	/* Disable watchdog */
	WDT_Disable(WDT);

	/* Output example information */
	printf("-- UART Example %s --\n\r", SOFTPACK_VERSION);
	printf("-- %s\n\r", BOARD_NAME);
	printf("-- Compiled: %s %s With %s--\n\r", __DATE__, __TIME__, COMPILER_NAME);

	/* Enable I and D cache */
	SCB_EnableICache();
	SCB_EnableDCache();

	/* Display menu */
	DisplayMenu();

	while (1) {
		ucKey = DBG_GetChar();

		switch (ucKey) {
		case 'h':
			DisplayMenu();
			break;
		case 'i':
		case 'I':
			printf("\n\rSending Tx Buffer.. \n\r");
			UartTransfer();
			break;

		case 'd':
		case 'D':
			memset(pRxBuffer,'X' ,30);
			pRxBuffer[28] = '\n';
			pRxBuffer[29] = '\r';
			printf("\n\rRx Buffer before transfer is \n\r");
			puts((char*)pRxBuffer);
			_UartdConfigLB();
			UARTD_EnableRxChannels(&Uartd, &UartRx);
			UARTD_EnableTxChannels(&Uartd, &UartTx);
			UARTD_RcvData(&Uartd);
			UARTD_SendData(&Uartd);

			printf("\n\rRx Buffer after transfer is \n\r");

			while (Uartd.pRxChannel->sempaphore == 0);
			puts((char*)pRxBuffer);
			UARTD_DisableRxChannels(&Uartd, &UartRx);
			UARTD_DisableTxChannels(&Uartd, &UartTx);
			break;

		default :
			break;
		}
	}
}

/**
 * \brief usb_massstorage Application entry point.
 *
 * Configures UART,
 * Configures TC0, USB MSD Driver and run it.
 *
 * \return Unused (ANSI-C compatibility).
 */
int main( void )
{
    sSdCard *pSd = 0;
 
    /* Disable watchdog */
    WDT_Disable( WDT ) ;
        
    SCB_EnableICache();
    SCB_EnableDCache();

#if defined LUN_RAMDISK
     /* Enable SDRAM */
    BOARD_ConfigureSdram();
#endif

    TRACE_INFO("-- USB Device Mass Storage Example %s --\n\r", SOFTPACK_VERSION);
    TRACE_INFO("-- %s\n\r", BOARD_NAME);
    TRACE_INFO("-- Compiled: %s %s --\n\r", __DATE__, __TIME__);

    /* If they are present, configure Vbus & Wake-up pins */
    PIO_InitializeInterrupts(0);

    /* Initialize all USB power (off) */
    _ConfigureUotghs();
    /* Initialize PIO pins */
    _ConfigurePIOs();

    /* Initialize drivers */
    _ConfigureDrivers();

    _MemoriesInitialize(pSd);
    
    /* BOT driver initialization */
    MSDDriver_Initialize(&msdDriverDescriptors, luns, MAX_LUNS);

    /* connect if needed */
    USBD_Connect();
    while (1) {

        /* Mass storage state machine */
        if (USBD_GetState() < USBD_STATE_CONFIGURED){}
        else 
        {
          MSDDriver_StateMachine();
          
          if (msdRefresh)
          {
              msdRefresh = 0;

              if (msdWriteTotal < 50 * 1000)
              {
                  /* Flush Disk Media */
              }
              msdWriteTotal = 0;
          }
        }
    }
}

/**
  * @brief  CPU L1-Cache enable.
  * @param  None
  * @retval None
  */
static void CPU_CACHE_Enable(void)
{
    /* Enable branch prediction */
  SCB->CCR |= (1 <<18); 
  __DSB();

  /* Enable I-Cache */
  SCB_EnableICache();

  /* Enable D-Cache */
  SCB_EnableDCache();
}

static void prvSetupHardware( void )
{
	/* Disable watchdog. */
	WDT_Disable( WDT );
	WDT_Disable( ( Wdt * ) RSWDT );

	SCB_EnableICache();
	SCB_EnableDCache();

    LED_Configure( 0 );
    LED_Configure( 1 );
}

void
SystemInit ()
{
#ifdef __USE_FPU__
  /* Initialize FPU */
  FpuInit ();
#endif
#ifdef __USE_CACHE__
  /* Enable Instruction Cache */
  SCB_EnableICache ();
  /* Enable Data Cache */
  SCB_EnableDCache ();
#endif
}

/**
 * @brief  CPU L1-Cache enable.
 *         Invalidate Data cache before enabling
 *         Enable Data & Instruction Cache
 * @param  None
 * @retval None
 */
static void CPU_CACHE_Enable(void){

	(*(uint32_t *) 0xE000ED94) &= ~0x5;
	(*(uint32_t *) 0xE000ED98) = 0x0; //MPU->RNR
	(*(uint32_t *) 0xE000ED9C) = 0x20010000 |1<<4; //MPU->RBAR
	(*(uint32_t *) 0xE000EDA0) = 0<<28 | 3 <<24 | 0<<19 | 0<<18 | 1<<17 | 0<<16 | 0<<8 | 30<<1 | 1<<0 ; //MPU->RASE  WT
	(*(uint32_t *) 0xE000ED94) = 0x5;

	/* Invalidate I-Cache : ICIALLU register*/
	SCB_InvalidateICache();

	/* Enable branch prediction */
	SCB->CCR |= (1 <<18);
	__DSB();

	/* Enable I-Cache */
	SCB_EnableICache();

	/* Enable D-Cache */
	SCB_InvalidateDCache();
	SCB_EnableDCache();
}

void system_init(void)
{
    SCB_EnableICache();
    SCB_EnableDCache();

    DBG_INIT();

    init_system_clock();

    HAL_Init();

    BSP_SDRAM_Init();
    BSP_LED_Init(LED1);
    BSP_PB_Init(BUTTON_KEY, BUTTON_MODE_GPIO);

    MX_FATFS_Init();

    FRESULT res = f_mount(&ctx.fs, SD_Path, 0);
    ASSERT_WARN(res == FR_OK);

    gui_init();
}

// BSP functions =============================================================
void BSP::init(void) {
    // NOTE: SystemInit() has been already called from the startup code
    // but SystemCoreClock needs to be updated
    SystemCoreClockUpdate();

    // NOTE: The VFP (hardware Floating Point) unit is configured by FreeRTOS */

    SCB_EnableICache(); // Enable I-Cache
    SCB_EnableDCache(); // Enable D-Cache

    // Configure Flash prefetch and Instr. cache through ART accelerator
#if (ART_ACCLERATOR_ENABLE != 0)
    __HAL_FLASH_ART_ENABLE();
#endif // ART_ACCLERATOR_ENABLE

    /* Configure the LEDs */
    BSP_LED_Init(LED1);
    BSP_LED_Init(LED2);
    BSP_LED_Init(LED3);

    // Configure the User Button in GPIO Mode
    BSP_PB_Init(BUTTON_KEY, BUTTON_MODE_GPIO);

    //...
    BSP::randomSeed(1234U);

    // initialize the QS software tracing...
    if (!QS_INIT((void *)0)) {
        Q_ERROR();
    }
    QS_OBJ_DICTIONARY(&l_TickHook);
    QS_OBJ_DICTIONARY(&l_EXTI0_IRQHandler);
    QS_USR_DICTIONARY(PHILO_STAT);
    QS_USR_DICTIONARY(PAUSED_STAT);
    QS_USR_DICTIONARY(COMMAND_STAT);
}

/**
 *  \brief gmac_uip_telnetd example entry point.
 *
 *  \return Unused (ANSI-C compatibility).
 */
int main(void)
{
	uip_ipaddr_t ipaddr;
	struct timer periodic_timer, arp_timer;
	uint32_t i;
	struct uip_eth_addr OrigiGMacAddr;

	/* Disable watchdog */
	WDT_Disable(WDT);

	SCB_EnableICache();
	SCB_EnableDCache();

	TimeTick_Configure();
	printf("-- GMAC uIP Telnetd Example %s --\n\r", SOFTPACK_VERSION);
	printf("-- %s\n\r", BOARD_NAME);
	printf("-- Compiled: %s %s With %s--\n\r", __DATE__, __TIME__ ,
			COMPILER_NAME);

	/* Configure systick for 1 ms. */
	TimeTick_Configure();
	/* Configure TWI pins. */
	PIO_Configure(twiPins, PIO_LISTSIZE(twiPins));
	/* Enable TWI */
	PMC_EnablePeripheral(BOARD_ID_TWI_EEPROM);
	TWI_ConfigureMaster(BOARD_BASE_TWI_EEPROM, TWCK, BOARD_MCK);
	TWID_Initialize(&twid, BOARD_BASE_TWI_EEPROM);
	/* Display MAC & IP settings */
	TWID_Read(&twid, AT24MAC_SERIAL_NUM_ADD, 0x9A, 1, OrigiGMacAddr.addr, PAGE_SIZE,
				0);

	if ((OrigiGMacAddr.addr[0] == 0xFC) && (OrigiGMacAddr.addr[1] == 0xC2)
		&& (OrigiGMacAddr.addr[2] == 0x3D)) {
		for (i = 0; i < 6; i++)
			GMacAddress.addr[i] = OrigiGMacAddr.addr[i];
	}

	printf("-- MAC %x:%x:%x:%x:%x:%x\n\r",
			GMacAddress.addr[0], GMacAddress.addr[1], GMacAddress.addr[2],
			GMacAddress.addr[3], GMacAddress.addr[4], GMacAddress.addr[5]);

#ifndef __DHCPC_H__
	printf(" - Host IP  %d.%d.%d.%d\n\r",
			HostIpAddress[0], HostIpAddress[1], HostIpAddress[2], HostIpAddress[3]);
	printf(" - Router IP  %d.%d.%d.%d\n\r",
			RoutIpAddress[0], RoutIpAddress[1], RoutIpAddress[2], RoutIpAddress[3]);
	printf(" - Net Mask  %d.%d.%d.%d\n\r",
			NetMask[0], NetMask[1], NetMask[2], NetMask[3]);
#endif

	/* System devices initialize */
	gmac_tapdev_setmac((uint8_t *)GMacAddress.addr);
	gmac_tapdev_init();
	clock_init();
	timer_set(&periodic_timer, CLOCK_SECOND / 2);
	timer_set(&arp_timer, CLOCK_SECOND * 10);

	/* Init uIP */
	uip_init();

#ifdef __DHCPC_H__
	printf("P: DHCP Supported\n\r");
	uip_ipaddr(ipaddr, 0, 0, 0, 0);
	uip_sethostaddr(ipaddr);
	uip_ipaddr(ipaddr, 0, 0, 0, 0);
	uip_setdraddr(ipaddr);
	uip_ipaddr(ipaddr, 0, 0, 0, 0);
	uip_setnetmask(ipaddr);
#else
	/* Set the IP address of this host */
	uip_ipaddr(ipaddr, HostIpAddress[0], HostIpAddress[1],
				HostIpAddress[2], HostIpAddress[3]);
	uip_sethostaddr(ipaddr);

	uip_ipaddr(ipaddr, RoutIpAddress[0], RoutIpAddress[1],
				RoutIpAddress[2], RoutIpAddress[3]);
	uip_setdraddr(ipaddr);

	uip_ipaddr(ipaddr, NetMask[0], NetMask[1], NetMask[2], NetMask[3]);
	uip_setnetmask(ipaddr);
#endif
	uip_setethaddr(GMacAddress);
	_app_init();

	while (1) {
		uip_len = gmac_tapdev_read();

		if (uip_len > 0) {
			if (BUF->type == htons(UIP_ETHTYPE_IP)) {
				uip_arp_ipin();
				uip_input();

				/* If the above function invocation resulted in data that
					should be sent out on the network, the global variable
					uip_len is set to a value > 0. */
//.........这里部分代码省略.........

/* MPU configuration. */
void BOARD_ConfigMPU(void)
{
    /* Disable I cache and D cache */
    if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) {
        SCB_DisableICache();
    }
    if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) {
        SCB_DisableDCache();
    }

    /* Disable MPU */
    ARM_MPU_Disable();

    /* MPU configure:
     * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
     * API in core_cm7.h.
     * param DisableExec       Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled.
     * param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
     *      Use MACROS defined in core_cm7.h: ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
     * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
     *  TypeExtField  IsShareable  IsCacheable  IsBufferable   Memory Attribtue    Shareability        Cache
     *     0             x           0           0             Strongly Ordered    shareable
     *     0             x           0           1              Device             shareable
     *     0             0           1           0              Normal             not shareable   Outer and inner write through no write allocate
     *     0             0           1           1              Normal             not shareable   Outer and inner write back no write allocate
     *     0             1           1           0              Normal             shareable       Outer and inner write through no write allocate
     *     0             1           1           1              Normal             shareable       Outer and inner write back no write allocate
     *     1             0           0           0              Normal             not shareable   outer and inner noncache
     *     1             1           0           0              Normal             shareable       outer and inner noncache
     *     1             0           1           1              Normal             not shareable   outer and inner write back write/read acllocate
     *     1             1           1           1              Normal             shareable       outer and inner write back write/read acllocate
     *     2             x           0           0              Device              not shareable
     *  Above are normal use settings, if your want to see more details or want to config different inner/outter cache policy.
     *  please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
     * param SubRegionDisable  Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
     * param Size              Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in core_cm7.h.
     */

    /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
    MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);

    /* Region 1 setting: Memory with Device type, not shareable,  non-cacheable. */
    MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);

    /* Region 2 setting */
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
    /* Setting Memory with Normal type, not shareable, outer/inner write back. */
    MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512MB);
#else
    /* Setting Memory with Device type, not shareable, non-cacheable. */
    MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
#endif

    /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
    MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);

    /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
    MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);

    /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
    MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);

    /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
    MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);

    /* The define sets the cacheable memory to shareable,
     * this suggestion is referred from chapter 2.2.1 Memory regions,
     * types and attributes in Cortex-M7 Devices, Generic User Guide */
#if defined(SDRAM_IS_SHAREABLE)
    /* Region 7 setting: Memory with Normal type, shareable, outer/inner write back, write/read allocate */
    MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
#else
    /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back, write/read allocate */
    MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
#endif

    /* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
     * accessed by cache can be put here */
    /* Memory with Normal type, not shareable, non-cacheable */
    MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);

    /* Enable MPU */
    ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);

    /* Enable I cache and D cache */
    SCB_EnableDCache();
    SCB_EnableICache();
}