本文整理汇总了C++中RShiftU64函数的典型用法代码示例。如果您正苦于以下问题:C++ RShiftU64函数的具体用法?C++ RShiftU64怎么用?C++ RShiftU64使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了RShiftU64函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: Power2MaxMemory
UINT64
Power2MaxMemory (
IN UINT64 MemoryLength
)
/*++
Routine Description:
TODO: Add function description
Arguments:
MemoryLength - TODO: add argument description
Returns:
TODO: add return values
--*/
{
UINT64 Result;
if (RShiftU64 (MemoryLength, 32)) {
Result = LShiftU64 ((UINT64) SetPower2 ((UINT32) RShiftU64 (MemoryLength, 32)), 32);
} else {
Result = (UINT64) SetPower2 ((UINT32) MemoryLength);
}
return Result;
}
示例2: ConfigureRootPortForPcieNand
/**
Configure RootPort for downstream PCIe NAND devices.
@param[in] RpBase - PCIe configuration space address of this RootPort
@param[in] BusNumber - Bus number
@param[in] MemoryBase - Memory base address
@param[in] MemoryLength - Memory size
**/
VOID
ConfigureRootPortForPcieNand (
IN UINTN RpBase,
IN UINTN BusNumber,
IN UINT32 MemoryBase,
IN UINT32 MemoryLength
)
{
UINT32 MemoryLimit;
DEBUG ((DEBUG_INFO, "ConfigureRootPortForPcieNand, BusNumber: %x, MemoryBase: %x, MemoryLength: %x\n",
BusNumber, MemoryBase, MemoryLength));
if (MemoryLength == 0) {
MemoryLimit = MemoryBase;
} else {
MemoryLimit = MemoryBase + MemoryLength + 0xFFFFF; // 1M
}
///
/// Configue PCIE configuration space for RootPort
///
PciWrite8 (RpBase + NVME_PCIE_BNUM + 1, (UINT8) BusNumber); // Secondary Bus Number registers
PciWrite8 (RpBase + NVME_PCIE_BNUM + 2, (UINT8) BusNumber); // Subordinate Bus Number registers
PciWrite8 (RpBase + NVME_PCIE_IOBL, 0xFF); // I/O Base registers
PciWrite8 (RpBase + NVME_PCIE_IOBL + 1, 0x00); // I/O Limit registers
PciWrite16 (RpBase + NVME_PCIE_MBL, (UINT16) RShiftU64 ((UINTN)MemoryBase, 16)); // Memory Base register
PciWrite16 (RpBase + NVME_PCIE_MBL + 2, (UINT16) RShiftU64 ((UINTN)MemoryLimit, 16)); // Memory Limit register
PciWrite16 (RpBase + NVME_PCIE_PMBL, 0xFFFF); // Prefetchable Memory Base registers
PciWrite16 (RpBase + NVME_PCIE_PMBL + 2, 0x0000); // Prefetchable Memory Limit registers
PciWrite32 (RpBase + NVME_PCIE_PMBU32, 0xFFFFFFFF); // Prefetchable Memory Upper Base registers
PciWrite32 (RpBase + NVME_PCIE_PMLU32, 0x00000000); // Prefetchable Memory Upper Limit registers
}
示例3: SetCacheability
/**
Set memory cache ability.
@param PageTable PageTable Address
@param Address Memory Address to change cache ability
@param Cacheability Cache ability to set
**/
VOID
SetCacheability (
IN UINT64 *PageTable,
IN UINTN Address,
IN UINT8 Cacheability
)
{
UINTN PTIndex;
VOID *NewPageTableAddress;
UINT64 *NewPageTable;
UINTN Index;
ASSERT ((Address & EFI_PAGE_MASK) == 0);
if (sizeof (UINTN) == sizeof (UINT64)) {
PTIndex = (UINTN)RShiftU64 (Address, 39) & 0x1ff;
ASSERT (PageTable[PTIndex] & IA32_PG_P);
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask);
}
PTIndex = (UINTN)RShiftU64 (Address, 30) & 0x1ff;
ASSERT (PageTable[PTIndex] & IA32_PG_P);
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask);
//
// A perfect implementation should check the original cacheability with the
// one being set, and break a 2M page entry into pieces only when they
// disagreed.
//
PTIndex = (UINTN)RShiftU64 (Address, 21) & 0x1ff;
if ((PageTable[PTIndex] & IA32_PG_PS) != 0) {
//
// Allocate a page from SMRAM
//
NewPageTableAddress = AllocatePages (1);
ASSERT (NewPageTableAddress != NULL);
NewPageTable = (UINT64 *)NewPageTableAddress;
for (Index = 0; Index < 0x200; Index++) {
NewPageTable[Index] = PageTable[PTIndex];
if ((NewPageTable[Index] & IA32_PG_PAT_2M) != 0) {
NewPageTable[Index] &= ~((UINT64)IA32_PG_PAT_2M);
NewPageTable[Index] |= (UINT64)IA32_PG_PAT_4K;
}
NewPageTable[Index] |= (UINT64)(Index << EFI_PAGE_SHIFT);
}
PageTable[PTIndex] = ((UINTN)NewPageTableAddress & gPhyMask) | IA32_PG_P;
}
ASSERT (PageTable[PTIndex] & IA32_PG_P);
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask);
PTIndex = (UINTN)RShiftU64 (Address, 12) & 0x1ff;
ASSERT (PageTable[PTIndex] & IA32_PG_P);
PageTable[PTIndex] &= ~((UINT64)((IA32_PG_PAT_4K | IA32_PG_CD | IA32_PG_WT)));
PageTable[PTIndex] |= (UINT64)Cacheability;
}
示例4: PostPmInitCallBack
EFI_STATUS
EFIAPI
PostPmInitCallBack (
IN EFI_EVENT Event,
IN VOID *Context
)
{
UINT64 OriginalGTTMMADR;
UINT32 LoGTBaseAddress;
UINT32 HiGTBaseAddress;
//
// Enable Bus Master, I/O and Memory access on 0:2:0
//
PciOr8 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_CMD), (BIT2 | BIT1));
//
// only 32bit read/write is legal for device 0:2:0
//
OriginalGTTMMADR = (UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR));
OriginalGTTMMADR = LShiftU64 ((UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR + 4)), 32) | (OriginalGTTMMADR);
//
// 64bit GTTMADR does not work for S3 save script table since it is executed in PEIM phase
// Program temporarily 32bits GTTMMADR for POST and S3 resume
//
LoGTBaseAddress = (UINT32) (GTTMMADR & 0xFFFFFFFF);
HiGTBaseAddress = (UINT32) RShiftU64 ((GTTMMADR & 0xFFFFFFFF00000000), 32);
S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);
S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);
//
// Restore original GTTMMADR
//
LoGTBaseAddress = (UINT32) (OriginalGTTMMADR & 0xFFFFFFFF);
HiGTBaseAddress = (UINT32) RShiftU64 ((OriginalGTTMMADR & 0xFFFFFFFF00000000), 32);
S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);
S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);
//
// Lock the following registers, GGC, BDSM, BGSM
//
PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_MGGC_OFFSET), LockBit);
PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_BSM_OFFSET), LockBit);
PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_BGSM), LockBit);
gBS->CloseEvent (Event);
//
// Return final status
//
return EFI_SUCCESS;
}
示例5: MonotonicCounterDriverGetNextHighMonotonicCount
EFI_RUNTIMESERVICE
EFI_STATUS
EFIAPI
MonotonicCounterDriverGetNextHighMonotonicCount (
OUT UINT32 *HighCount
)
/*++
Routine Description:
Arguments:
Returns:
--*/
{
EFI_STATUS Status;
EFI_TPL OldTpl;
//
// Check input parameters
//
if (HighCount == NULL) {
return EFI_INVALID_PARAMETER;
}
if (!mEfiAtRuntime) {
//
// Use a lock if called before ExitBootServices()
//
OldTpl = gBS->RaiseTPL (EFI_TPL_HIGH_LEVEL);
*HighCount = (UINT32) RShiftU64 (mEfiMtc, 32) + 1;
mEfiMtc = LShiftU64 (*HighCount, 32);
gBS->RestoreTPL (OldTpl);
} else {
*HighCount = (UINT32) RShiftU64 (mEfiMtc, 32) + 1;
mEfiMtc = LShiftU64 (*HighCount, 32);
}
//
// Update the NvRam store to match the new high part
//
Status = gRT->SetVariable (
mEfiMtcName,
&mEfiMtcGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_BOOTSERVICE_ACCESS,
sizeof (UINT32),
HighCount
);
return Status;
}
示例6: LogMemorySmbiosRecord
/**
This is the standard EFI driver point that detects whether there is a
MemoryConfigurationData Variable and, if so, reports memory configuration info
to the DataHub.
@param ImageHandle Handle for the image of this driver
@param SystemTable Pointer to the EFI System Table
@return EFI_SUCCESS if the data is successfully reported
@return EFI_NOT_FOUND if the HOB list could not be located.
**/
EFI_STATUS
LogMemorySmbiosRecord (
VOID
)
{
EFI_STATUS Status;
UINT64 TotalMemorySize;
UINT8 NumSlots;
SMBIOS_TABLE_TYPE19 *Type19Record;
EFI_SMBIOS_HANDLE MemArrayMappedAddrSmbiosHandle;
EFI_SMBIOS_PROTOCOL *Smbios;
CHAR16 *MemString;
Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID**)&Smbios);
ASSERT_EFI_ERROR (Status);
NumSlots = 1;
//
// Process Memory String in form size!size ...
// So 64!64 is 128 MB
//
MemString = (CHAR16 *)PcdGetPtr (PcdEmuMemorySize);
for (TotalMemorySize = 0; *MemString != '\0';) {
TotalMemorySize += StrDecimalToUint64 (MemString);
while (*MemString != '\0') {
if (*MemString == '!') {
MemString++;
break;
}
MemString++;
}
}
//
// Convert Total Memory Size to based on KiloByte
//
TotalMemorySize = LShiftU64 (TotalMemorySize, 20);
//
// Generate Memory Array Mapped Address info
//
Type19Record = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE19) + 2);
Type19Record->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS;
Type19Record->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE19);
Type19Record->Hdr.Handle = 0;
Type19Record->StartingAddress = 0;
Type19Record->EndingAddress = (UINT32)RShiftU64(TotalMemorySize, 10) - 1;
Type19Record->MemoryArrayHandle = 0;
Type19Record->PartitionWidth = (UINT8)(NumSlots);
//
// Generate Memory Array Mapped Address info (TYPE 19)
//
Status = AddSmbiosRecord (Smbios, &MemArrayMappedAddrSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type19Record);
FreePool(Type19Record);
ASSERT_EFI_ERROR (Status);
return Status;
}
示例7: InitHostVmcs
/**
This function initialize host VMCS.
**/
VOID
InitHostVmcs (
UINTN Index
)
{
UINT64 Data64;
UINTN Size;
//
// VMCS size
//
Data64 = AsmReadMsr64 (IA32_VMX_BASIC_MSR_INDEX);
Size = (UINTN)(RShiftU64 (Data64, 32) & 0xFFFF);
//
// Allocate
//
mHostContextCommon.HostContextPerCpu[Index].Vmcs = (UINT64)(UINTN)AllocatePages (FRM_SIZE_TO_PAGES(Size));
//
// Set RevisionIdentifier
//
*(UINT32 *)(UINTN)mHostContextCommon.HostContextPerCpu[Index].Vmcs = (UINT32)Data64;
return ;
}
示例8: EfiSizeToPages
/**
Converts a size, in bytes, to a number of EFI_PAGESs.
NOTE: Do not use EFI_SIZE_TO_PAGES because it handles UINTN only.
@param Size A size in bytes.
@return The number of EFI_PAGESs associated with the number of bytes specified
by Size.
**/
STATIC
UINT64
EfiSizeToPages (
IN UINT64 Size
)
{
return RShiftU64 (Size, EFI_PAGE_SHIFT) + ((((UINTN)Size) & EFI_PAGE_MASK) ? 1 : 0);
}
示例9: Stall
EFI_STATUS
EFIAPI
Stall (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_STALL_PPI *This,
IN UINTN Microseconds
)
{
UINTN Ticks;
UINTN Counts;
UINT32 CurrentTick;
UINT32 OriginalTick;
UINT32 RemainingTick;
if (Microseconds == 0) {
return EFI_SUCCESS;
}
OriginalTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR);
OriginalTick &= (V_PCH_ACPI_PM1_TMR_MAX_VAL - 1);
CurrentTick = OriginalTick;
//
// The timer frequency is 3.579545MHz, so 1 ms corresponds to 3.58 clocks
//
Ticks = Microseconds * 358 / 100 + OriginalTick + 1;
//
// The loops needed for timer overflow
//
Counts = (UINTN)RShiftU64((UINT64)Ticks, 24);
//
// Remaining clocks within one loop
//
RemainingTick = Ticks & 0xFFFFFF;
//
// Do not intend to use TMROF_STS bit of register PM1_STS, because this add extra
// one I/O operation, and may generate SMI
//
while (Counts != 0) {
CurrentTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR) & B_PCH_ACPI_PM1_TMR_VAL;
if (CurrentTick <= OriginalTick) {
Counts--;
}
OriginalTick = CurrentTick;
}
while ((RemainingTick > CurrentTick) && (OriginalTick <= CurrentTick)) {
OriginalTick = CurrentTick;
CurrentTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR) & B_PCH_ACPI_PM1_TMR_VAL;
}
return EFI_SUCCESS;
}
示例10: REGISTER
/**
Get the PCI-E Address from a PCI address format 0x0000ssbbddffrrr
where ss is SEGMENT, bb is BUS, dd is DEVICE, ff is FUNCTION
and rrr is REGISTER (extension format for PCI-E).
@param[in] InputAddress PCI address format on input.
@param[out]PciEAddress PCI-E address extention format.
**/
VOID
EFIAPI
GetPciEAddressFromInputAddress (
IN UINT64 InputAddress,
OUT UINT64 *PciEAddress
)
{
*PciEAddress = RShiftU64(InputAddress & ~(UINT64) 0xFFF, 4);
*PciEAddress += LShiftU64((UINT16) InputAddress & 0x0FFF, 32);
}
示例11: Power2MaxMemory
/**
Calculate the maximum value which is a power of 2, but less the MemoryLength.
@param MemoryLength The number to pass in.
@return The maximum value which is align to power of 2 and less the MemoryLength
**/
UINT64
Power2MaxMemory (
IN UINT64 MemoryLength
)
{
UINT64 Result;
if (RShiftU64 (MemoryLength, 32) != 0) {
Result = LShiftU64 (
(UINT64) GetPowerOfTwo32 (
(UINT32) RShiftU64 (MemoryLength, 32)
),
32
);
} else {
Result = (UINT64) GetPowerOfTwo32 ((UINT32) MemoryLength);
}
return Result;
}
示例12: WaitForTick
/**
Internal worker function to call the Metronome Architectural Protocol for
the number of ticks specified by the UINT64 Counter value. WaitForTick()
service of the Metronome Architectural Protocol uses a UINT32 for the number
of ticks to wait, so this function loops when Counter is larger than 0xffffffff.
@param Counter Number of ticks to wait.
**/
VOID
CoreInternalWaitForTick (
IN UINT64 Counter
)
{
while (RShiftU64 (Counter, 32) > 0) {
gMetronome->WaitForTick (gMetronome, 0xffffffff);
Counter -= 0xffffffff;
}
gMetronome->WaitForTick (gMetronome, (UINT32)Counter);
}
示例13: GetCurrentMicrocodeSignature
/**
Get microcode update signature of currently loaded microcode update.
@return Microcode signature.
**/
UINT32
GetCurrentMicrocodeSignature (
VOID
)
{
UINT64 Signature;
AsmWriteMsr64 (EFI_MSR_IA32_BIOS_SIGN_ID, 0);
AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL);
Signature = AsmReadMsr64 (EFI_MSR_IA32_BIOS_SIGN_ID);
return (UINT32) RShiftU64 (Signature, 32);
}
示例14: ASSERT
/**
Returns a bit field from a 64-bit value.
Returns the bitfield specified by the StartBit and the EndBit from Operand.
If 64-bit operations are not supported, then ASSERT().
If StartBit is greater than 63, then ASSERT().
If EndBit is greater than 63, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Operand Operand on which to perform the bitfield operation.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..63.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..63.
@return The bit field read.
**/
UINT64
EFIAPI
BitFieldRead64 (
IN UINT64 Operand,
IN UINTN StartBit,
IN UINTN EndBit
)
{
ASSERT (EndBit < sizeof (Operand) * 8);
ASSERT (StartBit <= EndBit);
return RShiftU64 (Operand & ~LShiftU64 ((UINT64)-2, EndBit), StartBit);
}
示例15: WriteDMAExt
/**
WRITE_DMA_EXT command
@param CardData Pointer to CARD_DATA.
@param LBA The starting logical block address to read from on the device.
@param Buffer A pointer to the destination buffer for the data. The caller
is responsible for either having implicit or explicit ownership
of the buffer.
@param SectorCount Size in 512 bytes unit.
@retval EFI_SUCCESS Success
@retval EFI_DEVICE_ERROR Hardware Error
@retval EFI_INVALID_PARAMETER Parameter is error
@retval EFI_NO_MEDIA No media
@retval EFI_MEDIA_CHANGED Media Change
@retval EFI_BAD_BUFFER_SIZE Buffer size is bad
**/
EFI_STATUS
WriteDMAExt (
IN CARD_DATA *CardData,
IN EFI_LBA LBA,
IN UINT8 *Buffer,
IN UINT16 SectorCount
)
{
EFI_STATUS Status;
ZeroMem (&CardData->TaskFile, sizeof (TASK_FILE));
//
//The host only supports nIEN = 0
//
CardData->TaskFile.Command_Status = WRITE_DMA_EXT;
CardData->TaskFile.SectorCount = (UINT8)SectorCount;
CardData->TaskFile.SectorCount_Exp = (UINT8)(SectorCount >> 8);
CardData->TaskFile.LBALow = (UINT8)LBA;
CardData->TaskFile.LBAMid = (UINT8)RShiftU64(LBA, 8);
CardData->TaskFile.LBAHigh = (UINT8)RShiftU64(LBA, 16);
CardData->TaskFile.LBALow_Exp = (UINT8)RShiftU64(LBA, 24);
CardData->TaskFile.LBAMid_Exp = (UINT8)RShiftU64(LBA, 32);
CardData->TaskFile.LBAHigh_Exp = (UINT8)RShiftU64(LBA, 40);
Status = SendATACommand (
CardData,
&CardData->TaskFile,
TRUE,
Buffer,
SectorCount
);
return Status;
}