本文整理汇总了C++中REG_RD函数的典型用法代码示例。如果您正苦于以下问题:C++ REG_RD函数的具体用法?C++ REG_RD怎么用?C++ REG_RD使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了REG_RD函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: _scale_isr_root
static irqreturn_t _scale_isr_root(int irq, void *dev_id)
{
uint32_t status;
struct scale_frame frame;
uint32_t flag;
(void)irq; (void)dev_id;
status = REG_RD(SCALE_INT_STS);
if (unlikely(0 == (status & SCALE_IRQ_BIT))) {
return IRQ_HANDLED;
}
SCALE_TRACE("SCALE DRV: _scale_isr_root \n");
spin_lock_irqsave(&scale_lock, flag);
if (g_path->user_func) {
frame.yaddr = g_path->output_addr.yaddr;
frame.uaddr = g_path->output_addr.uaddr;
frame.vaddr = g_path->output_addr.vaddr;
frame.width = g_path->output_size.w;
if (SCALE_MODE_SLICE == g_path->scale_mode) {
frame.height = g_path->slice_out_height;
g_path->slice_out_height = REG_RD(SCALE_SLICE_VER);
g_path->slice_out_height = (g_path->slice_out_height >> 16) & 0xFFF;
frame.height = g_path->slice_out_height - frame.height;
} else {
示例2: epd_enable
void epd_enable(void)
{
char temp = TEMP_USE_DEFAULT;
debug("epd_enable\n");
//epdc_power_on();
/* Draw data to display */
//draw_mode0();
/* Enable clock gating (clear to enable) */
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
while (REG_RD(EPDC_BASE, EPDC_CTRL) &
(EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
;
REG_WR(EPDC_BASE, EPDC_TEMP, TEMP_USE_DEFAULT);
temp = read_temperature();
// temp = do_read_temperature_via_i2c();
temp_set_index(temp);
/* Set Waveform Bufferr register to real waveform address */
REG_WR(EPDC_BASE, EPDC_WVADDR, panel_info.epdc_data.waveform_buf_addr);
debug("epdc_irq's value %08x\nEPDC_IRQ_CLR's value %08x\n",REG_RD(EPDC_BASE, EPDC_IRQ), REG_RD(EPDC_BASE, EPDC_IRQ_CLR));
debug("EPDC LUT STATUS %08x\n",REG_RD(EPDC_BASE,EPDC_STATUS_LUTS));
draw_splash_screen();
debug("epdc_irq's value %08x\nEPDC_IRQ_CLR's value %08x\n",REG_RD(EPDC_BASE, EPDC_IRQ), REG_RD(EPDC_BASE, EPDC_IRQ_CLR));
debug("EPDC LUT STATUS %08x\n",REG_RD(EPDC_BASE,EPDC_STATUS_LUTS));
}
示例3: scale_continue
int32_t scale_continue(void)
{
enum scale_drv_rtn rtn = SCALE_RTN_SUCCESS;
uint32_t slice_h = g_path->slice_height;
SCALE_TRACE("SCALE DRV: continue %d, %d, %d \n",
g_path->slice_height, g_path->slice_in_height, g_path->scale_mode);
if (SCALE_MODE_SLICE == g_path->scale_mode) {
if (g_path->slice_in_height + g_path->slice_height >= g_path->input_rect.h) {
slice_h = g_path->input_rect.h - g_path->slice_in_height;
g_path->is_last_slice = 1;
REG_MWR(SCALE_SLICE_VER, 0x3FF, slice_h);
REG_OWR(SCALE_SLICE_VER, (1 << 12));
SCALE_TRACE("SCALE DRV: continue, last slice, 0x%x \n", REG_RD(SCALE_SLICE_VER));
} else {
g_path->is_last_slice = 0;
REG_MWR(SCALE_SLICE_VER, (1 << 12), (0 << 12));
}
g_path->slice_in_height += g_path->slice_height;
}
REG_WR(SCALE_FRM_SWAP_Y, g_path->temp_buf_addr.yaddr);
REG_WR(SCALE_FRM_SWAP_U, g_path->temp_buf_addr.uaddr);
REG_WR(SCALE_FRM_LINE, g_path->temp_buf_addr.vaddr);
_scale_reg_trace();
REG_OWR(SCALE_CFG, 1);
atomic_inc(&g_path->start_flag);
SCALE_TRACE("SCALE DRV: continue %x.\n", REG_RD(SCALE_CFG));
return rtn;
}
示例4: sunxi_gpio_do_tasklet
/*
void sunxi_gpio_do_tasklet(unsigned long data)
{
printk("this is irp donw dispuse !\n");
}
DECLARE_TASKLET(sunxi_tasklet,sunxi_gpio_do_tasklet,0);
*/
irqreturn_t sunxi_interrupt(int irq,void *dev_id)
{
unsigned int PIC, PIS,tmp;
int i = 0;
PIC = REG_RD(GPIO_TEST_BASE + 0x210 ) ;
PIS = REG_RD(GPIO_TEST_BASE + 0x214 ) ;
tmp = PIS;
while(tmp) {
if(tmp & 0x1) {
/*if (tmp & 0x1) is true, the i represent NO.i EINT interrupt take place.
you can through the value of i to decide to do what*/
printk("this is NO.%d gpio INT \n",i);
}
tmp >>= 1;
i++;
}
GPIO_SW_DEBUG("0 PIC is %x \n PIS is %x \n",PIC,PIS);
__raw_writel(PIS, GPIO_TEST_BASE + 0x214);
GPIO_SW_DEBUG("1 PIC is %x \n PIS is %x \n",PIC,PIS);
/*this is a interface to connect interrupt top half and bottom half,if want to use bottom half,you can open fanctions sunxi_gpio_do_tasklet and tasklet_schedule*/
/*
tasklet_schedule(&sunxi_tasklet);
*/
return IRQ_HANDLED;
}
示例5: console_write_direct
static void
console_write_direct(struct console *co, const char *buf, unsigned int len)
{
int i;
reg_ser_r_stat_din stat;
reg_ser_rw_tr_dma_en tr_dma_en, old;
/* Switch to manual mode */
tr_dma_en = old = REG_RD (ser, port->instance, rw_tr_dma_en);
if (tr_dma_en.en == regk_ser_yes) {
tr_dma_en.en = regk_ser_no;
REG_WR(ser, port->instance, rw_tr_dma_en, tr_dma_en);
}
/* Send data */
for (i = 0; i < len; i++) {
/* LF -> CRLF */
if (buf[i] == '\n') {
do {
stat = REG_RD (ser, port->instance, r_stat_din);
} while (!stat.tr_rdy);
REG_WR_INT (ser, port->instance, rw_dout, '\r');
}
/* Wait until transmitter is ready and send.*/
do {
stat = REG_RD (ser, port->instance, r_stat_din);
} while (!stat.tr_rdy);
REG_WR_INT (ser, port->instance, rw_dout, buf[i]);
}
/* Restore mode */
if (tr_dma_en.en != old.en)
REG_WR(ser, port->instance, rw_tr_dma_en, old);
}
示例6: start_timer_trig
/* Called with ints off */
inline void start_timer_trig(unsigned long delay_us)
{
reg_timer_rw_ack_intr ack_intr = { 0 };
reg_timer_rw_intr_mask intr_mask;
reg_timer_rw_trig trig;
reg_timer_rw_trig_cfg trig_cfg = { 0 };
reg_timer_r_time r_time0;
reg_timer_r_time r_time1;
unsigned char trig_wrap;
unsigned char time_wrap;
r_time0 = REG_RD(timer, regi_timer0, r_time);
D1(printk("start_timer_trig : %d us freq: %i div: %i\n",
delay_us, freq_index, div));
/* Clear trig irq */
intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask);
intr_mask.trig = 0;
REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask);
/* Set timer values and check if trigger wraps. */
/* r_time is 100MHz (10 ns resolution) */
trig_wrap = (trig = r_time0 + delay_us*(1000/10)) < r_time0;
timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = trig;
timer_delay_settings[fast_timers_started % NUM_TIMER_STATS] = delay_us;
/* Ack interrupt */
ack_intr.trig = 1;
REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr);
/* Start timer */
REG_WR(timer, regi_timer0, rw_trig, trig);
trig_cfg.tmr = regk_timer_time;
REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg);
/* Check if we have already passed the trig time */
r_time1 = REG_RD(timer, regi_timer0, r_time);
time_wrap = r_time1 < r_time0;
if ((trig_wrap && !time_wrap) || (r_time1 < trig)) {
/* No, Enable trig irq */
intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask);
intr_mask.trig = 1;
REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask);
fast_timers_started++;
fast_timer_running = 1;
} else {
/* We have passed the time, disable trig point, ack intr */
trig_cfg.tmr = regk_timer_off;
REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg);
REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr);
/* call the int routine */
INIT_WORK(&fast_work, timer_trig_handler);
schedule_work(&fast_work);
}
}
示例7: epdc_ctrl_init
int epdc_ctrl_init(void *lcdbase)
{
/*
* We rely on lcdbase being a physical address, i.e., either MMU off,
* or 1-to-1 mapping. Might want to add some virt2phys here.
*/
if (!lcdbase)
return -1;
eink_color_fg = 0xFF;
eink_color_bg = 0xFF;
/* Reset */
REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
while (!(REG_RD(EPDC_BASE, EPDC_CTRL) & EPDC_CTRL_CLKGATE))
;
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
/* Enable clock gating (clear to enable) */
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
while (REG_RD(EPDC_BASE, EPDC_CTRL) &
(EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
;
debug("resolution %dx%d, bpp %d\n", (int)panel_info.vl_col,
(int)panel_info.vl_row, NBITS(panel_info.vl_bpix));
/* Set framebuffer pointer */
REG_WR(EPDC_BASE, EPDC_UPD_ADDR, (u32)lcdbase);
#if 0
/* Set Working Buffer pointer */
REG_WR(EPDC_BASE, EPDC_WB_ADDR, panel_info.epdc_data.working_buf_addr);
/* Set Waveform Buffer pointer */
REG_WR(EPDC_BASE, EPDC_WVADDR, panel_info.epdc_data.waveform_buf_addr);
#endif
/* Set waveform and working buffer, they will be changed later */
REG_WR(EPDC_BASE, EPDC_WVADDR, (unsigned long)CONFIG_TEMP_INIT_WAVEFORM_ADDR);
REG_WR(EPDC_BASE, EPDC_WB_ADDR, (unsigned long)CONFIG_WORKING_BUF_ADDR);
#if 0
/* Get waveform data address and offset */
int data_offs = setup_waveform_file();
if(data_offs == -1) {
printf("Can't load waveform data!\n");
return -1;
}
#endif
/* Initialize EPDC, passing pointer to EPDC registers */
epdc_init_settings();
epdc_initialized = 1;
return;
}
示例8: serial_getc
/* Receive character */
int serial_getc(void)
{
/* Wait while TX FIFO is empty */
while (REG_RD(DBGUART_BASE + UARTDBGFR) & RXFE)
;
/* Read data byte */
return REG_RD(DBGUART_BASE + UARTDBGDR) & 0xff;
}
示例9: start_timer_trig
/* Called with ints off */
void __INLINE__ start_timer_trig(unsigned long delay_us)
{
reg_timer_rw_ack_intr ack_intr = { 0 };
reg_timer_rw_intr_mask intr_mask;
reg_timer_rw_trig trig;
reg_timer_rw_trig_cfg trig_cfg = { 0 };
reg_timer_r_time r_time;
r_time = REG_RD(timer, regi_timer, r_time);
D1(printk("start_timer_trig : %d us freq: %i div: %i\n",
delay_us, freq_index, div));
/* Clear trig irq */
intr_mask = REG_RD(timer, regi_timer, rw_intr_mask);
intr_mask.trig = 0;
REG_WR(timer, regi_timer, rw_intr_mask, intr_mask);
/* Set timer values */
/* r_time is 100MHz (10 ns resolution) */
trig = r_time + delay_us*(1000/10);
timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = trig;
timer_delay_settings[fast_timers_started % NUM_TIMER_STATS] = delay_us;
/* Ack interrupt */
ack_intr.trig = 1;
REG_WR(timer, regi_timer, rw_ack_intr, ack_intr);
/* Start timer */
REG_WR(timer, regi_timer, rw_trig, trig);
trig_cfg.tmr = regk_timer_time;
REG_WR(timer, regi_timer, rw_trig_cfg, trig_cfg);
/* Check if we have already passed the trig time */
r_time = REG_RD(timer, regi_timer, r_time);
if (r_time < trig) {
/* No, Enable trig irq */
intr_mask = REG_RD(timer, regi_timer, rw_intr_mask);
intr_mask.trig = 1;
REG_WR(timer, regi_timer, rw_intr_mask, intr_mask);
fast_timers_started++;
fast_timer_running = 1;
}
else
{
/* We have passed the time, disable trig point, ack intr */
trig_cfg.tmr = regk_timer_off;
REG_WR(timer, regi_timer, rw_trig_cfg, trig_cfg);
REG_WR(timer, regi_timer, rw_ack_intr, ack_intr);
/* call the int routine directly */
timer_trig_handler();
}
}
示例10: ecore_map_q_cos
/* Maps the specified queue to the specified COS */
void ecore_map_q_cos(struct _lm_device_t *pdev, u32_t q_num, u32_t new_cos)
{
/* find current COS mapping */
u32_t curr_cos = REG_RD(pdev, QM_REG_QVOQIDX_0 + q_num * 4);
/* check if queue->COS mapping has changed */
if (curr_cos != new_cos) {
u32_t num_vnics = ECORE_PORT2_MODE_NUM_VNICS;
u32_t reg_addr, reg_bit_map, vnic;
/* update parameters for 4port mode */
if (INIT_MODE_FLAGS(pdev) & MODE_PORT4) {
num_vnics = ECORE_PORT4_MODE_NUM_VNICS;
if (PORT_ID(pdev)) {
curr_cos += ECORE_E3B0_PORT1_COS_OFFSET;
new_cos += ECORE_E3B0_PORT1_COS_OFFSET;
}
}
/* change queue mapping for each VNIC */
for (vnic = 0; vnic < num_vnics; vnic++) {
u32_t pf_q_num =
ECORE_PF_Q_NUM(q_num, PORT_ID(pdev), vnic);
u32_t q_bit_map = 1 << (pf_q_num & 0x1f);
/* overwrite queue->VOQ mapping */
REG_WR(pdev, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
/* clear queue bit from current COS bit map */
reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
reg_bit_map = REG_RD(pdev, reg_addr);
REG_WR(pdev, reg_addr, reg_bit_map & (~q_bit_map));
/* set queue bit in new COS bit map */
reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
reg_bit_map = REG_RD(pdev, reg_addr);
REG_WR(pdev, reg_addr, reg_bit_map | q_bit_map);
/* set/clear queue bit in command-queue bit map
(E2/E3A0 only, valid COS values are 0/1) */
if (!(INIT_MODE_FLAGS(pdev) & MODE_E3_B0)) {
reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num);
reg_bit_map = REG_RD(pdev, reg_addr);
q_bit_map = 1 << (2 * (pf_q_num & 0xf));
reg_bit_map = new_cos ?
(reg_bit_map | q_bit_map) :
(reg_bit_map & (~q_bit_map));
REG_WR(pdev, reg_addr, reg_bit_map);
}
}
}
}
示例11: etraxfs_uart_start_tx_bottom
static inline void etraxfs_uart_start_tx_bottom(struct uart_port *port)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
void __iomem *regi_ser = up->regi_ser;
reg_ser_rw_tr_ctrl tr_ctrl;
reg_ser_rw_intr_mask intr_mask;
tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl);
tr_ctrl.stop = regk_ser_no;
REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl);
intr_mask = REG_RD(ser, regi_ser, rw_intr_mask);
intr_mask.tr_rdy = regk_ser_yes;
REG_WR(ser, regi_ser, rw_intr_mask, intr_mask);
}
示例12: sync_serial_start_port
static void sync_serial_start_port(struct sync_port *port)
{
reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
reg_sser_rw_tr_cfg tr_cfg =
REG_RD(sser, port->regi_sser, rw_tr_cfg);
reg_sser_rw_rec_cfg rec_cfg =
REG_RD(sser, port->regi_sser, rw_rec_cfg);
cfg.en = regk_sser_yes;
tr_cfg.tr_en = regk_sser_yes;
rec_cfg.rec_en = regk_sser_yes;
REG_WR(sser, port->regi_sser, rw_cfg, cfg);
REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
port->started = 1;
}
示例13: lcd_ctrl_init
void lcd_ctrl_init(void *lcdbase)
{
/*
* We rely on lcdbase being a physical address, i.e., either MMU off,
* or 1-to-1 mapping. Might want to add some virt2phys here.
*/
if (!lcdbase)
return;
lcd_color_fg = 0xFF;
lcd_color_bg = 0xFF;
/* Reset */
REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
while (!(REG_RD(EPDC_BASE, EPDC_CTRL) & EPDC_CTRL_CLKGATE))
;
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
/* Enable clock gating (clear to enable) */
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
while (REG_RD(EPDC_BASE, EPDC_CTRL) &
(EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
;
debug("resolution %dx%d, bpp %d\n", (int)panel_info.vl_col,
(int)panel_info.vl_row, NBITS(panel_info.vl_bpix));
/* Set framebuffer pointer */
REG_WR(EPDC_BASE, EPDC_UPD_ADDR, (u32)lcdbase);
/* Set Working Buffer pointer */
REG_WR(EPDC_BASE, EPDC_WB_ADDR, panel_info.epdc_data.working_buf_addr);
/* Get waveform data address and offset */
if (setup_waveform_file()) {
printf("Can't load waveform data!\n");
return;
}
/* Set Waveform Buffer pointer */
REG_WR(EPDC_BASE, EPDC_WVADDR,
panel_info.epdc_data.waveform_buf_addr);
/* Initialize EPDC, passing pointer to EPDC registers */
epdc_init_settings();
return;
}
示例14: epdc_is_lut_active
static inline int epdc_is_lut_active(u32 lut_num)
{
u32 val = REG_RD(EPDC_BASE, EPDC_STATUS_LUTS);
int is_active = val & (1 << lut_num) ? TRUE : FALSE;
return is_active;
}
示例15: cris_timer_init
void __init
cris_timer_init(void)
{
int cpu = smp_processor_id();
reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
reg_timer_rw_intr_mask timer_intr_mask;
/* Setup the etrax timers
* Base frequency is 100MHz, divider 1000000 -> 100 HZ
* We use timer0, so timer1 is free.
* The trig timer is used by the fasttimer API if enabled.
*/
tmr0_ctrl.op = regk_timer_ld;
tmr0_ctrl.freq = regk_timer_f100;
REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
tmr0_ctrl.op = regk_timer_run;
REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
/* enable the timer irq */
timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
timer_intr_mask.tmr0 = 1;
REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
}