本文整理汇总了C++中REG函数的典型用法代码示例。如果您正苦于以下问题：C++ REG函数的具体用法？C++ REG怎么用？C++ REG使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了REG函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: analop_esil
//.........这里部分代码省略.........
break;
case MIPS_INS_BGEZALC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_ND ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGTZALC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,%s,==,$z,?{,BREAK,},", ARG(0));
r_strbuf_appendf (&op->esil, "0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_ND ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BLTZAL:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",1,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_CALL_D ("%s")",}", ARG(0), ARG(1));
break;
case MIPS_INS_BLTZ:
case MIPS_INS_BLTZC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",1,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J ("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BGTZ:
case MIPS_INS_BGTZC:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,%s,==,$z,?{,BREAK,},", ARG (0));
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,"ES_IS_NEGATIVE ("%s")",==,$z,?{,"ES_J("%s")",}",
ARG (0), ARG (1));
break;
case MIPS_INS_BTEQZ:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,t,==,$z,?{,"ES_J ("%s")",}", ARG (0));
break;
case MIPS_INS_BTNEZ:
r_strbuf_appendf (&op->esil, ES_TRAP_DS () ",0,t,==,$z,!,?{,"ES_J ("%s")",}", ARG (0));
break;
case MIPS_INS_MOV:
case MIPS_INS_MOVE:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "%s,%s,=", ARG (1), REG (0));
}
break;
case MIPS_INS_MOVZ:
case MIPS_INS_MOVF:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "0,%s,==,$z,?{,%s,%s,=,}",
ARG (2), ARG (1), REG (0));
}
break;
case MIPS_INS_MOVT:
PROTECT_ZERO () {
r_strbuf_appendf (&op->esil, "1,%s,==,$z,?{,%s,%s,=,}",
ARG (2), ARG (1), REG (0));
}
break;
case MIPS_INS_FSUB:
case MIPS_INS_SUB:
case MIPS_INS_SUBU:
case MIPS_INS_DSUB:
case MIPS_INS_DSUBU:
PROTECT_ZERO () {
r_strbuf_appendf(&op->esil, "%s,%s,-,%s,=",
ARG (2), ARG (1), ARG (0));
}
break;
case MIPS_INS_NEG:
case MIPS_INS_NEGU:
r_strbuf_appendf (&op->esil, "%s,0,-,%s,=,",
ARG (1), ARG (0));
break;
/** signed -- sets overflow flag */示例2: uart_init
/*---------------------------------------------------------------------------*/
void
uart_init(uint8_t uart)
{
const uart_regs_t *regs;
if(uart >= UART_INSTANCE_COUNT) {
return;
}
regs = &uart_regs[uart];
if(regs->rx.port < 0 || regs->tx.port < 0) {
return;
}
lpm_register_peripheral(permit_pm1);
/* Enable clock for the UART while Running, in Sleep and Deep Sleep */
REG(SYS_CTRL_RCGCUART) |= regs->sys_ctrl_rcgcuart_uart;
REG(SYS_CTRL_SCGCUART) |= regs->sys_ctrl_scgcuart_uart;
REG(SYS_CTRL_DCGCUART) |= regs->sys_ctrl_dcgcuart_uart;
/* Run on SYS_DIV */
REG(regs->base + UART_CC) = 0;
/*
* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
*
* The value to be written will be on of the IOC_INPUT_SEL_Pxn defines from
* ioc.h. The value can also be calculated as:
*
* (port << 3) + pin
*/
REG(regs->ioc_uartrxd_uart) = (regs->rx.port << 3) + regs->rx.pin;
/*
* Pad Control for the TX pin:
* - Set function to UARTn TX
* - Output Enable
*/
ioc_set_sel(regs->tx.port, regs->tx.pin, regs->ioc_pxx_sel_uart_txd);
ioc_set_over(regs->tx.port, regs->tx.pin, IOC_OVERRIDE_OE);
/* Set RX and TX pins to peripheral mode */
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->tx.port),
GPIO_PIN_MASK(regs->tx.pin));
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rx.port),
GPIO_PIN_MASK(regs->rx.pin));
/*
* UART Interrupt Masks:
* Acknowledge RX and RX Timeout
* Acknowledge Framing, Overrun and Break Errors
*/
REG(regs->base + UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
REG(regs->base + UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
REG(regs->base + UART_IFLS) =
UART_IFLS_RXIFLSEL_1_8 | UART_IFLS_TXIFLSEL_1_2;
/* Make sure the UART is disabled before trying to configure it */
REG(regs->base + UART_CTL) = UART_CTL_VALUE;
/* Baud Rate Generation */
REG(regs->base + UART_IBRD) = regs->ibrd;
REG(regs->base + UART_FBRD) = regs->fbrd;
/* UART Control: 8N1 with FIFOs */
REG(regs->base + UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
/*
* Enable hardware flow control (RTS/CTS) if requested.
* Note that hardware flow control is available only on UART1.
*/
if(regs->cts.port >= 0) {
REG(IOC_UARTCTS_UART1) = ioc_input_sel(regs->cts.port, regs->cts.pin);
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->cts.port), GPIO_PIN_MASK(regs->cts.pin));
ioc_set_over(regs->cts.port, regs->cts.pin, IOC_OVERRIDE_DIS);
REG(UART_1_BASE + UART_CTL) |= UART_CTL_CTSEN;
}
if(regs->rts.port >= 0) {
ioc_set_sel(regs->rts.port, regs->rts.pin, IOC_PXX_SEL_UART1_RTS);
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rts.port), GPIO_PIN_MASK(regs->rts.pin));
ioc_set_over(regs->rts.port, regs->rts.pin, IOC_OVERRIDE_OE);
REG(UART_1_BASE + UART_CTL) |= UART_CTL_RTSEN;
}
/* UART Enable */
REG(regs->base + UART_CTL) |= UART_CTL_UARTEN;
/* Enable UART0 Interrupts */
nvic_interrupt_enable(regs->nvic_int);
}示例3: analop_esil
static int analop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn) {
char str[32][32];
r_strbuf_init (&op->esil);
r_strbuf_set (&op->esil, "");
if (insn)
switch (insn->id) {
case MIPS_INS_NOP:
r_strbuf_setf (&op->esil, ",");
break;
case MIPS_INS_SW:
r_strbuf_appendf (&op->esil, "%s,%s,=[4]",
ARG(0), ARG(1));
break;
case MIPS_INS_SWC1:
case MIPS_INS_SWC2:
r_strbuf_setf (&op->esil, "%s,$", ARG(1));
break;
case MIPS_INS_SB:
r_strbuf_appendf (&op->esil, "%s,%s,=[1]",
ARG(0), ARG(1));
break;
case MIPS_INS_CMP:
case MIPS_INS_CMPU:
case MIPS_INS_CMPGU:
case MIPS_INS_CMPGDU:
case MIPS_INS_CMPI:
r_strbuf_appendf (&op->esil, "%s,%s,==", ARG(1), ARG(0));
break;
case MIPS_INS_SHRAV:
case MIPS_INS_SHRAV_R:
case MIPS_INS_SHRA:
case MIPS_INS_SHRA_R:
case MIPS_INS_SRA:
r_strbuf_appendf (&op->esil, "%s,%s,>>,31,%s,>>,?{,32,%s,-,%s,1,<<,1,-,<<,}{,0,},|,%s,=,",
ARG(2), ARG(1), ARG(1), ARG(2), ARG(2), ARG(0));
break;
case MIPS_INS_SHRL:
// suffix 'S' forces conditional flag to be updated
case MIPS_INS_SRLV:
case MIPS_INS_SRL:
r_strbuf_appendf (&op->esil, "%s,%s,>>,%s,=", ARG(2), ARG(1), ARG(0));
break;
case MIPS_INS_SLLV:
case MIPS_INS_SLL:
r_strbuf_appendf (&op->esil, "%s,%s,<<,%s,=", ARG(2), ARG(1), ARG(0));
break;
case MIPS_INS_BAL:
case MIPS_INS_JAL:
case MIPS_INS_JALR:
case MIPS_INS_JALRS:
case MIPS_INS_JALRC:
case MIPS_INS_BLTZAL: // Branch on less than zero and link
r_strbuf_appendf (&op->esil, "pc,8,+,ra,=,%s,pc,=", ARG(0));
break;
case MIPS_INS_JRADDIUSP:
// increment stackpointer in X and jump to %ra
r_strbuf_appendf (&op->esil, "%d,sp,+=,ra,pc,=", ARG(0));
break;
case MIPS_INS_JR:
case MIPS_INS_JRC:
case MIPS_INS_J:
// jump to address with conditional
r_strbuf_appendf (&op->esil, "%s,pc,=", ARG(0));
break;
case MIPS_INS_B: // ???
case MIPS_INS_BZ:
case MIPS_INS_BGTZ:
case MIPS_INS_BGTZC:
case MIPS_INS_BGTZALC:
case MIPS_INS_BGEZ:
case MIPS_INS_BGEZC:
case MIPS_INS_BGEZAL: // Branch on less than zero and link
case MIPS_INS_BGEZALC:
r_strbuf_appendf (&op->esil, "%s,pc,=", ARG(0));
break;
case MIPS_INS_BNE: // bne $s, $t, offset
case MIPS_INS_BNEZ:
r_strbuf_appendf (&op->esil, "%s,%s,==,!,?{,%s,pc,=,}",
ARG(0), ARG(1), ARG(2));
break;
case MIPS_INS_BEQ:
case MIPS_INS_BEQZ:
case MIPS_INS_BEQZC:
case MIPS_INS_BEQZALC:
r_strbuf_appendf (&op->esil, "%s,%s,==,?{,%s,pc,=,}",
ARG(0), ARG(1), ARG(2));
break;
case MIPS_INS_BTEQZ:
case MIPS_INS_BTNEZ:
r_strbuf_appendf (&op->esil, "%s,pc,=", ARG(0));
break;
case MIPS_INS_MOV:
case MIPS_INS_MOVE:
case MIPS_INS_MOVF:
case MIPS_INS_MOVT:
case MIPS_INS_MOVZ:
if (REG(0)[0]!='z'){
r_strbuf_appendf (&op->esil, "%s,%s,=", ARG(1), REG(0));
} else {
r_strbuf_appendf (&op->esil, ",");
//.........这里部分代码省略.........
示例4: vm_JMP_REG
inline void vm_JMP_REG(int32_t param1, int32_t unused param2)
{
/* REG: set PC to the value in REG */
REG(PC) = REG(param1);
}示例5: i2c_slave_address
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
REG(SAR0.UINT32) = (address & 0xfffffffe);
}示例6: i2c_reg_reset
static void i2c_reg_reset(i2c_t *obj) {
/* full reset */
REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on
REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on
REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack)
REG(SER.UINT8[0]) = 0x00; // no slave addr enabled
/* set frequency */
REG(MR1.UINT8[0]) |= obj->pclk_bit;
REG(BRL.UINT8[0]) = obj->width_low;
REG(BRH.UINT8[0]) = obj->width_hi;
REG(MR2.UINT8[0]) = 0x07;
REG(MR3.UINT8[0]) = 0x00;
REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT
REG(IER.UINT8[0]) = 0x00; // no interrupt
REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset
}示例7: adc_init
/*---------------------------------------------------------------------------*/
void
adc_init(void)
{
/* Start conversions only manually */
REG(SOC_ADC_ADCCON1) |= SOC_ADC_ADCCON1_STSEL;
}示例8: adc_get
/*---------------------------------------------------------------------------*/
int16_t
adc_get(uint8_t channel, uint8_t ref, uint8_t div)
{
uint32_t cctest_tr0, rfcore_xreg_atest;
int16_t res;
/* On-chip temperature sensor */
if(channel == SOC_ADC_ADCCON_CH_TEMP) {
/* Connect the temperature sensor to the ADC */
cctest_tr0 = REG(CCTEST_TR0);
REG(CCTEST_TR0) = cctest_tr0 | CCTEST_TR0_ADCTM;
/* Enable the temperature sensor */
rfcore_xreg_atest = REG(RFCORE_XREG_ATEST);
REG(RFCORE_XREG_ATEST) = (rfcore_xreg_atest & ~RFCORE_XREG_ATEST_ATEST_CTRL) |
RFCORE_XREG_ATEST_ATEST_CTRL_TEMP;
}
/* Start a single extra conversion with the given parameters */
REG(SOC_ADC_ADCCON3) = (REG(SOC_ADC_ADCCON3) &
~(SOC_ADC_ADCCON3_EREF | SOC_ADC_ADCCON3_EDIV | SOC_ADC_ADCCON3_ECH)) |
ref | div | channel;
/* Poll until end of conversion */
while(!(REG(SOC_ADC_ADCCON1) & SOC_ADC_ADCCON1_EOC));
/* Read conversion result, reading SOC_ADC_ADCH last to clear
* SOC_ADC_ADCCON1.EOC */
res = REG(SOC_ADC_ADCL) & 0xfc;
res |= REG(SOC_ADC_ADCH) << 8;
/* On-chip temperature sensor */
if(channel == SOC_ADC_ADCCON_CH_TEMP) {
/* Restore the initial temperature sensor state and connection (better for
* power consumption) */
REG(RFCORE_XREG_ATEST) = rfcore_xreg_atest;
REG(CCTEST_TR0) = cctest_tr0;
}
/* Return conversion result */
return res;
}示例9: write32
/**
* Write a uint32_t value to a memory address
*/
inline void write32(uint32_t address, uint32_t value)
{
REG(address) = value;
}示例10: read32
/**
* Read an uint32_t from a memory address
*/
inline uint32_t read32(uint32_t address)
{
return REG(address);
}示例11: PMI_readI2C
/*
* ======== PMI_readI2C ========
* Read a PMIC register via I2C.
*/
PMI_Status PMI_readI2C(unsigned addr, unsigned reg, unsigned * data)
{
unsigned status;
unsigned busy;
/* wait for any previously sent STOP to auto complete ...*/
do
{
busy = REG(ICMDR) & STP_BIT;
}
while (busy != 0);
/* wait for any in progress bus transaction to complete... */
do
{
busy = REG(ICSTR) & BUSY_BIT;
}
while (busy != 0);
/* set slave address to be the PMIC */
REG(ICSAR) = addr;
/* set transmit byte count (ICCNT) to one byte (i.e., PMIC register ID) */
REG(ICCNT) = 1;
/* set controller mode to be master transmit */
REG(ICMDR) |= (TRX_BIT | MST_BIT);
/* put the PMIC register ID into the transmit data register */
REG(ICDXR) = reg;
/* start the transaction */
REG(ICMDR) |= STT_BIT;
asm(" .global _PMI_waitR1");
asm("_PMI_waitR1:");
/* wait for TX ready status */
do
{
status = REG(ICSTR) & ICXRDY_BIT;
}
while (status == 0);
/* wait for ARDY to indicate new register access is OK */
do
{
status = REG(ICSTR) & ARDY_BIT;
}
while (status == 0);
/* set controller mode to receive */
REG(ICMDR) &= ~TRX_BIT;
/* re-assert master bit, indicate NACK reply to slave data byte */
REG(ICMDR) |= (MST_BIT | NACKMOD_BIT);
/* start the read operation */
REG(ICMDR) |= STT_BIT;
asm(" .global _PMI_waitR2");
asm("_PMI_waitR2:");
/* wait for RX ready status */
do
{
status = REG(ICSTR) & ICRRDY_BIT;
}
while (status == 0);
/* read the received byte */
*data = REG(ICDRR);
/* signal bus STOP */
REG(ICMDR) |= STP_BIT;
return(PMI_OK);
}示例12: PMI_initI2C
/*
* ======== PMI_initI2C ========
*/
PMI_Status PMI_initI2C(void)
{
unsigned busy;
unsigned temp;
/* setup C6748 PINMUX register to select I2C functionality */
temp = REG(PINMUX4);
REG(PINMUX4) = (temp & SELECT_I2C_MASK) | SELECT_I2C_VALUE;
/* put I2C into reset */
REG(ICMDR) &= ~IRS_BIT;
/* write initial config to I2C mode register */
REG(ICMDR) = MASTERCONFIG;
/* setup I2C clock frequency */
REG(ICPSC) = PRESCALEDIVIDE;
/* setup I2C clock divider registers */
REG(ICCLKL) = CLOCKDIVIDE_LO;
REG(ICCLKH) = CLOCKDIVIDE_HI;
/* write back to clear the interrupt status register */
REG(ICSTR) = REG(ICSTR);
/* release the I2C controller from reset */
REG(ICMDR) |= IRS_BIT;
/* wait until busy busy bit is cleared indicating bus is free */
do
{
busy = REG(ICSTR) & BUSY_BIT;
}
while (busy != 0);
return(PMI_OK);
}示例13: PMI_writeI2C
/*
* ======== PMI_writeI2C ========
* Write a PMIC register via I2C.
*/
PMI_Status PMI_writeI2C(unsigned addr, unsigned reg, unsigned data)
{
unsigned status;
unsigned busy;
/* wait for any previously sent STOP to auto complete ...*/
do
{
busy = REG(ICMDR) & STP_BIT;
}
while (busy != 0);
/* wait for any previous bus transaction to complete... */
do
{
busy = REG(ICSTR) & BUSY_BIT;
}
while (busy != 0);
/* set slave address to be the PMIC */
REG(ICSAR) = addr;
/* set transmit byte count (ICCNT) to two bytes (register ID + value) */
REG(ICCNT) = 2;
/* set controller mode to master transmit */
REG(ICMDR) |= (TRX_BIT | MST_BIT);
/* put the PMIC register ID into the transmit data register */
REG(ICDXR) = reg;
/* start the transaction */
REG(ICMDR) |= STT_BIT;
asm(" .global _PMI_waitT1");
asm("_PMI_waitT1:");
/* wait for TX ready status */
do
{
status = REG(ICSTR) & ICXRDY_BIT;
}
while (status == 0);
/* put the PMIC register data value into the transmit data register */
REG(ICDXR) = data;
asm(" .global _PMI_waitT2");
asm("_PMI_waitT2:");
/* wait for TX ready status */
do
{
status = REG(ICSTR) & ICXRDY_BIT;
}
while (status == 0);
/* signal bus STOP */
REG(ICMDR) |= STP_BIT;
return(PMI_OK);
}示例14: i2c_read
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int count = 0;
int status;
int value;
volatile uint32_t work_reg = 0;
if(length <= 0) {
return 0;
}
i2c_set_MR3_ACK(obj);
/* There is a STOP condition for last processing */
if (obj->last_stop_flag != 0) {
status = i2c_start(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_BUS_BUSY;
}
}
obj->last_stop_flag = stop;
/* Send Slave address */
status = i2c_read_address_write(obj, (address | 0x01));
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* wait RDRF */
status = i2c_wait_RDRF(obj);
/* check ACK/NACK */
if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
/* Slave sends NACK */
(void)i2c_set_STOP(obj);
/* dummy read */
value = REG(DRR.UINT32);
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
obj->last_stop_flag = 1;
return I2C_ERROR_NO_SLAVE;
}
/* Read in all except last byte */
if (length > 2) {
/* dummy read */
value = REG(DRR.UINT32);
for (count = 0; count < (length - 1); count++) {
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* Recieve the data */
if (count == (length - 2)) {
value = i2c_do_read(obj, 1);
} else if ((length >= 3) && (count == (length - 3))) {
value = i2c_do_read(obj, 2);
} else {
value = i2c_do_read(obj, 0);
}
data[count] = (char)value;
}
} else if (length == 2) {
/* Set MR3 WATI bit is 1 */
REG(MR3.UINT32) |= MR3_WAIT;
/* dummy read */
value = REG(DRR.UINT32);
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
i2c_set_MR3_NACK(obj);
data[count] = (char)REG(DRR.UINT32);
count++;
} else {
/* length == 1 */
/* Set MR3 WATI bit is 1 */;
REG(MR3.UINT32) |= MR3_WAIT;
i2c_set_MR3_NACK(obj);
/* dummy read */
value = REG(DRR.UINT32);
}
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* If not repeated start, send stop. */
if (stop) {
(void)i2c_set_STOP(obj);
/* RIICnDRR read */
value = (REG(DRR.UINT32) & 0xFF);
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
} else {
(void)i2c_restart(obj);
//.........这里部分代码省略.........
示例15: orc_compiler_powerpc_register_rules
void
orc_compiler_powerpc_register_rules (OrcTarget *target)
{
OrcRuleSet *rule_set;
rule_set = orc_rule_set_new (orc_opcode_set_get("sys"), target, 0);
#define REG(name) \
orc_rule_register (rule_set, #name , powerpc_rule_ ## name , NULL);
REG(addb);
REG(addssb);
REG(addusb);
REG(andb);
REG(avgsb);
REG(avgub);
REG(cmpeqb);
REG(cmpgtsb);
REG(maxsb);
REG(maxub);
REG(minsb);
REG(minub);
REG(orb);
REG(shlb);
REG(shrsb);
REG(shrub);
REG(subb);
REG(subssb);
REG(subusb);
REG(xorb);
REG(addw);
REG(addssw);
REG(addusw);
REG(andw);
REG(avgsw);
REG(avguw);
REG(cmpeqw);
REG(cmpgtsw);
REG(maxsw);
REG(maxuw);
REG(minsw);
REG(minuw);
REG(orw);
REG(shlw);
REG(shrsw);
REG(shruw);
REG(subw);
REG(subssw);
REG(subusw);
REG(xorw);
REG(addl);
REG(addssl);
REG(addusl);
REG(andl);
REG(avgsl);
REG(avgul);
REG(cmpeql);
REG(cmpgtsl);
REG(maxsl);
REG(maxul);
REG(minsl);
REG(minul);
REG(orl);
REG(shll);
REG(shrsl);
REG(shrul);
REG(subl);
REG(subssl);
REG(subusl);
REG(xorl);
REG(andq);
REG(orq);
REG(xorq);
REG(mullb);
REG(mulhsb);
REG(mulhub);
REG(mullw);
REG(mulhsw);
REG(mulhuw);
REG(convsbw);
REG(convswl);
REG(convubw);
REG(convuwl);
REG(convssswb);
REG(convssslw);
REG(convsuswb);
REG(convsuslw);
REG(convuuswb);
REG(convuuslw);
REG(convwb);
REG(convlw);
REG(mulsbw);
REG(mulubw);
REG(mulswl);
//.........这里部分代码省略.........