C++ READ_REG32函数代码示例

/*******************************************************************************
* Function Name  : OTGD_FS_EP0Activate
* Description    : enables EP0 OUT to receive SETUP packets and configures EP0
                   IN for transmitting packets
* Input          : None
* Output         : None
* Return         : status
*******************************************************************************/
USB_OTG_Status  OTGD_FS_EP0Activate(void)
{
  USB_OTG_Status          status = USB_OTG_OK;
  USB_OTG_dev_sts_data    dsts;
  USB_OTG_dev_ep_ctl_data diepctl;
  USB_OTG_dev_ctl_data    dctl;

  dctl.d32 = 0;
  /* Read the Device Status and Endpoint 0 Control registers */
  dsts.d32 = READ_REG32(&core_regs.dev_regs->dev_sts);
  diepctl.d32 = READ_REG32(&core_regs.inep_regs[0]->dev_in_ep_ctl);

  /* Set the MPS of the IN EP based on the enumeration speed */
  switch (dsts.b.enumspd)
  {
    case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
    case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
    case DSTS_ENUMSPD_FS_PHY_48MHZ:
      diepctl.b.mps = DEP0CTL_MPS_64;
      break;
    case DSTS_ENUMSPD_LS_PHY_6MHZ:
      diepctl.b.mps = DEP0CTL_MPS_8;
      break;
  }

  WRITE_REG32(&core_regs.inep_regs[0]->dev_in_ep_ctl, diepctl.d32);
  dctl.b.cgnpinnak = 1;
  MODIFY_REG32(&core_regs.dev_regs->dev_ctl, dctl.d32, dctl.d32);
  return status;
}

/*******************************************************************************
* Function Name  : OTGD_FS_ReadDevOutEP_itr
* Description    : returns the Device OUT EP Interrupt register
* Input          : None
* Output         : None
* Return         : None
*******************************************************************************/
uint32_t OTGD_FS_ReadDevOutEP_itr(USB_OTG_EP *ep)
{
  uint32_t v;
  v  = READ_REG32(&core_regs.outep_regs[ep->num]->dev_out_ep_int);
  v &= READ_REG32(&core_regs.dev_regs->dev_out_ep_msk);
  return v;
}

/*******************************************************************************
* Function Name  : OTGD_FS_EPSetStall
* Description    : Set the EP STALL
* Input          : None
* Output         : None
* Return         : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_EPSetStall(USB_OTG_EP *ep)
{
  USB_OTG_Status status = USB_OTG_OK;
  USB_OTG_dev_ep_ctl_data depctl; 
  __IO uint32_t *depctl_addr;

  if (ep->is_in == 1)
  {
    depctl_addr = &(core_regs.inep_regs[ep->num]->dev_in_ep_ctl);
    depctl.d32 = READ_REG32(depctl_addr);

    /* set the disable and stall bits */
    if (depctl.b.epena)
    {
      depctl.b.epdis = 1;
    }
    depctl.b.stall = 1;
    WRITE_REG32(depctl_addr, depctl.d32);
  }
  else
  {
    depctl_addr = &(core_regs.outep_regs[ep->num]->dev_out_ep_ctl);
    depctl.d32 = READ_REG32(depctl_addr);

    /* set the stall bit */
    depctl.b.stall = 1;
    WRITE_REG32(depctl_addr, depctl.d32);
  }
  return status;
}

/*******************************************************************************
* Function Name  : OTGD_FS_ReadDevAllInEPItr
* Description    : Get int status register
* Input          : None
* Output         : None
* Return         : None
*******************************************************************************/
uint32_t OTGD_FS_ReadDevAllInEPItr(void)
{
  uint32_t v;
  v = READ_REG32(&core_regs.dev_regs->dev_all_int);
  v &= READ_REG32(&core_regs.dev_regs->dev_all_int_msk);
  return (v & 0xffff);
}

/*******************************************************************************
* Function Name  : OTGD_FS_ReadDevAllOutEp_itr
* Description    : returns the OUT endpoint interrupt bits
* Input          : None
* Output         : None
* Return         : None
*******************************************************************************/
uint32_t OTGD_FS_ReadDevAllOutEp_itr(void)
{
  uint32_t v;
  v  = READ_REG32(&core_regs.dev_regs->dev_all_int);
  v &= READ_REG32(&core_regs.dev_regs->dev_all_int_msk);
  return ((v & 0xffff0000) >> 16);
}

/*
 * ============================================================================
 *
 *  Function Name: void chal_audio_dmic2_pwrctrl(CHAL_HANDLE handle,
 *						_Bool pwronoff)
 *
 *  Description:   power on/off digital microphone path
 *
 *  Parameters:
 *                 handle   ---  the  audio handle
 *			pwronoff ---  on or off selection
 *  Return:        none
 *
 * ============================================================================
 */
void chal_audio_dmic2_pwrctrl(CHAL_HANDLE handle, _Bool pwronoff)
{

	cUInt32 regVal;
	cUInt32 function = 0x0;

	if (pwronoff == TRUE)
		function = 0x4;

	/* Select the function for GPIO33 */
	/* For function = 4 (alt_fn5), this will be set
	 * as DMIC2_CLK */
	regVal = READ_REG32((KONA_PAD_CTRL_VA + PADCTRLREG_GPIO33_OFFSET));
	regVal &= (~PADCTRLREG_GPIO33_PINSEL_GPIO33_MASK);
	regVal |= (function << PADCTRLREG_GPIO33_PINSEL_GPIO33_SHIFT);
	WRITE_REG32((KONA_PAD_CTRL_VA + PADCTRLREG_GPIO33_OFFSET), regVal);

	/* Select the function for GPIO34 */
	/* For function = 4 (alt_fn5), this will be set as
	 * DMIC2_DATA */
	regVal = READ_REG32((KONA_PAD_CTRL_VA + PADCTRLREG_GPIO34_OFFSET));
	regVal &= (~PADCTRLREG_GPIO34_PINSEL_GPIO34_MASK);
	regVal |= (function << PADCTRLREG_GPIO34_PINSEL_GPIO34_SHIFT);
	WRITE_REG32((KONA_PAD_CTRL_VA + PADCTRLREG_GPIO34_OFFSET), regVal);
	/* For FPGA no pads are present */
}

/*******************************************************************************
* Function Name  : OTGD_FS_ReadCoreItr
* Description    : returns the Core Interrupt register
* Input          : None
* Output         : None
* Return         : None
*******************************************************************************/
uint32_t OTGD_FS_ReadCoreItr(void)
{
  uint32_t v;

  v = READ_REG32(&core_regs.common_regs->int_sts);
  v &= READ_REG32(&core_regs.common_regs->int_msk);

  return v;
}

/*******************************************************************************
* Function Name  : OTGD_FS_CoreInit
* Description    : Initialize the USB_OTG controller registers and prepares the core
                   for device mode or host mode operation.
* Input          : None
* Output         : None
* Return         : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_CoreInit(void)
{
  USB_OTG_Status status = USB_OTG_OK;
  USB_OTG_usb_cfg_data usbcfg;

  usbcfg.d32 = 0;

  /* Reset the Controller */
  OTGD_FS_CoreReset();

  usbcfg.d32 = READ_REG32(&core_regs.common_regs->usb_cfg);
  usbcfg.b.physel = 1;
  WRITE_REG32 (&core_regs.common_regs->usb_cfg, usbcfg.d32);

  /* init and configure the phy */
  OTGD_FS_PhyInit();

  /* Reset after a PHY select and set Host mode */
  OTGD_FS_CoreReset();

  /* Set Host or Device Mode */
  SetID();

  return status;
}

static unsigned int
lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
{
	u32 data = ~0U;
	int error = 0;
	u32 arb_mask = 0;	/* used by LBA_CFG_SETUP/RESTORE */
	u32 error_config = 0;	/* used by LBA_CFG_SETUP/RESTORE */
	u32 status_control = 0;	/* used by LBA_CFG_SETUP/RESTORE */

	LBA_CFG_SETUP(d, tok);
	LBA_CFG_PROBE(d, tok);
	LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
	if (!error) {
		void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;

		LBA_CFG_ADDR_SETUP(d, tok | reg);
		switch (size) {
		case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break;
		case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break;
		case 4: data = READ_REG32(data_reg); break;
		}
	}
	LBA_CFG_RESTORE(d, d->hba.base_addr);
	return(data);
}

/*******************************************************************************
* Function Name  : OTGD_FS_EPClearStall
* Description    : Clear the EP STALL
* Input          : None
* Output         : None
* Return         : Status
*******************************************************************************/
USB_OTG_Status OTGD_FS_EPClearStall(USB_OTG_EP *ep)
{
  USB_OTG_Status status = USB_OTG_OK;
  USB_OTG_dev_ep_ctl_data depctl;
  __IO uint32_t *depctl_addr;

  if (ep->is_in == 1)
  {
    depctl_addr = &(core_regs.inep_regs[ep->num]->dev_in_ep_ctl);
  }
  else
  {
    depctl_addr = &(core_regs.outep_regs[ep->num]->dev_out_ep_ctl);
  }

  
  depctl.d32 = READ_REG32(depctl_addr);
   
  /* clear the stall bits */
  depctl.b.stall = 0;

  if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
  {
    depctl.b.setd0pid = 1; /* DATA0 */
  }

  WRITE_REG32(depctl_addr, depctl.d32);
  return status;
}

/*******************************************************************************
* Function Name  : OTGD_FS_FlushRxFifo
* Description    : Flush a Rx FIFO
* Input          : None
* Output         : None
* Return         : status
*******************************************************************************/
USB_OTG_Status OTGD_FS_FlushRxFifo( void )
{
  USB_OTG_Status status = USB_OTG_OK;
  __IO USB_OTG_rst_ctl_data greset;
  int count = 0;

  greset.d32 = 0;
  greset.b.rxfflsh = 1;
  WRITE_REG32( &core_regs.common_regs->rst_ctl, greset.d32 );

  do
  {
    greset.d32 = READ_REG32( &core_regs.common_regs->rst_ctl);
    if (++count > 200000)
    {
      break;
    }
  }
  while (greset.b.rxfflsh == 1);

  /* Wait for 3 PHY Clocks*/
  uDELAY(3);

  return status;
}

static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
{
	struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
	u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
	u32 tok = LBA_CFG_TOK(local_bus, devfn);
	void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;

	if ((pos > 255) || (devfn > 255))
		return -EINVAL;

	LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
	switch(size) {
	case 1:
		*data = READ_REG8(data_reg + (pos & 3));
		break;
	case 2:
		*data = READ_REG16(data_reg + (pos & 2));
		break;
	case 4:
		*data = READ_REG32(data_reg);             break;
		break;
	}

	DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data);
	return 0;
}

/*******************************************************************************
* Function Name  : InitDevSpeed
* Description    : Initializes the DevSpd field of the DCFG register depending
                   on the PHY type and the enumeration speed of the device.
* Input          : None
* Output         : None
* Return         : None
*******************************************************************************/
static void InitDevSpeed(void)
{
  USB_OTG_dev_cfg_data  dcfg;

  dcfg.d32 = READ_REG32(&core_regs.dev_regs->dev_cfg);
  dcfg.b.devspd = 0x3;  /* Full speed PHY */
  WRITE_REG32(&core_regs.dev_regs->dev_cfg, dcfg.d32);
}

// Read the FIFO for the endpoint indexed by Endpoint, into the buffer pointed
// at by Buffer, whose size is *Size bytes.
//
// If *Size is less than the number of bytes in the FIFO, return EFI_BUFFER_TOO_SMALL
//
// Update *Size with the number of bytes of data in the FIFO.
STATIC
EFI_STATUS
ReadEndpointBuffer (
  IN      UINT8   Endpoint,
  IN OUT  UINTN  *Size,
  IN OUT  VOID   *Buffer
  )
{
  UINT16  NumBytesAvailable;
  UINT32  Val32;
  UINTN   Index;
  UINTN   NumBytesRead;

  SelectEndpoint (Endpoint);

  NumBytesAvailable = READ_REG16 (ISP1761_BUFFER_LENGTH);

  if (NumBytesAvailable > *Size) {
    *Size = NumBytesAvailable;
    return EFI_BUFFER_TOO_SMALL;
  }
  *Size = NumBytesAvailable;

  /* -- NB! --
    The datasheet says the Data Port is 16 bits but it actually appears to
    be 32 bits.
   */

  // Read 32-bit chunks
  for (Index = 0; Index < NumBytesAvailable / 4; Index++) {
    ((UINT32 *) Buffer)[Index] = READ_REG32 (ISP1761_DATA_PORT);
  }

  // Read remaining bytes

  // Round NumBytesAvailable down to nearest power of 4
  NumBytesRead = NumBytesAvailable & (~0x3);
  if (NumBytesRead != NumBytesAvailable) {
    Val32 = READ_REG32 (ISP1761_DATA_PORT);
    // Copy each required byte of 32-bit word into buffer
    for (Index = 0; Index < NumBytesAvailable % 4; Index++) {
      ((UINT8 *) Buffer)[NumBytesRead + Index] = Val32 >> (Index * 8);
    }
  }

cVoid chal_audio_mic_input_select(CHAL_HANDLE handle, UInt16 mic_input)
{

	cUInt32 regVal = 0;

	cUInt32 base = ((ChalAudioCtrlBlk_t *) handle)->audioh_base;

	cUInt32 reg_val;

	reg_val = BRCM_READ_REG(base, AUDIOH_ADC_CTL);
	reg_val &= ~(AUDIOH_ADC_CTL_AMIC_EN_MASK);

	/* if(mic_input == CHAL_AUDIO_ENABLE) { */
	reg_val |= AUDIOH_ADC_CTL_AMIC_EN_MASK;

	/* Set the required setting */
	BRCM_WRITE_REG(base, AUDIOH_ADC_CTL, reg_val);

	/* ACI control for analog microphone */

	/* WRITE_REG32(0x3500E0D4, 0xC0); */
	regVal = READ_REG32((ACI_BASE_ADDR + ACI_ADC_CTRL_OFFSET));
	regVal |= ACI_ADC_CTRL_AUDIORX_VREF_PWRUP_MASK;
	regVal |= ACI_ADC_CTRL_AUDIORX_BIAS_PWRUP_MASK;
	WRITE_REG32((ACI_BASE_ADDR + ACI_ADC_CTRL_OFFSET), regVal);

	/* enable AUXMIC */

	/* WRITE_REG32(0x3500E014, 0x01); */
	regVal = READ_REG32((AUXMIC_BASE_ADDR + AUXMIC_AUXEN_OFFSET));
	regVal |= AUXMIC_AUXEN_MICAUX_EN_MASK;
	WRITE_REG32((AUXMIC_BASE_ADDR + AUXMIC_AUXEN_OFFSET), regVal);

	/* disable AUXMIC force power down */

	regVal = READ_REG32((AUXMIC_BASE_ADDR + AUXMIC_F_PWRDWN_OFFSET));
	regVal &= ~AUXMIC_F_PWRDWN_FORCE_PWR_DWN_MASK;
	WRITE_REG32((AUXMIC_BASE_ADDR + AUXMIC_F_PWRDWN_OFFSET), regVal);

	return;
}