本文整理汇总了C++中READ_MPEG_REG函数的典型用法代码示例。如果您正苦于以下问题：C++ READ_MPEG_REG函数的具体用法？C++ READ_MPEG_REG怎么用？C++ READ_MPEG_REG使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了READ_MPEG_REG函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: tsdemux_init
s32 tsdemux_init(u32 vid, u32 aid, u32 sid, u32 pcrid, bool is_hevc)
{
s32 r;
u32 parser_sub_start_ptr;
u32 parser_sub_end_ptr;
u32 parser_sub_rp;
u32 pcr_num;
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
switch_mod_gate_by_type(MOD_DEMUX, 1);
#endif
parser_sub_start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
parser_sub_end_ptr = READ_MPEG_REG(PARSER_SUB_END_PTR);
parser_sub_rp = READ_MPEG_REG(PARSER_SUB_RP);
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER);
#ifdef ENABLE_DEMUX_DRIVER
tsdemux_reset();
#else
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER | RESET_DEMUXSTB);
WRITE_MPEG_REG(STB_TOP_CONFIG, 0);
WRITE_MPEG_REG(DEMUX_CONTROL, 0);
#endif
/* set PID filter */
printk("tsdemux video_pid = 0x%x, audio_pid = 0x%x, sub_pid = 0x%x, pcrid = 0x%x\n",
vid, aid, sid, pcrid);
#ifndef ENABLE_DEMUX_DRIVER
WRITE_MPEG_REG(FM_WR_DATA,
(((vid & 0x1fff) | (VIDEO_PACKET << 13)) << 16) |
((aid & 0x1fff) | (AUDIO_PACKET << 13)));
WRITE_MPEG_REG(FM_WR_ADDR, 0x8000);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(FM_WR_DATA,
(((sid & 0x1fff) | (SUB_PACKET << 13)) << 16) | 0xffff);
WRITE_MPEG_REG(FM_WR_ADDR, 0x8001);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(MAX_FM_COMP_ADDR, 1);
WRITE_MPEG_REG(STB_INT_MASK, 0);
WRITE_MPEG_REG(STB_INT_STATUS, 0xffff);
/* TS data path */
WRITE_MPEG_REG(FEC_INPUT_CONTROL, 0x7000);
WRITE_MPEG_REG(DEMUX_MEM_REQ_EN,
(1 << VIDEO_PACKET) |
(1 << AUDIO_PACKET) |
(1 << SUB_PACKET));
WRITE_MPEG_REG(DEMUX_ENDIAN,
(7 << OTHER_ENDIAN) |
(7 << BYPASS_ENDIAN) |
(0 << SECTION_ENDIAN));
WRITE_MPEG_REG(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE);
WRITE_MPEG_REG(TS_FILE_CONFIG,
(demux_skipbyte << 16) |
(6 << DES_OUT_DLY) |
(3 << TRANSPORT_SCRAMBLING_CONTROL_ODD) |
(1 << TS_HIU_ENABLE) |
(4 << FEC_FILE_CLK_DIV));
/* enable TS demux */
WRITE_MPEG_REG(DEMUX_CONTROL, (1 << STB_DEMUX_ENABLE) | (1 << KEEP_DUPLICATE_PACKAGE));
#endif
if (fetchbuf == 0) {
printk("%s: no fetchbuf\n", __FUNCTION__);
return -ENOMEM;
}
/* hook stream buffer with PARSER */
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
if (HAS_HEVC_VDEC && is_hevc) {
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(HEVC_STREAM_START_ADDR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(HEVC_STREAM_END_ADDR) - 8);
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_VREG(DOS_GEN_CTRL0, 3<<1); // set vififo_vbuf_rp_sel=>hevc
SET_VREG_MASK(HEVC_STREAM_CONTROL, (1<<3)|(0<<4)); // set use_parser_vbuf_wp
SET_VREG_MASK(HEVC_STREAM_CONTROL, 1); // set stream_fetch_enable
SET_VREG_MASK(HEVC_STREAM_FIFO_CTL, (1<<29)); // set stream_buffer_hole with 256 bytes
} else
#endif
{
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(VLD_MEM_VIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
//.........这里部分代码省略.........
示例2: feed_vb
static inline void feed_vb(s32 s)
{
u32 addr = READ_MPEG_REG(VLD_MEM_VIFIFO_START_PTR);
amlog_mask_level(LOG_MASK_PARSER,LOG_LEVEL_LOW,"feed start addr:0x%x\n",addr);
WRITE_MPEG_REG(VLD_MEM_VIFIFO_WP, (addr + s + PADDINGSIZE + 7) & ~7);
}示例3: _rmparser_write
static ssize_t _rmparser_write(const char __user *buf, size_t count)
{
size_t r = count;
const char __user *p = buf;
u32 len;
int ret;
static int halt_droped_len=0;
u32 vwp,awp;
if (r > 0) {
len = min(r, (size_t)FETCHBUF_SIZE);
if (copy_from_user(fetchbuf_remap, p, len)) {
return -EFAULT;
}
fetch_done = 0;
wmb();
vwp=buf_wp(BUF_TYPE_VIDEO);
awp=buf_wp(BUF_TYPE_AUDIO);
WRITE_MPEG_REG(PARSER_FETCH_ADDR, virt_to_phys((u8 *)fetchbuf));
WRITE_MPEG_REG(PARSER_FETCH_CMD,
(7 << FETCH_ENDIAN) | len);
ret = wait_event_interruptible_timeout(rm_wq, fetch_done != 0, HZ/10);
if (ret == 0) {
WRITE_MPEG_REG(PARSER_FETCH_CMD, 0);
parse_halt ++;
printk("write timeout, retry,halt_count=%d parse_control=%x \n",
parse_halt,READ_MPEG_REG(PARSER_CONTROL));
vreal_set_fatal_flag(1);
if(parse_halt > 10) {
WRITE_MPEG_REG(PARSER_CONTROL, (ES_SEARCH | ES_PARSER_START));
printk("reset parse_control=%x\n",READ_MPEG_REG(PARSER_CONTROL));
}
return -EAGAIN;
} else if (ret < 0) {
return -ERESTARTSYS;
}
if(vwp==buf_wp(BUF_TYPE_VIDEO) && awp==buf_wp(BUF_TYPE_AUDIO)){
if((parse_halt+1)%10==1)
printk("Video&Audio WP not changed after write,video %x->%x,Audio:%x-->%x,parse_halt=%d\n",
vwp,buf_wp(BUF_TYPE_VIDEO),awp,buf_wp(BUF_TYPE_AUDIO),parse_halt);
parse_halt ++;/*wp not changed ,we think have bugs on parser now.*/
if(parse_halt > 10 && (stbuf_level(get_buf_by_type(BUF_TYPE_VIDEO))< 1000 || stbuf_level(get_buf_by_type(BUF_TYPE_AUDIO))< 100))
{/*reset while at least one is underflow.*/
WRITE_MPEG_REG(PARSER_CONTROL, (ES_SEARCH | ES_PARSER_START));
printk("reset parse_control=%x\n",READ_MPEG_REG(PARSER_CONTROL));
}
if(parse_halt <= 10 || halt_droped_len <100*1024){/*drops first 10 pkt ,some times maybe no av data*/
printk("drop this pkt=%d,len=%d\n",parse_halt,len);
p += len;
r -= len;
halt_droped_len+=len;
}else{
return -EAGAIN;
}
}else{
halt_droped_len=0;
parse_halt = 0;
p += len;
r -= len;
}
}
return count - r;
}示例4: timestamp_apts_get
u32 timestamp_apts_get(void)
{
return READ_MPEG_REG(AUDIO_PTS);
}示例5: aml_m1_reset
void aml_m1_reset(struct snd_soc_codec* codec, bool first_time)
{
unsigned long data32;
if(first_time){
/* initialize clock for audiodac */
audio_set_clk(AUDIO_CLK_FREQ_48,0);
/* power up pll */
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) & ~(1 << 15));
/* enable audiodac clock */
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 1, 23, 1);
msleep(100);
data32 = 0;
data32 |= 0 << 15; // [15] audac_soft_reset_n
data32 |= 0 << 14; // [14] audac_reset_ctrl: 0=use audac_reset_n pulse from reset module; 1=use audac_soft_reset_n.
data32 |= 0 << 9; // [9] delay_rd_en
data32 |= 0 << 8; // [8] audac_reg_clk_inv
data32 |= 0 << 1; // [7:1] audac_i2caddr
data32 |= 0 << 0; // [0] audac_intfsel: 0=use host bus; 1=use I2C.
WRITE_MPEG_REG(AIU_AUDAC_CTRL0, data32);
// Enable APB3 fail on error
data32 = 0;
data32 |= 1 << 15; // [15] err_en
data32 |= 255 << 0; // [11:0] max_err
WRITE_MPEG_REG(AIU_AUDAC_CTRL1, data32);
snd_soc_write(codec, ADAC_RESET, (0<<1));
snd_soc_write(codec, ADAC_RESET, (0<<1));
snd_soc_write(codec, ADAC_RESET, (0<<1));
snd_soc_write(codec, ADAC_RESET, (0<<1));
snd_soc_write(codec, ADAC_RESET, (0<<1));
msleep(100);
snd_soc_write(codec,ADAC_CLOCK, 0);
snd_soc_write(codec,ADAC_I2S_CONFIG_REG1, 6);
snd_soc_write(codec, ADAC_I2S_CONFIG_REG2, 1|(1<<3)); // I2S, split
snd_soc_write(codec, ADAC_POWER_CTRL_REG1, 0xc3);
snd_soc_write(codec, ADAC_POWER_CTRL_REG2, 0);
snd_soc_write(codec, ADAC_MUTE_CTRL_REG1,0);
snd_soc_write(codec,ADAC_DAC_ADC_MIXER, 0);
snd_soc_write(codec,ADAC_PLAYBACK_VOL_CTRL_LSB, 0x54);
snd_soc_write(codec,ADAC_PLAYBACK_VOL_CTRL_MSB, 0x54);
snd_soc_write(codec,ADAC_STEREO_HS_VOL_CTRL_LSB, 0x28);
snd_soc_write(codec,ADAC_STEREO_HS_VOL_CTRL_MSB, 0x28);
latch(codec);
snd_soc_write(codec, ADAC_POWER_CTRL_REG2, (0<<7));
latch(codec);
snd_soc_write(codec, ADAC_POWER_CTRL_REG2, (1<<7));
latch(codec);
}else{
latch(codec);
snd_soc_write(codec, ADAC_POWER_CTRL_REG2, (0<<7));
latch(codec);
snd_soc_write(codec, ADAC_POWER_CTRL_REG2, (1<<7));
latch(codec);
}
snd_soc_write(codec, ADAC_RESET, (0<<1));
latch(codec);
snd_soc_write(codec, ADAC_RESET, (1<<1));
latch(codec);
msleep(100);
}示例6: timestamp_vpts_get
u32 timestamp_vpts_get(void)
{
return READ_MPEG_REG(VIDEO_PTS);
}示例7: read_i2s_rd_ptr
unsigned int read_i2s_rd_ptr(void)
{
unsigned int val;
val = READ_MPEG_REG(AIU_MEM_I2S_RD_PTR);
return val;
}示例8: read_i2s_mute_swap_reg
unsigned int read_i2s_mute_swap_reg(void)
{
unsigned int val;
val = READ_MPEG_REG(AIU_I2S_MUTE_SWAP);
return val;
}示例9: lvds_port_disable
static void lvds_port_disable(void)
{
//disable minilvds_data channel
WRITE_MPEG_REG(LVDS_PHY_CNTL4, READ_MPEG_REG(LVDS_PHY_CNTL4) & ~(0x7f<<0));
}示例10: audio_set_clk
void audio_set_clk(unsigned freq, unsigned fs_config)
{
int i;
struct clk *clk;
int xtal = 0;
int (*audio_clock_config)[2];
// if (fs_config == AUDIO_CLK_256FS) {
if(1){
int index=0;
switch(freq)
{
case AUDIO_CLK_FREQ_192:
index=4;
break;
case AUDIO_CLK_FREQ_96:
index=3;
break;
case AUDIO_CLK_FREQ_48:
index=2;
break;
case AUDIO_CLK_FREQ_441:
index=1;
break;
case AUDIO_CLK_FREQ_32:
index=0;
break;
case AUDIO_CLK_FREQ_8:
index = 5;
break;
case AUDIO_CLK_FREQ_11:
index = 6;
break;
case AUDIO_CLK_FREQ_12:
index = 7;
break;
case AUDIO_CLK_FREQ_16:
index = 8;
break;
case AUDIO_CLK_FREQ_22:
index = 9;
break;
case AUDIO_CLK_FREQ_24:
index = 10;
break;
default:
index=0;
break;
};
// get system crystal freq
clk=clk_get_sys("clk_xtal", NULL);
if(!clk)
{
printk(KERN_ERR "can't find clk %s for AUDIO PLL SETTING!\n\n","clk_xtal");
//return -1;
}
else
{
xtal=clk_get_rate(clk);
xtal=xtal/1000000;
if(xtal>=24 && xtal <=25)/*current only support 24,25*/
{
xtal-=24;
}
else
{
printk(KERN_WARNING "UNsupport xtal setting for audio xtal=%d,default to 24M\n",xtal);
xtal=0;
}
}
audio_clock_config = audio_clock_config_table[xtal];
// gate the clock off
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8));
#ifdef CONFIG_SND_AML_M2
WRITE_MPEG_REG(HHI_AUD_PLL_CNTL2, 0x065e31ff);
WRITE_MPEG_REG(HHI_AUD_PLL_CNTL3, 0x9649a941);
// select Audio PLL as MCLK source
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 9));
#endif
// Put the PLL to sleep
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15));
#ifdef CONFIG_SND_AML_M2
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);
#endif
// Bring out of reset but keep bypassed to allow to stablize
//Wr( HHI_AUD_PLL_CNTL, (1 << 15) | (0 << 14) | (hiu_reg & 0x3FFF) );
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, (1 << 15) | (audio_clock_config[index][0] & 0x7FFF) );
// Set the XD value
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, (READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(0xff << 0)) | audio_clock_config[index][1]);
// delay 5uS
//udelay(5);
for (i = 0; i < 500000; i++) ;
// Bring the PLL out of sleep
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) & ~(1 << 15));
//.........这里部分代码省略.........
示例11: lvds_port_enable
static void lvds_port_enable(void)
{
printk("\n\nLVDS port enable.\n");
//enable minilvds_data channel
WRITE_MPEG_REG(LVDS_PHY_CNTL4, READ_MPEG_REG(LVDS_PHY_CNTL4) | (0x2f<<0));
}示例12: am_set_regmap
void am_set_regmap(unsigned int cnt, struct am_reg_s *p)
{
unsigned short i;
unsigned int temp = 0;
for (i=0; i<cnt; i++) {
switch (p->type)
{
case REG_TYPE_PHY:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: phy..............\n", __func__);
#endif
break;
case REG_TYPE_CBUS:
if (p->mask == 0xffffffff)
WRITE_CBUS_REG(p->addr, p->val);
else
WRITE_CBUS_REG(p->addr, (READ_CBUS_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: cbus: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_APB:
if (p->mask == 0xffffffff)
WRITE_APB_REG(p->addr, p->val);
else
WRITE_APB_REG(p->addr, (READ_APB_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: apb bus: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_MPEG:
if (p->mask == 0xffffffff)
WRITE_MPEG_REG(p->addr, p->val);
else
WRITE_MPEG_REG(p->addr, (READ_MPEG_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: mpeg: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_AXI:
if (p->mask == 0xffffffff)
WRITE_AXI_REG(p->addr, p->val);
else
WRITE_AXI_REG(p->addr, (READ_AXI_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: axi: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_AHB:
if (p->mask == 0xffffffff)
WRITE_AHB_REG(p->addr, p->val);
else
WRITE_AHB_REG(p->addr, (READ_AHB_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: ahb: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_INDEX_VPPCHROMA:
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
if (p->mask == 0xffffffff)
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
else
{
temp = READ_CBUS_REG(VPP_CHROMA_DATA_PORT);
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, (temp & (~p->mask)) | (p->val & p->mask));
}
#ifdef PQ_DEBUG_EN
pr_info("%s: vppchroma: 0x1d70:port0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_INDEX_GAMMA:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: REG_TYPE_INDEX_GAMMA..............\n", __func__);
#endif
break;
case VALUE_TYPE_CONTRAST_BRIGHTNESS:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: VALUE_TYPE_CONTRAST_BRIGHTNESS..............\n", __func__);
#endif
break;
case REG_TYPE_INDEX_VPP_COEF:
if (((p->addr&0xf) == 0)||((p->addr&0xf) == 0x8))
{
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
else
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
#ifdef PQ_DEBUG_EN
pr_info("%s: vppcoef: 0x1d70:port0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
default:
pr_info("%s: bus type error!!!bustype = 0x%x................\n", __func__, p->type);
//.........这里部分代码省略.........
示例13: tsdemux_isr
static irqreturn_t tsdemux_isr(int irq, void *dev_id)
{
#ifndef ENABLE_DEMUX_DRIVER
u32 int_status = READ_MPEG_REG(STB_INT_STATUS);
#else
int id = (int)dev_id;
u32 int_status = id ? READ_MPEG_REG(STB_INT_STATUS_2) : READ_MPEG_REG(STB_INT_STATUS);
#endif
if (int_status & (1 << NEW_PDTS_READY)) {
#ifndef ENABLE_DEMUX_DRIVER
u32 pdts_status = READ_MPEG_REG(STB_PTS_DTS_STATUS);
if (pdts_status & (1 << VIDEO_PTS_READY))
pts_checkin_wrptr(PTS_TYPE_VIDEO,
READ_MPEG_REG(VIDEO_PDTS_WR_PTR),
READ_MPEG_REG(VIDEO_PTS_DEMUX));
if (pdts_status & (1 << AUDIO_PTS_READY))
pts_checkin_wrptr(PTS_TYPE_AUDIO,
READ_MPEG_REG(AUDIO_PDTS_WR_PTR),
READ_MPEG_REG(AUDIO_PTS_DEMUX));
WRITE_MPEG_REG(STB_PTS_DTS_STATUS, pdts_status);
#else
#define DMX_READ_REG(i,r)\
((i)?((i==1)?READ_MPEG_REG(r##_2):READ_MPEG_REG(r##_3)):READ_MPEG_REG(r))
u32 pdts_status = DMX_READ_REG(id, STB_PTS_DTS_STATUS);
if (pdts_status & (1 << VIDEO_PTS_READY))
pts_checkin_wrptr(PTS_TYPE_VIDEO,
DMX_READ_REG(id, VIDEO_PDTS_WR_PTR),
DMX_READ_REG(id, VIDEO_PTS_DEMUX));
if (pdts_status & (1 << AUDIO_PTS_READY))
pts_checkin_wrptr(PTS_TYPE_AUDIO,
DMX_READ_REG(id, AUDIO_PDTS_WR_PTR),
DMX_READ_REG(id, AUDIO_PTS_DEMUX));
if (id == 1) {
WRITE_MPEG_REG(STB_PTS_DTS_STATUS_2, pdts_status);
} else if (id == 2){
WRITE_MPEG_REG(STB_PTS_DTS_STATUS_3, pdts_status);
} else {
WRITE_MPEG_REG(STB_PTS_DTS_STATUS, pdts_status);
}
#endif
}
if (int_status & (1 << DIS_CONTINUITY_PACKET)) {
discontinued_counter++;
//printk("discontinued counter=%d\n",discontinued_counter);
}
if (int_status & (1 << SUB_PES_READY)) {
/* TODO: put data to somewhere */
//printk("subtitle pes ready\n");
wakeup_sub_poll();
}
#ifndef ENABLE_DEMUX_DRIVER
WRITE_MPEG_REG(STB_INT_STATUS, int_status);
#endif
return IRQ_HANDLED;
}示例14: store_dbg
static ssize_t store_dbg(struct device * dev, struct device_attribute *attr, const char * buf, size_t count)
{
char tmpbuf[128];
int i=0;
unsigned int adr;
unsigned int value=0;
while((buf[i])&&(buf[i]!=',')&&(buf[i]!=' ')){
tmpbuf[i]=buf[i];
i++;
}
tmpbuf[i]=0;
if(strncmp(tmpbuf, "config_dvin", 11)==0){
#ifdef DEBUG_DVIN
config_dvin (hs_pol_inv,
vs_pol_inv,
de_pol_inv,
field_pol_inv,
ext_field_sel,
de_mode,
data_comp_map,
mode_422to444,
dvin_clk_inv,
vs_hs_tim_ctrl,
hs_lead_vs_odd_min,
hs_lead_vs_odd_max,
active_start_pix_fe,
active_start_pix_fo,
active_start_line_fe,
active_start_line_fo,
line_width,
field_height);
#endif
}
else if(strncmp(tmpbuf, "pause", 5)==0){
hdmirx_device.task_pause = 1;
printk("Pause %s\n", __func__);
}
else if(strncmp(tmpbuf, "start", 5)==0){
hdmirx_device.task_pause = 0;
printk("Start %s\n", __func__);
}
else if(strncmp(tmpbuf, "spdif", 5)==0){
setHDMIRX_SPDIFOutput();
}
else if(strncmp(tmpbuf, "i2s", 3)==0){
setHDMIRX_I2SOutput(0x1);
}
else if(strncmp(tmpbuf, "hpd", 3)==0){
if(tmpbuf[3]=='0'){
CLEAR_HPD;
}
else if(tmpbuf[3]=='1'){
SET_HPD;
}
}
else if(tmpbuf[0]=='w'){
adr=simple_strtoul(tmpbuf+2, NULL, 16);
value=simple_strtoul(buf+i+1, NULL, 16);
if(buf[1]=='h'){
HDMIRX_WriteI2C_Byte(adr, value);
}
else if(buf[1]=='c'){
WRITE_MPEG_REG(adr, value);
pr_info("write %x to CBUS reg[%x]\n",value,adr);
}
else if(buf[1]=='p'){
WRITE_APB_REG(adr, value);
pr_info("write %x to APB reg[%x]\n",value,adr);
}
}
else if(tmpbuf[0]=='r'){
adr=simple_strtoul(tmpbuf+2, NULL, 16);
if(buf[1]=='h'){
value = HDMIRX_ReadI2C_Byte(adr);
pr_info("HDMI reg[%x]=%x\n", adr, value);
}
else if(buf[1]=='c'){
value = READ_MPEG_REG(adr);
pr_info("CBUS reg[%x]=%x\n", adr, value);
}
else if(buf[1]=='p'){
value = READ_APB_REG(adr);
pr_info("APB reg[%x]=%x\n", adr, value);
}
}
return 16;
}示例15: tsdemux_init
s32 tsdemux_init(u32 vid, u32 aid, u32 sid)
{
s32 r;
u32 parser_sub_start_ptr;
u32 parser_sub_end_ptr;
u32 parser_sub_rp;
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
switch_mod_gate_by_type(MOD_DEMUX, 1);
#endif
parser_sub_start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
parser_sub_end_ptr = READ_MPEG_REG(PARSER_SUB_END_PTR);
parser_sub_rp = READ_MPEG_REG(PARSER_SUB_RP);
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER);
#ifdef ENABLE_DEMUX_DRIVER
tsdemux_reset();
#else
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER | RESET_DEMUXSTB);
WRITE_MPEG_REG(STB_TOP_CONFIG, 0);
WRITE_MPEG_REG(DEMUX_CONTROL, 0);
#endif
/* set PID filter */
printk("tsdemux video_pid = 0x%x, audio_pid = 0x%x, sub_pid = 0x%x\n",
vid, aid, sid);
#ifndef ENABLE_DEMUX_DRIVER
WRITE_MPEG_REG(FM_WR_DATA,
(((vid & 0x1fff) | (VIDEO_PACKET << 13)) << 16) |
((aid & 0x1fff) | (AUDIO_PACKET << 13)));
WRITE_MPEG_REG(FM_WR_ADDR, 0x8000);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(FM_WR_DATA,
(((sid & 0x1fff) | (SUB_PACKET << 13)) << 16) | 0xffff);
WRITE_MPEG_REG(FM_WR_ADDR, 0x8001);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(MAX_FM_COMP_ADDR, 1);
WRITE_MPEG_REG(STB_INT_MASK, 0);
WRITE_MPEG_REG(STB_INT_STATUS, 0xffff);
/* TS data path */
WRITE_MPEG_REG(FEC_INPUT_CONTROL, 0x7000);
WRITE_MPEG_REG(DEMUX_MEM_REQ_EN,
(1 << VIDEO_PACKET) |
(1 << AUDIO_PACKET) |
(1 << SUB_PACKET));
WRITE_MPEG_REG(DEMUX_ENDIAN,
(7 << OTHER_ENDIAN) |
(7 << BYPASS_ENDIAN) |
(0 << SECTION_ENDIAN));
WRITE_MPEG_REG(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE);
WRITE_MPEG_REG(TS_FILE_CONFIG,
(demux_skipbyte << 16) |
(6 << DES_OUT_DLY) |
(3 << TRANSPORT_SCRAMBLING_CONTROL_ODD) |
(1 << TS_HIU_ENABLE) |
(4 << FEC_FILE_CLK_DIV));
/* enable TS demux */
WRITE_MPEG_REG(DEMUX_CONTROL, (1 << STB_DEMUX_ENABLE) | (1 << KEEP_DUPLICATE_PACKAGE));
#endif
if (fetchbuf == 0) {
printk("%s: no fetchbuf\n", __FUNCTION__);
return -ENOMEM;
}
/* hook stream buffer with PARSER */
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(VLD_MEM_VIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(VLD_MEM_VIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_CONFIG,
(10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) |
(1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) |
(16 << PS_CFG_MAX_FETCH_CYCLE_BIT));
WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
//.........这里部分代码省略.........