本文整理汇总了C++中READ32函数的典型用法代码示例。如果您正苦于以下问题:C++ READ32函数的具体用法?C++ READ32怎么用?C++ READ32使用的例子?那么, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了READ32函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: nfs4_xdr_enc_cb_recall
static int
nfs4_xdr_enc_cb_recall(struct rpc_rqst *req, __be32 *p, struct nfs4_cb_recall *args)
{
struct xdr_stream xdr;
struct nfs4_cb_compound_hdr hdr = {
.ident = args->cbr_ident,
.nops = 1,
};
xdr_init_encode(&xdr, &req->rq_snd_buf, p);
encode_cb_compound_hdr(&xdr, &hdr);
return (encode_cb_recall(&xdr, args));
}
static int
decode_cb_compound_hdr(struct xdr_stream *xdr, struct nfs4_cb_compound_hdr *hdr){
__be32 *p;
READ_BUF(8);
READ32(hdr->status);
READ32(hdr->taglen);
READ_BUF(hdr->taglen + 4);
hdr->tag = (char *)p;
p += XDR_QUADLEN(hdr->taglen);
READ32(hdr->nops);
return 0;
}
示例2: nfs4_xdr_enc_cb_recall
static int
nfs4_xdr_enc_cb_recall(struct rpc_rqst *req, __be32 *p,
struct nfs4_rpc_args *rpc_args)
{
struct xdr_stream xdr;
struct nfs4_delegation *args = rpc_args->args_op;
struct nfs4_cb_compound_hdr hdr = {
.ident = args->dl_ident,
.minorversion = rpc_args->args_seq.cbs_minorversion,
};
xdr_init_encode(&xdr, &req->rq_snd_buf, p);
encode_cb_compound_hdr(&xdr, &hdr);
encode_cb_sequence(&xdr, &rpc_args->args_seq, &hdr);
encode_cb_recall(&xdr, args, &hdr);
encode_cb_nops(&hdr);
return 0;
}
static int
decode_cb_compound_hdr(struct xdr_stream *xdr, struct nfs4_cb_compound_hdr *hdr){
__be32 *p;
READ_BUF(8);
READ32(hdr->status);
READ32(hdr->taglen);
READ_BUF(hdr->taglen + 4);
hdr->tag = (char *)p;
p += XDR_QUADLEN(hdr->taglen);
READ32(hdr->nops);
return 0;
}
示例3: _hsmci_reset
static void _hsmci_reset(SIM_HBA *hba)
{
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci;
uintptr_t base;
ext = (SIM_MMC_EXT *)hba->ext;
hsmci = (hsmci_ext_t *)ext->handle;
base = hsmci->base;
int dtor = READ32(MCI_DTOR);
int mr = READ32(MCI_MR);
int sdcr = READ32(MCI_SDCR);
/* Reset and disable controller */
WRITE32 (MCI_CR, SWRST|PWSDIS);
delay (100);
WRITE32 (MCI_CR, MCIDIS | PWSDIS | MCIEN);
WRITE32(MCI_DMA, (READ32(MCI_DMA) & (~(DMAEN))));
WRITE32 (MCI_IDR, 0xffffffff);
WRITE32(MCI_DTOR, dtor);
WRITE32(MCI_MR, mr);
WRITE32(MCI_SDCR, sdcr);
}
示例4: FracSynthControlWord
void
evgEvtClk::setFracSynFreq(epicsFloat64 freq) {
epicsUInt32 controlWord, oldControlWord;
epicsFloat64 error;
controlWord = FracSynthControlWord (freq, MRF_FRAC_SYNTH_REF, 0, &error);
if ((!controlWord) || (error > 100.0)) {
char err[80];
sprintf(err, "Cannot set event clock speed to %f MHz.\n", freq);
std::string strErr(err);
throw std::runtime_error(strErr);
}
oldControlWord=READ32(m_pReg, FracSynthWord);
/* Changing the control word disturbes the phase of the synthesiser
which will cause a glitch. Don't change the control word unless needed.*/
if(controlWord != oldControlWord){
WRITE32(m_pReg, FracSynthWord, controlWord);
epicsUInt32 uSecDivider = (epicsUInt16)freq;
WRITE32(m_pReg, uSecDiv, uSecDivider);
}
m_fracSynFreq = FracSynthAnalyze(READ32(m_pReg, FracSynthWord), 24.0, 0);
}
示例5: _hsmci_pio_done
/*
* The real PIO transfer.
* Note:
* We only use PIO to read SCR and check/switch high speed mode, so only read operation is possible
*/
static int _hsmci_pio_done(SIM_HBA *hba, char *buf, int len, int dir)
{
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci;
uintptr_t base;
int i;
int timeout = TIMEOUT_LOOPS;
uint32_t *buf32 = (uint32_t *) buf;
ext = (SIM_MMC_EXT *)hba->ext;
hsmci = (hsmci_ext_t *)ext->handle;
base = hsmci->base;
// Make sure the data is ready
while (!(READ32(MCI_SR) & RXRDY) && timeout--);
if (dir == DATA_READ) {
for (i = 0; i < len; i+=4) {
*buf32++ = READ32(MCI_RDR);
delay(5);
}
} else {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "%s: We only support PIO read\n", __func__);
return -1;
}
clearFIFO (hba);
return len;
}
示例6: nfs4_xdr_enc_cb_recall
static int
nfs4_xdr_enc_cb_recall(struct rpc_rqst *req, __be32 *p,
struct nfsd4_callback *cb)
{
struct xdr_stream xdr;
struct nfs4_delegation *args = cb->cb_op;
struct nfs4_cb_compound_hdr hdr = {
.ident = cb->cb_clp->cl_cb_ident,
.minorversion = cb->cb_minorversion,
};
xdr_init_encode(&xdr, &req->rq_snd_buf, p);
encode_cb_compound_hdr(&xdr, &hdr);
encode_cb_sequence(&xdr, cb, &hdr);
encode_cb_recall(&xdr, args, &hdr);
encode_cb_nops(&hdr);
return 0;
}
static int
decode_cb_compound_hdr(struct xdr_stream *xdr, struct nfs4_cb_compound_hdr *hdr){
__be32 *p;
u32 taglen;
READ_BUF(8);
READ32(hdr->status);
/* We've got no use for the tag; ignore it: */
READ32(taglen);
READ_BUF(taglen + 4);
p += XDR_QUADLEN(taglen);
READ32(hdr->nops);
return 0;
}
示例7: READ16
int NormalIMBase::readHeader(const unsigned char *buf)
{
int pos=0;
senderVersion = READ16(buf+pos);
pos+=2;
sender = READ32(buf+pos);
pos+=4;
receiver = READ32(buf+pos);
pos+=4;
memcpy(fileSessionKey, buf+pos, 16);
pos+=16;
type = READ16(buf+pos);
pos+=2;
sequence = READ16(buf+pos);
pos+=2;
sendTime = READ32(buf+pos);
pos+=4;
senderFace = READ16(buf+pos);
pos+=2;
return pos;
}
示例8:
SeqRunMode
evgSeqRam::getRunMode() const {
if(READ32(m_pReg, SeqControl(m_id)) & EVG_SEQ_RAM_SINGLE)
return Single;
if(READ32(m_pReg, SeqControl(m_id)) & EVG_SEQ_RAM_RECYCLE)
return Auto;
else
return Normal;
}
示例9: uart_gnss_poll_out
/*
* @brief Output a character to serial port
*
* @param dev UART device struct
* @param c character to output
*/
unsigned char uart_gnss_poll_out(struct device *dev, unsigned char c)
{
/* wait for transmitter to ready to accept a character */
uint32_t status = READ32(&__UART1->status);
while (status & UART_STATUS_TX_FULL) {
status = READ32(&__UART1->status);
}
WRITE32(&__UART1->data, c);
return c;
}
示例10: uart_gnss_fifo_read
/**
* @brief Read data from FIFO
*
* @param dev UART device struct
* @param rx_data Pointer to data container
* @param size Container size
*
* @return Number of bytes read
*/
static int uart_gnss_fifo_read(struct device *dev, uint8_t *rx_data,
const int size)
{
uint32_t status = READ32(&__UART1->status);
uint8_t num_rx = 0;
while ((size - num_rx > 0) && ((status & UART_STATUS_RX_EMPTY) == 0)) {
rx_data[num_rx++] = (uint8_t)READ32(&__UART1->data);
status = READ32(&__UART1->status);
}
return num_rx;
}
示例11: create_RTcore_taskConfig
int create_RTcore_taskConfig( ST_STD_device *pSTDdev)
{
ST_RTcore* pRTcore;
unsigned int nval=0;
int status;
pRTcore = (ST_RTcore *)malloc(sizeof(ST_RTcore));
if( !pRTcore) return WR_ERROR;
pSTDdev->pUser = pRTcore;
pRTcore->fd_event = open("/dev/intLTU.0", O_RDWR|O_NDELAY);
if (pRTcore->fd_event < 0)
{
fprintf(stdout, "intLTU device open error !!!!!!\n");
return WR_ERROR;
}
pRTcore->base0 = (char *)mmap(0, 0x1000, PROT_READ|PROT_WRITE, MAP_SHARED, pRTcore->fd_event, 0);
if( pRTcore->base0 == 0x0) {
perror("mmap() error!");
close( pRTcore->fd_event );
return WR_ERROR;
}
status = ioctl(pRTcore->fd_event, IOCTL_CLTU_INTERRUPT_ENABLE, &nval);
nval = READ32(pRTcore->base0 + 0x0);
printf("0x0: 0x%x\n", (nval));
nval = READ32(pRTcore->base0 + 0x4);
printf("0x4: 0x%x\n", (nval));
nval = READ32(pRTcore->base0 + 0x8);
printf("0x8: 0x%x\n", (nval));
nval = READ32(pRTcore->base0 + 0xc);
printf("0xc: 0x%x\n", (nval));
// pRTcore->cntDAQ = 0;
pRTcore->cntDAQ_loop = 0;
pRTcore->cntAccum = 0;
/* pRTcore->daqStepTime = 0.00001; */
pRTcore->useScanIoRequest = 0;
/* pRTcore->clkStartTime = -15.0; */
return WR_OK;
}
示例12: READ32
epicsUInt32
EvrCML::countHigh() const
{
epicsUInt32 val = READ32(base, OutputCMLCount(N));
val >>= OutputCMLCount_high_shft;
return val & OutputCMLCount_mask;
}
示例13: FETCH
void i386_device::i486_cmpxchg_rm32_r32() // Opcode 0x0f b1
{
UINT8 modrm = FETCH();
if( modrm >= 0xc0 ) {
UINT32 dst = LOAD_RM32(modrm);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
STORE_RM32(modrm, src);
m_ZF = 1;
CYCLES(CYCLES_CMPXCHG_REG_REG_T);
} else {
REG32(EAX) = dst;
m_ZF = 0;
CYCLES(CYCLES_CMPXCHG_REG_REG_F);
}
} else {
UINT32 ea = GetEA(modrm,0);
UINT32 dst = READ32(ea);
UINT32 src = LOAD_REG32(modrm);
if( REG32(EAX) == dst ) {
WRITE32(ea, src);
m_ZF = 1;
CYCLES(CYCLES_CMPXCHG_REG_MEM_T);
} else {
REG32(EAX) = dst;
m_ZF = 0;
CYCLES(CYCLES_CMPXCHG_REG_MEM_F);
}
}
}
示例14: READ32
epicsUInt32
MRMCML::countLow () const
{
epicsUInt32 val = READ32(base, OutputCMLCount(N));
val >>= OutputCMLCount_low_shft;
return val & OutputCMLCount_mask;
}
示例15: _hsmci_wait_stat
static int _hsmci_wait_stat (SIM_HBA *hba, mmc_cmd_t *cmd)
{
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci;
uintptr_t base;
uint32_t mask = CMDRDY;
ext = (SIM_MMC_EXT *)hba->ext;
hsmci = (hsmci_ext_t *)ext->handle;
base = hsmci->base;
if (cmd->eflags & MMC_CMD_DATA) {
mask |= NOTBUSY | XFRDONE;
}
int timeout = TIMEOUT_LOOPS/100;
while (((READ32(MCI_SR) & mask) != mask) && timeout--)
nanospin_ns(100);
if (timeout <= 0) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: timeout on waiting for MCI_SR: 0x%x for CMD%d, mask: 0x%x", READ32(MCI_SR), cmd->opcode, mask);
return MMC_FAILURE;
}
return MMC_SUCCESS;
}