本文整理汇总了C++中PORT_PCR_MUX函数的典型用法代码示例。如果您正苦于以下问题：C++ PORT_PCR_MUX函数的具体用法？C++ PORT_PCR_MUX怎么用？C++ PORT_PCR_MUX使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了PORT_PCR_MUX函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: __pe_initialize_hardware
void __pe_initialize_hardware(void)
{
/*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
/*** ### MK21FN1M0VMC12 "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
/* Disable the WDOG module */
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
/* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */
WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG_STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
WDOG_STCTRLH_WAITEN_MASK |
WDOG_STCTRLH_STOPEN_MASK |
WDOG_STCTRLH_ALLOWUPDATE_MASK |
WDOG_STCTRLH_CLKSRC_MASK |
0x0100U;
#if MQX_ENABLE_LOW_POWER
/* Reset from LLWU wake up source */
if (_lpm_get_reset_source() == MQX_RESET_SOURCE_LLWU)
{
PMC_REGSC |= PMC_REGSC_ACKISO_MASK;
}
#endif
/* SIM_SCGC6: RTC=1 */
SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
if ((RTC_CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */
/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
RTC_CR &= (uint32_t)~(uint32_t)(
RTC_CR_SC2P_MASK |
RTC_CR_SC4P_MASK |
RTC_CR_SC8P_MASK |
RTC_CR_SC16P_MASK
);
/* RTC_CR: OSCE=1 */
RTC_CR |= RTC_CR_OSCE_MASK;
/* RTC_CR: CLKO=0 */
RTC_CR &= (uint32_t)~(uint32_t)(RTC_CR_CLKO_MASK);
}
/* System clock initialization */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x01) |
SIM_CLKDIV1_OUTDIV3(0x03) |
SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */
/* SIM_SCGC5: PORTD=1,PORTC=1,PORTA=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK |
SIM_SCGC5_PORTC_MASK |
SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=2,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
SIM_CLKDIV1_OUTDIV2(0x01) |
SIM_CLKDIV1_OUTDIV3(0x02) |
SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
/* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */
SIM_CLKDIV2 = (uint32_t)0x09UL; /* Update USB clock prescalers */
/* SIM_SOPT2: PLLFLLSEL=1 */
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=0 */
SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* PORTA_PCR19: ISF=0,MUX=0 */
PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* Switch to FBE Mode */
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK);
/* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=1,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC_CR = (OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK);
/* MCG_C7: OSCSEL=0 */
MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
/* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03));
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
MCG_C5 = MCG_C5_PRDIV0(0x01);
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=6 */
MCG_C6 = MCG_C6_VDIV0(0x06);
while((MCG_S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
}
while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x06));
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
}
/* Switch to PEE Mode */
/* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
//.........这里部分代码省略.........
示例2: SPI_Init
/***********************************************************************************************
功能：SPI 初始化
形参：SPI_InitStruct SPI 初始化结构
返回：0
详解：0
************************************************************************************************/
void SPI_Init(SPI_InitTypeDef* SPI_InitStruct)
{
SPI_Type *SPIx = NULL;
PORT_Type *SPI_PORT = NULL;
SPI_DataMapTypeDef *pSPI_DataMap = (SPI_DataMapTypeDef*)&(SPI_InitStruct->SPIxDataMap);
SPI_CSMapTypeDef *pSPI_CSMap = (SPI_CSMapTypeDef*)&(SPI_InitStruct->SPIxPCSMap);
//参数检测
assert_param(IS_SPI_DATA_CHL(SPI_InitStruct->SPIxDataMap));
assert_param(IS_SPI_PCS_CHL(SPI_InitStruct->SPIxPCSMap));
assert_param(IS_SPI_BAUDRATE(SPI_InitStruct->SPI_BaudRatePrescaler));
assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
assert_param(IS_SPI_FIRSTBIT(SPI_InitStruct->SPI_FirstBit));
//找出SPI模块 开SPI模块时钟
switch(pSPI_DataMap->SPI_Index)
{
case 0:
SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
SPIx = SPI0;
break;
case 1:
SIM->SCGC6 |= SIM_SCGC6_SPI1_MASK;
SPIx = SPI1;
break;
case 2:
SIM->SCGC3 |= SIM_SCGC3_SPI2_MASK;
SPIx = SPI2;
break;
default:break;
}
//找出对应的PORT
switch(pSPI_DataMap->SPI_GPIO_Index)
{
case 0:
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
SPI_PORT = PORTA;
break;
case 1:
SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;
SPI_PORT = PORTB;
break;
case 2:
SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
SPI_PORT = PORTC;
break;
case 3:
SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
SPI_PORT = PORTD;
break;
case 4:
SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
SPI_PORT = PORTE;
break;
default:break;
}
//开启对应的引脚 SCK SOUT SIN
SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index] &= ~PORT_PCR_MUX_MASK;
SPI_PORT->PCR[pSPI_DataMap->SPI_SIN_Pin_Index] &= ~PORT_PCR_MUX_MASK;
SPI_PORT->PCR[pSPI_DataMap->SPI_SOUT_Pin_Index] &= ~PORT_PCR_MUX_MASK;
SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
SPI_PORT->PCR[pSPI_DataMap->SPI_SIN_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
SPI_PORT->PCR[pSPI_DataMap->SPI_SOUT_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
/*SCK配置开漏*/
SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index]|= PORT_PCR_ODE_MASK;
//配置PCS
//找出对应的PORT
switch(pSPI_CSMap->SPI_GPIO_Index)
{
case 0:
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
SPI_PORT = PORTA;
break;
case 1:
SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;
SPI_PORT = PORTB;
break;
case 2:
SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
SPI_PORT = PORTC;
break;
case 3:
SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
SPI_PORT = PORTD;
break;
case 4:
SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
SPI_PORT = PORTE;
break;
default:break;
}
SPI_PORT->PCR[pSPI_CSMap->SPI_PCS_Pin_Index] &= ~PORT_PCR_MUX_MASK;
//.........这里部分代码省略.........
示例3: TWRK40_flexbus_init
void TWRK40_flexbus_init(void){
/* Enable the FlexBus */
/* Configure the FlexBus Registers for 8-bit port size */
/* with multiplexed address and data using chip select 0 */
/* These configurations are specific to communicating with */
/* the MRAM used in this example */
/* For K40 tower module - use the byte lane shift because there */
/* is a latch on the board which handles multiplexed address/data */
//Set Base address
FB_CSAR0 = (uint32)&MRAM_START_ADDRESS;
FB_CSCR0 = FB_CSCR_BLS_MASK // set byte lane shift for data on FB_AD[7:0] aka. right justified mode
| FB_CSCR_PS(1) // 8-bit port
| FB_CSCR_AA_MASK // auto-acknowledge
| FB_CSCR_ASET(0x1) // assert chip select on second clock edge after address is asserted
| FB_CSCR_WS(0x1) // 1 wait state - may need a wait state depending on the bus speed
;
FB_CSMR0 = FB_CSMR_BAM(0x7) //Set base address mask for 512K address space
| FB_CSMR_V_MASK //Enable cs signal
;
//enable BE signals - note, not used in this example
FB_CSPMCR = 0x02200000;
//fb clock divider 3
SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x3);
/* Configure the pins needed to FlexBus Function (Alt 5) */
/* this example uses low drive strength settings */
//address/Data
PORTA_PCR7=PORT_PCR_MUX(5); //fb_ad[18]
PORTA_PCR8=PORT_PCR_MUX(5); //fb_ad[17]
PORTA_PCR9=PORT_PCR_MUX(5); //fb_ad[16]
PORTA_PCR10=PORT_PCR_MUX(5); //fb_ad[15]
PORTA_PCR24=PORT_PCR_MUX(5); //fb_ad[14]
PORTA_PCR25=PORT_PCR_MUX(5); //fb_ad[13]
PORTA_PCR26=PORT_PCR_MUX(5); //fb_ad[12]
PORTA_PCR27=PORT_PCR_MUX(5); //fb_ad[11]
PORTA_PCR28=PORT_PCR_MUX(5); //fb_ad[10]
PORTD_PCR10=PORT_PCR_MUX(5); //fb_ad[9]
PORTD_PCR11=PORT_PCR_MUX(5); //fb_ad[8]
PORTD_PCR12=PORT_PCR_MUX(5); //fb_ad[7]
PORTD_PCR13=PORT_PCR_MUX(5); //fb_ad[6]
PORTD_PCR14=PORT_PCR_MUX(5); //fb_ad[5]
PORTE_PCR8=PORT_PCR_MUX(5); //fb_ad[4]
PORTE_PCR9=PORT_PCR_MUX(5); //fb_ad[3]
PORTE_PCR10=PORT_PCR_MUX(5); //fb_ad[2]
PORTE_PCR11=PORT_PCR_MUX(5); //fb_ad[1]
PORTE_PCR12=PORT_PCR_MUX(5); //fb_ad[0]
//control signals
PORTA_PCR11=PORT_PCR_MUX(5); //fb_oe_b
PORTD_PCR15=PORT_PCR_MUX(5); //fb_rw_b
PORTE_PCR7=PORT_PCR_MUX(5); //fb_cs0_b
PORTE_PCR6=PORT_PCR_MUX(5); //fb_ale
}示例4: LCD_setup
// Setup
inline void LCD_setup()
{
// Register Scan CLI dictionary
CLI_registerDictionary( lcdCLIDict, lcdCLIDictName );
// Initialize SPI
SPI_setup();
// Setup Register Control Signal (A0)
// Start in display register mode (1)
GPIOC_PDDR |= (1<<7);
PORTC_PCR7 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
GPIOC_PSOR |= (1<<7);
// Setup LCD Reset pin (RST)
// 0 - Reset, 1 - Normal Operation
// Start in normal mode (1)
GPIOC_PDDR |= (1<<8);
PORTC_PCR8 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
GPIOC_PSOR |= (1<<8);
// Run LCD intialization sequence
LCD_initialize();
// Write default image to LCD
for ( uint8_t page = 0; page < LCD_TOTAL_VISIBLE_PAGES; page++ )
LCD_writeDisplayReg( page, (uint8_t*)&STLcdDefaultImage[page * LCD_PAGE_LEN], LCD_PAGE_LEN );
// Setup Backlight
SIM_SCGC6 |= SIM_SCGC6_FTM0;
FTM0_CNT = 0; // Reset counter
// PWM Period
// 16-bit maximum
FTM0_MOD = 0xFFFF;
// Set FTM to PWM output - Edge Aligned, Low-true pulses
FTM0_C0SC = 0x24; // MSnB:MSnA = 10, ELSnB:ELSnA = 01
FTM0_C1SC = 0x24;
FTM0_C2SC = 0x24;
// Base FTM clock selection (72 MHz system clock)
// @ 0xFFFF period, 72 MHz / (0xFFFF * 2) = Actual period
// Higher pre-scalar will use the most power (also look the best)
// Pre-scalar calculations
// 0 - 72 MHz -> 549 Hz
// 1 - 36 MHz -> 275 Hz
// 2 - 18 MHz -> 137 Hz
// 3 - 9 MHz -> 69 Hz (Slightly visible flicker)
// 4 - 4 500 kHz -> 34 Hz (Visible flickering)
// 5 - 2 250 kHz -> 17 Hz
// 6 - 1 125 kHz -> 9 Hz
// 7 - 562 500 Hz -> 4 Hz
// Using a higher pre-scalar without flicker is possible but FTM0_MOD will need to be reduced
// Which will reduce the brightness range
// System clock, /w prescalar setting
FTM0_SC = FTM_SC_CLKS(1) | FTM_SC_PS( STLcdBacklightPrescalar_define );
// Red
FTM0_C0V = STLcdBacklightRed_define;
PORTC_PCR1 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(4);
// Green
FTM0_C1V = STLcdBacklightGreen_define;
PORTC_PCR2 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(4);
// Blue
FTM0_C2V = STLcdBacklightBlue_define;
PORTC_PCR3 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(4);
}示例5: PE_low_level_init
/*
** ===================================================================
** Method : PE_low_level_init (component MK20DX128EX5)
**
** Description :
** Initializes beans and provides common register initialization.
** The method is called automatically as a part of the
** application initialization code.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
#ifdef PEX_RTOS_INIT
PEX_RTOS_INIT(); /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */
#endif
/* Initialization of the SIM module */
/* PORTA_PCR4: ISF=0,MUX=7 */
PORTA_PCR4 = (uint32_t)((PORTA_PCR4 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK
)) | (uint32_t)(
PORT_PCR_MUX(0x07)
));
/* Initialization of the RCM module */
/* RCM_RPFW: RSTFLTSEL=0 */
RCM_RPFW &= (uint8_t)~(uint8_t)(RCM_RPFW_RSTFLTSEL(0x1F));
/* RCM_RPFC: RSTFLTSS=0,RSTFLTSRW=0 */
RCM_RPFC &= (uint8_t)~(uint8_t)(
RCM_RPFC_RSTFLTSS_MASK |
RCM_RPFC_RSTFLTSRW(0x03)
);
/* Initialization of the FTFL_FlashConfig module */
/* Initialization of the PMC module */
/* PMC_REGSC: ACKISO=0,BGBE=0 */
PMC_REGSC &= (uint8_t)~(uint8_t)(
PMC_REGSC_ACKISO_MASK |
PMC_REGSC_BGBE_MASK
);
/* PMC_LVDSC1: LVDACK=1,LVDIE=0,LVDRE=1,LVDV=0 */
PMC_LVDSC1 = (uint8_t)((PMC_LVDSC1 & (uint8_t)~(uint8_t)(
PMC_LVDSC1_LVDIE_MASK |
PMC_LVDSC1_LVDV(0x03)
)) | (uint8_t)(
PMC_LVDSC1_LVDACK_MASK |
PMC_LVDSC1_LVDRE_MASK
));
/* PMC_LVDSC2: LVWACK=1,LVWIE=0,LVWV=0 */
PMC_LVDSC2 = (uint8_t)((PMC_LVDSC2 & (uint8_t)~(uint8_t)(
PMC_LVDSC2_LVWIE_MASK |
PMC_LVDSC2_LVWV(0x03)
)) | (uint8_t)(
PMC_LVDSC2_LVWACK_MASK
));
/* SMC_PMPROT: ??=0,??=0,AVLP=0,??=0,ALLS=0,??=0,AVLLS=0,??=0 */
SMC_PMPROT = 0x00U; /* Setup Power mode protection register */
/* Common initialization of the CPU registers */
/* NVICIP8: PRI8=0 */
NVICIP8 = NVIC_IP_PRI8(0x00);
/* ### InternalI2C "I2C" init code ... */
I2C_Init();
/* ### Serial_LDD "IO1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
(void)IO1_Init(NULL);
/* ### PWM_LDD "PwmLdd1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
(void)PwmLdd1_Init(NULL);
/* ### PWM_LDD "PwmLdd2" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
(void)PwmLdd2_Init(NULL);
/* ### PWM_LDD "PwmLdd3" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
(void)PwmLdd3_Init(NULL);
/* ### RealTime_LDD "RealTimeLdd1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
(void)RealTimeLdd1_Init(NULL);
/* ### Asynchro serial "Inhr1" init code ... */
Inhr1_Init();
/* ### "AS1" init code ... */
/* Enable interrupts of the given priority level */
Cpu_SetBASEPRI(0U);
}示例6: CANInit
//============================================================================
//函数名称：CANInit
//函数返回：0：成功；1：失败
//参数说明：
// CANChannel：模块号
// baudrateKHz: 波特率
// selfLoop: 模式选择(1=回环模式；0=正常模式)
// idMask: ID过滤(1=ID过滤；0=ID不过滤)
//功能概要：CAN初始化
//============================================================================
uint8 CANInit(uint8 CANChannel,uint32 baudrateKHz,uint8 selfLoop,uint8 idMask)
{
int8 i;
CAN_MemMapPtr CANBaseAdd;
//使能FlexCAN外部时钟
OSC_CR |= OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK;
//通过模块号选择模块基地址
if(CANChannel == 0)
CANBaseAdd = CAN0_BASE_PTR;
else if(CANChannel == 1)
CANBaseAdd = CAN1_BASE_PTR;
//使能CAN模块时钟
if(CANBaseAdd == CAN0_BASE_PTR)
SIM_SCGC6 |= SIM_SCGC6_FLEXCAN0_MASK;//使能CAN0的时钟模块
else
SIM_SCGC3 |= SIM_SCGC3_FLEXCAN1_MASK;//使能CAN1的时钟模块
//使能CAN中断
if(CANChannel == 0)//使能CAN0的中断
{
NVICICPR0 = (NVICICPR0 & ~(0x07<<29)) | (0x07<<29);//清除挂载在FlexCAN0的中断
NVICISER0 = (NVICISER0 & ~(0x07<<29)) | (0x07<<29);//使能FlexCAN0中断
NVICICPR1 = (NVICICPR1 & ~(0x1F<<0)) | (0x1F);//清除挂载在FlexCAN0的中断
NVICISER1 = (NVICISER1 & ~(0x1F<<0)) | (0x1F);//使能FlexCAN0中断
}
else //使能CAN1的中断
{
NVICICPR1 = (NVICICPR1 & ~(0xFF<<5)) | (0xFF<<5);//清除挂载在FlexCAN1的中断
NVICISER1 = (NVICISER1 & ~(0xFF<<5)) | (0xFF<<5);//使能FlexCAN1中断
}
//配置CAN_RX/TX复用引脚功能
if(CANChannel == 0)
{
PORTA_PCR12 = PORT_PCR_MUX(2) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; //上拉
PORTA_PCR13 = PORT_PCR_MUX(2) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; //上拉
}
else
{
PORTE_PCR24 = PORT_PCR_MUX(2) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; //Tx上拉
PORTE_PCR25 = PORT_PCR_MUX(2) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; //Rx上拉
}
//选择时钟源，外设时钟48MHz，内部时钟：12MHz
CAN_CTRL1_REG(CANBaseAdd) |= CAN_CTRL1_CLKSRC_MASK;//选择内部时钟
CAN_MCR_REG(CANBaseAdd) |= CAN_MCR_FRZ_MASK; //使能冻结模式
CAN_MCR_REG(CANBaseAdd) &= ~CAN_MCR_MDIS_MASK;//使能CAN模块
//确认已退出冻结模式
while((CAN_MCR_LPMACK_MASK & CAN_MCR_REG(CANBaseAdd)));
//软件复位
CAN_MCR_REG(CANBaseAdd) ^= CAN_MCR_SOFTRST_MASK;
//等待复位完成
while(CAN_MCR_SOFTRST_MASK & CAN_MCR_REG(CANBaseAdd));
//等待进入冻结模式
while(!(CAN_MCR_FRZACK_MASK & CAN_MCR_REG(CANBaseAdd)));
//将16个邮箱缓冲区内容清0
for(i=0;i<16;i++)
{
CANBaseAdd->MB[i].CS = 0x00000000;
CANBaseAdd->MB[i].ID = 0x00000000;
CANBaseAdd->MB[i].WORD0 = 0x00000000;
CANBaseAdd->MB[i].WORD1 = 0x00000000;
}
//接收邮箱过滤IDE比较，RTR不比较
CAN_CTRL2_REG(CANBaseAdd) &= ~CAN_CTRL2_EACEN_MASK;
//远程请求帧产生
CAN_CTRL2_REG(CANBaseAdd) &= ~CAN_CTRL2_RRS_MASK;
//邮箱首先从接收FIFO队列匹配然后再在邮箱中匹配
CAN_CTRL2_REG(CANBaseAdd) &= ~CAN_CTRL2_MRP_MASK;
//使用一个32位过滤器
CAN_MCR_REG(CANBaseAdd) |= (CAN_MCR_REG(CANBaseAdd) & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0);
//设置波特率
if(SetCANBand(CANChannel,baudrateKHz) == 1)//若设置错误
return 1;
//模式选择：回环模式或正常模式
if(1==selfLoop)
CAN_CTRL1_REG(CANBaseAdd) |= CAN_CTRL1_LPB_MASK;//使用回环模式
//初始化掩码寄存器
if(1==idMask)//屏蔽ID
//.........这里部分代码省略.........
示例7: spi_init
/**
* @brief SPI初始化
*
* @param spino SPI通道号
* @param master 是否是主机
*
* @return E_ID 输入序号错误
* @return E_OK 初始化正常
*/
ER spi_init(uint8_t spino, uint8_t master)
{
if((spino < 0) || (spino > SPI_NO_GET(SPI2)))
{
return (E_ID);
}
SPI_MemMapPtr base_addr = spi_get_base_address(spino);
/* 使能SPI模块时钟，配置SPI引脚功能 */
if(SPI_MOD_SET(spino) == SPI0)
{
SIM_SCGC6 |= SIM_SCGC6_DSPI0_MASK;
/* PORT_PCR_MUX(0x2) ： SPI功能
* PORT_PCR_DSE_MASK ： Drive Strength Enable */
gpio_init(PORT_NO_GET(SD_CS), PIN_NO_GET(SD_CS), OUT_PUT, HIGH_POWER); /* PCS0 */
PORTA_PCR15 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* SCK */
PORTA_PCR16 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* SOUT */
PORTA_PCR17 = 0 | PORT_PCR_MUX(0x2); /* SIN */
}
else if(SPI_MOD_SET(spino) == SPI1)
{
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
PORTE_PCR4 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* PCS0 */
PORTE_PCR2 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* SCK */
PORTE_PCR1 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* SOUT */
PORTE_PCR3 = 0 | PORT_PCR_MUX(0x2); /* SIN */
}
else
{
SIM_SCGC3 |= SIM_SCGC3_SPI2_MASK;
}
SPI_MCR_REG(base_addr) = 0
| SPI_MCR_CLR_TXF_MASK /* Clear the Tx FIFO counter. */
| SPI_MCR_CLR_RXF_MASK /* Clear the Rx FIFO counter. */
| SPI_MCR_HALT_MASK; /* Starts and stops DSPI transfers */
/* 根据主从机模式设置工作模式 */
if(master == MASTER)
{
SPI_MCR_REG(base_addr) |= SPI_MCR_MSTR_MASK; /* Master/Slave Mode Select */
SPI_CTAR_REG(base_addr,0) = 0
| SPI_CTAR_DBR_MASK /* Double Baud Rate */
| SPI_CTAR_FMSZ(0x07) /* Frame Size： 8bit */
| SPI_CTAR_PDT_MASK /* 延时因子为7 */
| SPI_CTAR_BR(0x8); /* Selects the scaler value for the baud rate. */
//| SPI_CTAR_CPOL_MASK; /* Clock Polarity */
//| SPI_CTAR_CPHA_MASK; /* Clock Phase */
}
else
{
SPI_CTAR_SLAVE_REG(base_addr,0) = 0
| SPI_CTAR_SLAVE_FMSZ(0x07)
| SPI_CTAR_SLAVE_CPOL_MASK
| SPI_CTAR_SLAVE_CPHA_MASK;
}
SPI_SR_REG(base_addr) = SPI_SR_EOQF_MASK /* End of Queue Flag */
| SPI_SR_TFUF_MASK /* Transmit FIFO Underflow Flag */
| SPI_SR_TFFF_MASK /* Transmit FIFO Fill Flag */
| SPI_SR_RFOF_MASK /* Receive FIFO Overflow Flag */
| SPI_SR_RFDF_MASK; /* Receive FIFO Drain Flag */
SPI_MCR_REG(base_addr) &= ~SPI_MCR_HALT_MASK; /* start */
return (E_OK);
}示例8: gpio_enable_button_flag
void gpio_enable_button_flag(OS_TID task, U16 flags)
{
// When the "reset" button is pressed the ISR will set the
// event flags "flags" for task "task"
// Keep a local copy of task & flags
//isr_notify=task;
//isr_flags=flags;
PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] |= PORT_PCR_ISF_MASK;
//sw2 - interrupt on falling edge
PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK|PORT_PCR_PE_MASK|PORT_PCR_PFE_MASK|PORT_PCR_IRQC(10)|PORT_PCR_MUX(1);
NVIC_ClearPendingIRQ(PORTB_IRQn);
NVIC_EnableIRQ(PORTB_IRQn);
}示例9: PORTB_IRQHandler
void PORTB_IRQHandler(void)
{
if (PIN_nRESET_PORT->ISFR == (1<<PIN_nRESET_BIT))
{
PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] |= PORT_PCR_ISF_MASK;
// Notify a task that the button has been pressed
// disable interrupt
PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK|PORT_PCR_PE_MASK|PORT_PCR_PFE_MASK|PORT_PCR_IRQC(00)|PORT_PCR_MUX(1); // IRQ Falling edge
//isr_evt_set(isr_flags, isr_notify);
}
}示例10: AS1_Init
/* ===================================================================*/
LDD_TDeviceData* AS1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate device structure */
AS1_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
/* Allocate interrupt vectors */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_UART0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
/* SIM_SCGC4: UART0=1 */
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
/* PORTA_PCR1: ISF=0,MUX=2 */
PORTA_PCR1 = (uint32_t)((PORTA_PCR1 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* PORTE_PCR20: ISF=0,MUX=4 */
PORTE_PCR20 = (uint32_t)((PORTE_PCR20 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x03)
)) | (uint32_t)(
PORT_PCR_MUX(0x04)
));
/* NVIC_IPR3: PRI_12=0x80 */
NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_12(0x7F)
)) | (uint32_t)(
NVIC_IP_PRI_12(0x80)
));
/* NVIC_ISER: SETENA|=0x1000 */
NVIC_ISER |= NVIC_ISER_SETENA(0x1000);
UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */
/* UART0_C1: LOOPS=0,DOZEEN=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
UART0_C1 = 0x00U; /* Set the C1 register */
/* UART0_C3: R8T9=0,R9T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
UART0_C3 = 0x00U; /* Set the C3 register */
/* UART0_C4: MAEN1=0,MAEN2=0,M10=0,OSR=0 */
UART0_C4 = UART0_C4_OSR(0x00); /* Set the C4 register */
/* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
UART0_S2 = 0x00U; /* Set the S2 register */
UART0_PDD_SetClockSource(UART0_BASE_PTR, UART0_PDD_PLL_FLL_CLOCK);
UART0_PDD_SetBaudRate(UART0_BASE_PTR, 137U); /* Set the baud rate register. */
UART0_PDD_SetOversamplingRatio(UART0_BASE_PTR, 3U);
UART0_PDD_EnableSamplingOnBothEdges(UART0_BASE_PTR, PDD_ENABLE);
UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_ENABLE); /* Enable transmitter */
UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_ENABLE); /* Enable receiver */
UART0_PDD_EnableInterrupt(UART0_BASE_PTR, ( UART0_PDD_INTERRUPT_RECEIVER )); /* Enable interrupts */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_AS1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv);
}示例11: board_init
void board_init() {
uint16_t i,j;
//enable all port clocks.
SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK
| SIM_SCGC5_PORTB_MASK
| SIM_SCGC5_PORTC_MASK
| SIM_SCGC5_PORTD_MASK
| SIM_SCGC5_PORTE_MASK );
//init all pins for the radio
//SLPTR
#ifdef TOWER_K20
PORTB_PCR3 = PORT_PCR_MUX(1);// -- PTB3 used as gpio for slptr
GPIOB_PDDR |= RADIO_SLPTR_MASK; //set as output
//RADIO RST -- TODO in the TWR change it to another pin! this is one of the leds.
PORTC_PCR9 = PORT_PCR_MUX(1);// -- PTC9 used as gpio for radio rst
GPIOC_PDDR |= RADIO_RST_MASK; //set as output
#elif OPENMOTE_K20
PORTD_PCR4 = PORT_PCR_MUX(1);// -- PTD4 used as gpio for slptr
GPIOD_PDDR |= RADIO_SLPTR_MASK; //set as output
//RADIO RST
PORTD_PCR5 = PORT_PCR_MUX(1);// -- PTD5 used as gpio for radio rst
GPIOD_PDDR |= RADIO_RST_MASK; //set as output
#endif
PORT_PIN_RADIO_RESET_LOW();//activate the radio.
PORT_PIN_RADIO_SLP_TR_CNTL_LOW();
//ptc5 .. ptc5 is pin 62, irq A
enable_irq(RADIO_EXTERNAL_PORT_IRQ_NUM);//enable the irq. The function is mapped to the vector at position 105 (see manual page 69). The vector is in isr.h
//external port radio_isr.
PORTC_PCR5 = PORT_PCR_MUX(1);// -- PTC5 used as gpio for radio isr through llwu
GPIOC_PDDR &= ~1<<RADIO_ISR_PIN; //set as input ==0
PORTC_PCR5 |= PORT_PCR_IRQC(0x09); //9 interrupt on raising edge. page 249 of the manual.
PORTC_PCR5 |= PORT_PCR_ISF_MASK; //clear any pending interrupt.
llwu_init();//low leakage unit init - to recover from deep sleep
debugpins_init();
leds_init();
bsp_timer_init();
uart_init();
radiotimer_init();
spi_init();
radio_init();
leds_all_off();
leds_sync_on();
leds_radio_on();
leds_debug_on();
leds_error_on();
leds_all_off();
debugpins_fsm_clr();
}示例12: cfgPorts
//--------------------------------------------------------------
void cfgPorts(void)
{
//Turn on clock for portb and portd
SIM_SCGC5 = SIM_SCGC5_PORTB_MASK;
SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;
SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK;
/* Set pins of PORTB as GPIO */
//Connected to LCD
PORTC_PCR0 = PORT_PCR_MUX(1);
PORTC_PCR1 = PORT_PCR_MUX(1);
PORTC_PCR2 = PORT_PCR_MUX(1);
PORTC_PCR3 = PORT_PCR_MUX(1);
PORTC_PCR4 = PORT_PCR_MUX(1);
PORTC_PCR5 = PORT_PCR_MUX(1);
PORTC_PCR6 = PORT_PCR_MUX(1);
PORTC_PCR7 = PORT_PCR_MUX(1);
//LCD: RS and Enable
PORTB_PCR0 = PORT_PCR_MUX(1);
PORTB_PCR1 = PORT_PCR_MUX(1);
//Leds on board
PORTB_PCR18 = PORT_PCR_MUX(1);
PORTB_PCR19 = PORT_PCR_MUX(1);
PORTD_PCR1 = PORT_PCR_MUX(1);
//Configure all PortB as outputs
GPIOB_PDDR = 0xFFFFFFFF; //1111 1111 1111 1111 1111 1111 1111 0111
//Configure all PortD as outputs
GPIOC_PDDR = 0xFFFFFFFF;
//Configure all PortD as outputs
GPIOD_PDDR = 0xFFFFFFFF;
}示例13: _pwm_init
//.........这里部分代码省略.........
/* chose clock source is A */
pwm->PWMCLK = 0x00;
/* No Concatenates */
pwm->PWMCTL = 0x00;
/* Enable PWM */
pwm->PWME = 0x02;
#endif
/* Initialize PWM module for CFV1 families */
#if (defined BSP_TWRMCF51JE)||(defined BSP_TWRMCF51MM)||(defined BSP_MCF51JMEVB)
#if (defined BSP_TWRMCF51JE)
VMCF51JE_TPM_STRUCT_PTR tpm = &(((MCF51JE_STRUCT_PTR)_PSP_GET_MBAR())->TPM2);
VMCF51JE_STRUCT_PTR reg_ptr = _PSP_GET_MBAR();
#endif
#if (defined BSP_TWRMCF51MM)
VMCF51MM_TPM_STRUCT_PTR tpm = &(((MCF51MM_STRUCT_PTR)_PSP_GET_MBAR())->TPM2);
VMCF51MM_STRUCT_PTR reg_ptr = _PSP_GET_MBAR();
#endif
#if (defined BSP_MCF51JMEVB)
VMCF51JM_TPM2_STRUCT_PTR tpm = &(((MCF51JM_STRUCT_PTR)_PSP_GET_MBAR())->TPM2);
VMCF51JM_STRUCT_PTR reg_ptr = _PSP_GET_MBAR();
reg_ptr->SIMX.SCGC1 |= MCF51XX_SCGC1_TPM2_MASK;
#else
reg_ptr->SIM.SCGC1 |= MCF51XX_SCGC1_TPM2_MASK;
#endif
/* update duty */
duty = (uint_16*)(&(tpm->TPMxC[0].TPMxCyV));
tpm->TPMxSC = 0;
tpm->TPMxMOD = 0xFF;
tpm->TPMxC[0].TPMxCySC = 0x24;
tpm->TPMxSC = 0x08;
#endif
/* Initialize PWM module for kinetis families */
#if (defined BSP_TWR_K40X256) || (defined BSP_TWR_K60N512) || (defined BSP_TWR_K53N512)
duty = (uint_8 *)&(FTM0_C0V);
/* FTM0_CH0 enable on PTA3 ****/
PORTC_PCR1 = PORT_PCR_MUX(0x4);
/* Enable clock for FTM */
SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK;
/* Set FTM mode */
FTM0_MODE = (FTM_MODE_WPDIS_MASK | FTM_MODE_FTMEN_MASK);
FTM0_MODE &= ~FTM_MODE_FTMEN_MASK;
FTM0_SC = 0;
FTM0_CNTIN = 0x00;
/* Set FTM modular */
FTM0_MOD = 0xFF;
FTM0_QDCTRL &= ~(FTM_QDCTRL_QUADEN_MASK);
FTM0_COMBINE &= ~(FTM_COMBINE_DECAPEN0_MASK \
|FTM_COMBINE_DECAPEN1_MASK \
|FTM_COMBINE_DECAPEN2_MASK \
|FTM_COMBINE_DECAPEN3_MASK \
|FTM_COMBINE_COMBINE0_MASK \
|FTM_COMBINE_COMBINE1_MASK \
|FTM_COMBINE_COMBINE2_MASK \
|FTM_COMBINE_COMBINE3_MASK);
FTM0_C0SC = 0x28;
/* Enable FTM */
FTM0_SC = 0x08;
#endif
#if (defined BSP_TWRMCF51JF)
volatile MXC_MemMapPtr mxc;
volatile FTM_MemMapPtr ftm1;
mxc = MXC_BASE_PTR;
ftm1 = FTM1_BASE_PTR;
duty = (uint_16_ptr)&(ftm1->CHANNEL[0].CVH);
mxc->PTAPF4 &= ~MXC_PTAPF4_A0(0xF);
mxc->PTAPF4 |= MXC_PTAPF4_A0(0x4);
/* Init counter value*/
ftm1->CNTH = 0x00;
ftm1->CNTL = 0x00;
/* Set Modulo -> free run mode*/
ftm1->MODH = 0x00;
ftm1->MODL = 0xFF;
/* Disable dual capture mode and combine channels */
ftm1->COMBINE[0] &= ~(FTM_COMBINE_DECAPEN_MASK | FTM_COMBINE_COMBINE_MASK);
/* Select channel 0 to generate PWM signal */
ftm1->CHANNEL[0].CSC |= FTM_CSC_MSB_MASK;
ftm1->CHANNEL[0].CSC |= FTM_CSC_ELSB_MASK;
ftm1->CHANNEL[0].CSC &= ~FTM_CSC_ELSA_MASK;
/* Start timer */
ftm1->SC = 0x08;
#endif
}示例14: InitSSD1325_Interface
//This should any pin I/O setup
void InitSSD1325_Interface()
{
PORTD_PCR4 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
PORTC_PCR8 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
PORTA_PCR1 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
PORTB_PCR3 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
PORTB_PCR2 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
PORTC_PCR3 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
PORTC_PCR4 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
PORTA_PCR12 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
PORTA_PCR2 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
PORTC_PCR2 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
PORTD_PCR2 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
PORTD_PCR3 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
PORTD_PCR1 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
GPIOD_PDDR |= 1<<4; //DC Signal
GPIOC_PDDR |= 1<<8; //RW Signal
GPIOA_PDDR |= 1<<1; //E Signal
GPIOB_PDDR |= (1<<3) | (1<<2); //Reset and CS signal
SSD1325_SET_RESET;
SSD1325_SET_CS;
SSD1325_CLEAR_DC;
SSD1325_CLEAR_RW;
SSD1325_CLEAR_E;
SetSSD1325_DataBusAsInputs();
}示例15: FTM2_CH1_PWM_Start
void FTM2_CH1_PWM_Start(unsigned long u16DutyCycle)
{
FTM2_C1V = u16DutyCycle;
FTM2_PWMCH1_PORT = PORT_PCR_MUX(3); //Enables PWM Output
FTM2_SC |= FTM_SC_CLKS(1); //System clock on FTM2, start generating PWM
}