C++ PA函数代码示例

struct platform_device *__init at32_add_device_twi(unsigned int id)
{
	struct platform_device *pdev;

	if (id != 0)
		return NULL;

	pdev = platform_device_alloc("atmel_twi", id);
	if (!pdev)
		return NULL;

	if (platform_device_add_resources(pdev, atmel_twi0_resource,
				ARRAY_SIZE(atmel_twi0_resource)))
		goto err_add_resources;

	select_peripheral(PA(6),  PERIPH_A, 0);	/* SDA	*/
	select_peripheral(PA(7),  PERIPH_A, 0);	/* SDL	*/

	atmel_twi0_pclk.dev = &pdev->dev;

	platform_device_add(pdev);
	return pdev;

err_add_resources:
	platform_device_put(pdev);
	return NULL;
}

 void pade (gf_view<refreq> &gr, gf_view<imfreq> const &gw, int n_points, double freq_offset) {

  // make sure the GFs have the same structure
  //assert(gw.shape() == gr.shape());

  // copy the tail. it doesn't need to conform to the pade approximant
  gr.singularity() = gw.singularity();

  auto sh = gw.data().shape().front_pop();
  int N1 = sh[0], N2 = sh[1];
  for (int n1=0; n1<N1; n1++) {
    for (int n2=0; n2<N2; n2++) {

      arrays::vector<dcomplex> z_in(n_points); // complex points
      arrays::vector<dcomplex> u_in(n_points); // values at these points
      arrays::vector<dcomplex> a(n_points);    // corresponding Pade coefficients

      for (int i=0; i < n_points; ++i) z_in(i) = gw.mesh()[i];
      for (int i=0; i < n_points; ++i) u_in(i) = gw.on_mesh(i)(n1,n2);

      triqs::utility::pade_approximant PA(z_in,u_in);

      gr() = 0.0;
      for (auto om : gr.mesh()) {
        dcomplex e = om + dcomplex(0.0,1.0)*freq_offset;
        gr[om](n1,n2) = PA(e);
      }

    }
  }

 }

ANNcoord annSpread(				// compute point spread along dimension

	ANNpointArray		pa,				// point array

	ANNidxArray			pidx,			// point indices

	int					n,				// number of points

	int					d)				// dimension to check

{

	ANNcoord min = PA(0,d);				// compute max and min coords

	ANNcoord max = PA(0,d);

	for (int i = 1; i < n; i++) {

		ANNcoord c = PA(i,d);

		if (c < min) min = c;

		else if (c > max) max = c;

	}

	return (max - min);					// total spread is difference

}

void annPlaneSplit(				// split points by a plane
	ANNpointArray		pa,				// points to split
	ANNidxArray			pidx,			// point indices
	int					n,				// number of points
	int					d,				// dimension along which to split
	ANNcoord			cv,				// cutting value
	int					&br1,			// first break (values < cv)
	int					&br2)			// second break (values == cv)
{
	int l = 0;
	int r = n-1;
	for(;;) {							// partition pa[0..n-1] about cv
		while (l < n && PA(l,d) < cv) l++;
		while (r >= 0 && PA(r,d) >= cv) r--;
		if (l > r) break;
		PASWAP(l,r);
		l++; r--;
	}
	br1 = l;					// now: pa[0..br1-1] < cv <= pa[br1..n-1]
	r = n-1;
	for(;;) {							// partition pa[br1..n-1] about cv
		while (l < n && PA(l,d) <= cv) l++;
		while (r >= br1 && PA(r,d) > cv) r--;
		if (l > r) break;
		PASWAP(l,r);
		l++; r--;
	}
	br2 = l;					// now: pa[br1..br2-1] == cv < pa[br2..n-1]
}

void annMinMax(					// compute min and max coordinates along dim

	ANNpointArray		pa,				// point array

	ANNidxArray			pidx,			// point indices

	int					n,				// number of points

	int					d,				// dimension to check

	ANNcoord			&min,			// minimum value (returned)

	ANNcoord			&max)			// maximum value (returned)

{

	min = PA(0,d);						// compute max and min coords

	max = PA(0,d);

	for (int i = 1; i < n; i++) {

		ANNcoord c = PA(i,d);

		if (c < min) min = c;

		else if (c > max) max = c;

	}

}

static int
onfi_probe_cmd_exec(struct onfi_probe_params *params,
					unsigned char* data_ptr,
					int data_len)
{
	struct cmd_element *cmd_list_ptr = ce_array;
	struct cmd_element *cmd_list_ptr_start = ce_array;
	int num_desc = 0;
	uint32_t status = 0;
	int nand_ret = NANDC_RESULT_SUCCESS;
	uint8_t desc_flags = BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG
						| BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG;

	params->cfg.addr_loc_0 = 0;
	params->cfg.addr_loc_0 |= NAND_RD_LOC_LAST_BIT(1);
	params->cfg.addr_loc_0 |= NAND_RD_LOC_OFFSET(0);
	params->cfg.addr_loc_0 |= NAND_RD_LOC_SIZE(data_len);

	cmd_list_ptr = qpic_nand_add_onfi_probe_ce(params, cmd_list_ptr);

	/* Enqueue the desc for the above commands */
	bam_add_one_desc(&bam,
					 CMD_PIPE_INDEX,
					 (unsigned char*)cmd_list_ptr_start,
					 PA((addr_t)(uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start),
					 desc_flags);

	cmd_list_ptr_start = cmd_list_ptr;
	num_desc++;

	/* Add Data desc */
	bam_add_desc(&bam,
				 DATA_PRODUCER_PIPE_INDEX,
				 (unsigned char *)PA((addr_t)data_ptr),
				 data_len,
				 BAM_DESC_INT_FLAG);

	/* Wait for the commands to be executed */
	qpic_nand_wait_for_cmd_exec(num_desc);

	/* Read buffer status and check for errors. */
	status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr++);

	if (qpic_nand_check_status(status))
	{
		nand_ret = NANDC_RESULT_FAILURE;
		goto onfi_probe_exec_err;
	}

	/* Wait for data to be available */
	qpic_nand_wait_for_data(DATA_PRODUCER_PIPE_INDEX);

	/* Check for errors */
	nand_ret = qpic_nand_check_status(status);

onfi_probe_exec_err:
	return nand_ret;
}

int main() {
    Expr tcs[] = { cst( 0 ), cst( 1 ) };
    PA( tcs[ 0 ] );
    PA( tcs[ 1 ] );
    PA( cst( 0 ) );
    PA( cst( 1 ) );

    PA( slice( cst( SI64( 0x01234567 ) ), 8, 32 ) );

    Expr gfe = cst( SI64( 0x656667 ) );
    PRINT( gfe );
    PRINT( gfe.cst_data() );
    PRINT( gfe.cst_data( 8 ) );

    Expr pgfe = pointer_on( gfe );
    PRINT( pgfe );
    PRINT( pgfe.vat_data() );
    PRINT( pgfe.vat_data( 8 ) );

    PRINT( slice( gfe, 8, 32 ) );
    PRINT( slice( gfe, 8, 32 ).cst_data() );
    PRINT( slice( gfe, 8, 32 ).cst_data( 8 ) );

    PRINT( pointer_on( slice( gfe, 8, 32 ) ) );
    PRINT( pointer_on( slice( gfe, 8, 32 ) ).vat_data() );

    PRINT( add( arch->bt_ptr(), pointer_on( gfe ), cst( 1l ) ) );
    PRINT( val_at( add( arch->bt_ptr(), pointer_on( gfe ), cst( 1l ) ), 16 ) );

//    Expr sa = syscall( cst( 6 ), 2, tcs, 32 ).ret;
//    Expr sb = syscall( cst( 6 ), 2, tcs, 32 ).ret;
//    PA( sa );
//    PA( sb );

//    Expr pa = pointer_on( tcs[ 0 ], 64 );
//    Expr pb = pointer_on( tcs[ 0 ], 64 );
//    PA( pa );
//    PA( pb );

//    PA( add( bt_SI32, cst( 10 ), cst( 20 ) ) );

//    PA( rand( 64 ) );

//    PA( slice( cst( SI64( 0x176548 ) ), 8, 32 ) );

//    Expr struct_expr = concat( cst( 0x17 ), rand( 32 ) );
//    PA( struct_expr );
//    PA( slice( struct_expr,  0, 16 ) );
//    PA( slice( struct_expr,  0, 32 ) );
//    PA( slice( struct_expr, 32, 64 ) );
//    PA( slice( struct_expr, 32, 63 ) );

//    PA( val_at( pointer_on( cst( 0x32 ), 64 ), 32 ) );
//    PA( pointer_on( val_at( cst( 0x32 ), 32 ), 32 ) );
}

void mcfslt_profile_init(void)
{
	printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n",
	       PROFILEHZ);

	setup_irq(MCF_IRQ_PROFILER, &mcfslt_profile_irq);

	/* Set up TIMER 2 as high speed profile clock */
	__raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
	__raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
								PA(MCFSLT_SCR));

}

void
ia64_env_setup(struct ia64_boot_param *boot_param,
	struct kexec_boot_params *params)
{
	unsigned long len;
        efi_system_table_t *systab;
        efi_runtime_services_t *runtime;
	unsigned long *set_virtual_address_map;
	char *command_line = (char *)params->command_line;
	uint64_t command_line_len = params->command_line_len;
	struct ia64_boot_param *new_boot_param =
	(struct ia64_boot_param *) params->boot_param_base;
	memcpy(new_boot_param, boot_param, 4096);

	/*
	 * patch efi_runtime->set_virtual_address_map to a dummy function
	 *
	 * The EFI specification mandates that set_virtual_address_map only
	 * takes effect the first time that it is called, and that
	 * subsequent calls will return error.  By replacing it with a
	 * dummy function the new OS can think it is calling it again
	 * without either the OS or any buggy EFI implementations getting
	 * upset.
	 *
	 * Note: as the EFI specification says that set_virtual_address_map
	 * will only take affect the first time it is called, the mapping
	 * can't be updated, and thus mapping of the old and new OS really
	 * needs to be the same.
	 */
	len = __dummy_efi_function_end - __dummy_efi_function;
	memcpy(command_line + command_line_len,
		__dummy_efi_function, len);
	systab = (efi_system_table_t *)new_boot_param->efi_systab;
	runtime = (efi_runtime_services_t *)PA(systab->runtime);
	set_virtual_address_map =
		(unsigned long *)PA(runtime->set_virtual_address_map);
	*(set_virtual_address_map) =
		(unsigned long)(command_line + command_line_len);
	flush_icache_range(command_line + command_line_len, len);

	patch_efi_memmap(params, new_boot_param);

	new_boot_param->efi_memmap = params->efi_memmap_base;
	new_boot_param->command_line = params->command_line;
	new_boot_param->console_info.orig_x = 0;
	new_boot_param->console_info.orig_y = 0;
	new_boot_param->initrd_start = params->ramdisk_base;
	new_boot_param->initrd_size =  params->ramdisk_size;
	new_boot_param->vmcode_start = params->vmcode_base;
	new_boot_param->vmcode_size =  params->vmcode_size;
}

void coldfire_profile_init(void)
{
	printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n",
	       PROFILEHZ);

	/* Set up TIMER 2 as high speed profile clock */
	__raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));

	__raw_writetrr(((MCF_BUSCLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
	__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
		MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));

	setup_irq(MCF_IRQ_PROFILER, &coldfire_profile_irq);
}

static uint32_t
qpic_nand_fetch_id(struct flash_info *flash)
{
	struct cmd_element *cmd_list_ptr = ce_array;
	struct cmd_element *cmd_list_ptr_start = ce_array;
	int num_desc = 0;
	uint32_t status;
	uint32_t id;
	uint32_t flash_cmd = NAND_CMD_FETCH_ID;
	uint32_t exec_cmd = 1;
	int nand_ret = NANDC_RESULT_SUCCESS;

	/* Issue the Fetch id command to the NANDc */
	bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, (uint32_t)flash_cmd, CE_WRITE_TYPE);
	cmd_list_ptr++;

	/* Execute the cmd */
	bam_add_cmd_element(cmd_list_ptr, NAND_EXEC_CMD, (uint32_t)exec_cmd, CE_WRITE_TYPE);
	cmd_list_ptr++;

	/* Prepare the cmd desc for the above commands */
	bam_add_one_desc(&bam,
					 CMD_PIPE_INDEX,
					 (unsigned char*)cmd_list_ptr_start,
					 PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start),
					 BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG |
					 BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG);

	/* Keep track of the number of desc added. */
	num_desc++;
	qpic_nand_wait_for_cmd_exec(num_desc);

	cmd_list_ptr_start = ce_array;
	cmd_list_ptr = ce_array;

	/* Read the status register */
	status = qpic_nand_read_reg(NAND_FLASH_STATUS, 0, cmd_list_ptr);

	/* Check for errors */
	nand_ret = qpic_nand_check_status(status);
	if (nand_ret)
	{
		dprintf( CRITICAL, "Read ID cmd status failed\n");
		goto qpic_nand_fetch_id_err;
	}

	/* Read the id */
	id = qpic_nand_read_reg(NAND_READ_ID, BAM_DESC_UNLOCK_FLAG, cmd_list_ptr);

	flash->id = id;
	flash->vendor = id & 0xff;
	flash->device = (id >> 8) & 0xff;
	flash->dev_cfg = (id >> 24) & 0xFF;
	flash->widebus = 0;
	flash->widebus &= (id >> 24) & 0xFF;
	flash->widebus = flash->widebus? 1: 0;

qpic_nand_fetch_id_err:
	return nand_ret;
}

int annSplitBalance(			// determine balance factor of a split

	ANNpointArray		pa,				// points to split

	ANNidxArray			pidx,			// point indices

	int					n,				// number of points

	int					d,				// dimension along which to split

	ANNcoord			cv)				// cutting value

{

	int n_lo = 0;

	for(int i = 0; i < n; i++) {		// count number less than cv

		if (PA(i,d) < cv) n_lo++;

	}

	return n_lo - n/2;

}

static int usb_write(void *buf, unsigned len)
{
	int r;

	if (fastboot_state == STATE_ERROR)
		goto oops;

	req->buf = PA((addr_t)buf);
	req->length = len;
	req->complete = req_complete;
	r = udc_request_queue(in, req);
	if (r < 0) {
		dprintf(INFO, "usb_write() queue failed\n");
		goto oops;
	}
	event_wait(&txn_done);
	if (txn_status < 0) {
		dprintf(INFO, "usb_write() transaction failed\n");
		goto oops;
	}
	return req->length;

oops:
	fastboot_state = STATE_ERROR;
	return -1;
}

static uint32_t crypto_write_reg(struct bam_instance *bam_core,
								 uint32_t reg_addr,
								 uint32_t val,
								 uint8_t flags)
{
	uint32_t ret = 0;
	struct cmd_element cmd_list_ptr;


	ret = (uint32_t)bam_add_cmd_element(&cmd_list_ptr, reg_addr, val, CE_WRITE_TYPE);

	/* Enqueue the desc for the above command */
	ret = bam_add_one_desc(bam_core,
						   CRYPTO_WRITE_PIPE_INDEX,
						   (unsigned char*)PA((addr_t)&cmd_list_ptr),
						   BAM_CE_SIZE,
						   BAM_DESC_CMD_FLAG | BAM_DESC_INT_FLAG | flags);

	if (ret)
	{
		dprintf(CRITICAL,
				"CRYPTO_WRITE_REG: Reg write failed. reg addr = %x\n",
				reg_addr);
		goto crypto_read_reg_err;
	}

	crypto_wait_for_cmd_exec(bam_core, 1, CRYPTO_WRITE_PIPE_INDEX);

crypto_read_reg_err:
	return val;
}

irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
{
	/* Reset Slice Timer 1 */
	__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
	if (current->pid)
		profile_tick(CPU_PROFILING);
	return IRQ_HANDLED;
}