本文整理汇总了C++中OSMapPhysToLin函数的典型用法代码示例。如果您正苦于以下问题：C++ OSMapPhysToLin函数的具体用法？C++ OSMapPhysToLin怎么用？C++ OSMapPhysToLin使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了OSMapPhysToLin函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: Init_IRQ_CTRL
static IMG_VOID Init_IRQ_CTRL(PLAT_DATA *psPlatData)
{
IMG_CPU_PHYADDR sICRCpuPBase;
IMG_VOID *pvICRCpuVBase;
IMG_UINT32 ui32Value;
/* Map into CPU address space */
sICRCpuPBase.uiAddr = IMG_CAST_TO_CPUPHYADDR_UINT(psPlatData->uiICRCpuPAddr);
pvICRCpuVBase = OSMapPhysToLin(sICRCpuPBase,
psPlatData->uiICRSize,
0);
/* Configure IRQ_CTRL: For Rogue, enable IRQ, set sense to active low */
ui32Value = OSReadHWReg32(pvICRCpuVBase, EMULATOR_RGX_ICR_REG_IRQ_CTRL);
ui32Value &= ~EMULATOR_RGX_ICR_REG_IRQ_CTRL_IRQ_HINLO;
ui32Value |= EMULATOR_RGX_ICR_REG_IRQ_CTRL_IRQ_EN;
OSWriteHWReg32(pvICRCpuVBase,EMULATOR_RGX_ICR_REG_IRQ_CTRL, ui32Value);
/* Flush register write */
(void) OSReadHWReg32(pvICRCpuVBase, EMULATOR_RGX_ICR_REG_IRQ_CTRL);
OSWaitus(10);
PVR_TRACE(("Emulator FPGA image version (ICR_REG_CORE_REVISION): 0x%08x",
OSReadHWReg32(pvICRCpuVBase, EMULATOR_RGX_ICR_REG_CORE_REVISION)));
/* Unmap from CPU address space */
OSUnMapPhysToLin(pvICRCpuVBase, psPlatData->uiICRSize, 0);
}示例2: OSMapPhysToLin
/*!
******************************************************************************
@Function SysCreateVersionString
@Description Read the version string
@Return IMG_CHAR * : Version string
******************************************************************************/
static IMG_CHAR *SysCreateVersionString(void)
{
static IMG_CHAR aszVersionString[100];
SYS_DATA *psSysData;
IMG_UINT32 ui32SGXRevision;
IMG_INT32 i32Count;
#if !defined(NO_HARDWARE)
IMG_VOID *pvRegsLinAddr;
pvRegsLinAddr = OSMapPhysToLin(gsSGXDeviceMap.sRegsCpuPBase,
gsSGXDeviceMap.ui32RegsSize,
PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
IMG_NULL);
if(!pvRegsLinAddr)
{
return IMG_NULL;
}
#if SGX_CORE_REV == 105
ui32SGXRevision = 0x10005;
#else
ui32SGXRevision = OSReadHWReg((IMG_PVOID)((IMG_PBYTE)pvRegsLinAddr),
EUR_CR_CORE_REVISION);
#endif
#else
ui32SGXRevision = 0;
#endif
SysAcquireData(&psSysData);
i32Count = OSSNPrintf(aszVersionString, 100,
"SGX revision = %u.%u.%u",
(IMG_UINT)((ui32SGXRevision & EUR_CR_CORE_REVISION_MAJOR_MASK)
>> EUR_CR_CORE_REVISION_MAJOR_SHIFT),
(IMG_UINT)((ui32SGXRevision & EUR_CR_CORE_REVISION_MINOR_MASK)
>> EUR_CR_CORE_REVISION_MINOR_SHIFT),
(IMG_UINT)((ui32SGXRevision & EUR_CR_CORE_REVISION_MAINTENANCE_MASK)
>> EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT)
);
#if !defined(NO_HARDWARE)
OSUnMapPhysToLin(pvRegsLinAddr,
SYS_OMAP5430_SGX_REGS_SIZE,
PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
IMG_NULL);
#endif
if(i32Count == -1)
{
return IMG_NULL;
}
return aszVersionString;
}示例3: DisableSystemClocks
IMG_VOID DisableSystemClocks(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
IMG_BOOL bPowerLock;
#if defined(DEBUG) || defined(TIMING)
IMG_CPU_PHYADDR TimerRegPhysBase;
IMG_HANDLE hTimerDisable;
IMG_UINT32 *pui32TimerDisable;
#endif
PVR_TRACE(("DisableSystemClocks: Disabling System Clocks"));
DisableSGXClocks(psSysData);
bPowerLock = PowerLockWrappedOnCPU(psSysSpecData);
if (bPowerLock)
{
PowerLockUnwrap(psSysSpecData);
}
#if defined(DEBUG) || defined(TIMING)
TimerRegPhysBase.uiAddr = SYS_OMAP3430_GP11TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerDisable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerDisable);
if (pui32TimerDisable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSystemClocks: OSMapPhysToLin failed"));
}
else
{
*pui32TimerDisable = 0;
OSUnMapPhysToLin(pui32TimerDisable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerDisable);
}
clk_disable(psSysSpecData->psGPT11_ICK);
clk_disable(psSysSpecData->psGPT11_FCK);
#endif
if (bPowerLock)
{
PowerLockWrap(psSysSpecData);
}
}示例4: ReleaseGPTimer
/*!
******************************************************************************
@Function ReleaseGPTimer
@Description Release a GP timer
@Return PVRSRV_ERROR
******************************************************************************/
static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
IMG_HANDLE hTimerDisable;
IMG_UINT32 *pui32TimerDisable;
IMG_CPU_PHYADDR TimerRegPhysBase;
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
if (psSysSpecData->sTimerRegPhysBase.uiAddr == 0)
{
return;
}
#endif
/* Disable the timer */
pui32TimerDisable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerDisable);
if (pui32TimerDisable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSystemClocks: OSMapPhysToLin failed"));
}
else
{
*pui32TimerDisable = 0;
OSUnMapPhysToLin(pui32TimerDisable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerDisable);
}
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
psSysSpecData->sTimerRegPhysBase.uiAddr = 0;
#endif
#if defined(PVR_OMAP4_TIMING_PRCM)
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
clk_disable(psSysSpecData->psGPT11_ICK);
#endif
clk_disable(psSysSpecData->psGPT11_FCK);
#endif /* defined(PVR_OMAP4_TIMING_PRCM) */
}示例5: SysDebugInfo
PVRSRV_ERROR SysDebugInfo(PVRSRV_SYSTEM_CONFIG *psSysConfig)
{
PVRSRV_DEVICE_CONFIG *psDevice;
IMG_CPU_PHYADDR sWrapperRegsCpuPBase;
IMG_VOID *pvWrapperRegs;
psDevice = &sSysConfig.pasDevices[0];
sWrapperRegsCpuPBase.uiAddr = psDevice->sRegsCpuPBase.uiAddr + EMULATOR_RGX_REG_WRAPPER_OFFSET;
/* map emu registers */
pvWrapperRegs = OSMapPhysToLin(sWrapperRegsCpuPBase,
EMULATOR_RGX_REG_WRAPPER_SIZE,
0);
if (pvWrapperRegs == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR,"SysDebugDump: Failed to create wrapper register mapping\n"));
return PVRSRV_ERROR_BAD_MAPPING;
}
PVR_LOG(("------[ System Debug ]------"));
#define SYS_EMU_DBG_R32(R) PVR_LOG(("%-25s 0x%08X", #R ":", OSReadHWReg32(pvWrapperRegs, R)))
#define SYS_EMU_DBG_R64(R) PVR_LOG(("%-25s 0x%010llX", #R ":", OSReadHWReg64(pvWrapperRegs, R)))
SYS_EMU_DBG_R32(EMU_CR_PCI_MASTER);
SYS_EMU_DBG_R64(EMU_CR_WRAPPER_ERROR);
SYS_EMU_DBG_R32(EMU_CR_BANK_OUTSTANDING0);
SYS_EMU_DBG_R32(EMU_CR_BANK_OUTSTANDING1);
SYS_EMU_DBG_R32(EMU_CR_BANK_OUTSTANDING2);
SYS_EMU_DBG_R32(EMU_CR_BANK_OUTSTANDING3);
SYS_EMU_DBG_R32(EMU_CR_MEMORY_LATENCY);
/* remove mapping */
OSUnMapPhysToLin(pvWrapperRegs, EMULATOR_RGX_REG_WRAPPER_SIZE, 0);
return PVRSRV_OK;
}示例6: ReleaseGPTimer
static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
IMG_HANDLE hTimerDisable;
IMG_UINT32 *pui32TimerDisable;
IMG_CPU_PHYADDR TimerRegPhysBase;
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
if (psSysSpecData->sTimerRegPhysBase.uiAddr == 0)
{
return;
}
#endif
TimerRegPhysBase.uiAddr = SYS_TI335x_GP7TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerDisable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerDisable);
if (pui32TimerDisable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSystemClocks: OSMapPhysToLin failed"));
}
else
{
*pui32TimerDisable = 0;
OSUnMapPhysToLin(pui32TimerDisable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerDisable);
}
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
psSysSpecData->sTimerRegPhysBase.uiAddr = 0;
#endif
#if defined(PVR_OMAP3_TIMING_PRCM)
clk_disable(psSysSpecData->psGPT11_ICK);
clk_disable(psSysSpecData->psGPT11_FCK);
#endif
}示例7: SysMapInRegisters
static PVRSRV_ERROR SysMapInRegisters(IMG_VOID)
{
PVRSRV_DEVICE_NODE *psDeviceNodeList;
/*
Map the Atlas and PDP registers.
*/
gpsSysData->pvSOCRegsBase = OSMapPhysToLin(gsSOCRegsCpuPBase,
SYS_ATLAS_REG_REGION_SIZE,
PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
IMG_NULL);
if (gpsSysData->pvSOCRegsBase == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR,"SysPrePowerState: Failed to map SOC Register base"));
return PVRSRV_ERROR_REGISTER_BASE_NOT_SET;
}
psDeviceNodeList = gpsSysData->psDeviceNodeList;
while (psDeviceNodeList)
{
PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNodeList->pvDevice;
if (psDeviceNodeList->sDevId.eDeviceType == PVRSRV_DEVICE_TYPE_SGX)
{
#if defined(NO_HARDWARE) && defined(__linux__)
/*
* SysLocateDevices will have reallocated the dummy
* registers.
*/
PVR_ASSERT(gsSGXRegsCPUVAddr);
psDevInfo->pvRegsBaseKM = gsSGXRegsCPUVAddr;
#else
if (SYS_SPECIFIC_DATA_TEST(&gsSysSpecificData, SYS_SPECIFIC_DATA_PM_UNMAP_SGX_REGS))
{
/* Remap Regs */
psDevInfo->pvRegsBaseKM = OSMapPhysToLin(gsSGXDeviceMap.sRegsCpuPBase,
gsSGXDeviceMap.ui32RegsSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
if (!psDevInfo->pvRegsBaseKM)
{
PVR_DPF((PVR_DBG_ERROR,"SysMapInRegisters : Failed to map in regs\n"));
return PVRSRV_ERROR_BAD_MAPPING;
}
SYS_SPECIFIC_DATA_CLEAR(&gsSysSpecificData, SYS_SPECIFIC_DATA_PM_UNMAP_SGX_REGS);
}
#endif /* #if defined(NO_HARDWARE) && defined(__linux__) */
psDevInfo->ui32RegSize = gsSGXDeviceMap.ui32RegsSize;
psDevInfo->sRegsPhysBase = gsSGXDeviceMap.sRegsSysPBase;
#if defined(SGX_FEATURE_HOST_PORT)
if (gsSGXDeviceMap.ui32Flags & SGX_HOSTPORT_PRESENT)
{
if (SYS_SPECIFIC_DATA_TEST(&gsSysSpecificData, SYS_SPECIFIC_DATA_PM_UNMAP_SGX_HP))
{
/* Map Host Port */
psDevInfo->pvHostPortBaseKM = OSMapPhysToLin(gsSGXDeviceMap.sHPCpuPBase,
gsSGXDeviceMap.ui32HPSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
if (!psDevInfo->pvHostPortBaseKM)
{
PVR_DPF((PVR_DBG_ERROR,"SysMapInRegisters : Failed to map in host port\n"));
return PVRSRV_ERROR_BAD_MAPPING;
}
SYS_SPECIFIC_DATA_CLEAR(&gsSysSpecificData, SYS_SPECIFIC_DATA_PM_UNMAP_SGX_HP);
}
psDevInfo->ui32HPSize = gsSGXDeviceMap.ui32HPSize;
psDevInfo->sHPSysPAddr = gsSGXDeviceMap.sHPSysPBase;
}
#endif /* #if defined(SGX_FEATURE_HOST_PORT) */
}
psDeviceNodeList = psDeviceNodeList->psNext;
}
return PVRSRV_OK;
}示例8: _DeferredAllocPagetables
//.........这里部分代码省略.........
}
if (ppsPTInfoList[i]->PTPageCpuVAddr) {
sCpuPAddr =
OSMapLinToCPUPhys(ppsPTInfoList[i]->
PTPageCpuVAddr);
} else {
sCpuPAddr =
OSMemHandleToCpuPAddr(
ppsPTInfoList[i]->
hPTPageOSMemHandle,
0);
}
sDevPAddr =
SysCpuPAddrToDevPAddr
(PVRSRV_DEVICE_TYPE_SGX, sCpuPAddr);
} else {
struct IMG_SYS_PHYADDR sSysPAddr;
if (RA_Alloc(pMMUHeap->psDevArena->
psDeviceMemoryHeapInfo->psLocalDevMemArena,
SGX_MMU_PAGE_SIZE, NULL, 0,
SGX_MMU_PAGE_SIZE,
&(sSysPAddr.uiAddr)) != IMG_TRUE) {
PVR_DPF(PVR_DBG_ERROR,
"_DeferredAllocPagetables: "
"ERROR call to RA_Alloc failed");
return IMG_FALSE;
}
sCpuPAddr = SysSysPAddrToCpuPAddr(sSysPAddr);
ppsPTInfoList[i]->PTPageCpuVAddr =
(void __force *)
OSMapPhysToLin(sCpuPAddr, SGX_MMU_PAGE_SIZE,
PVRSRV_HAP_WRITECOMBINE |
PVRSRV_HAP_KERNEL_ONLY,
&ppsPTInfoList[i]->
hPTPageOSMemHandle);
if (!ppsPTInfoList[i]->PTPageCpuVAddr) {
PVR_DPF(PVR_DBG_ERROR,
"_DeferredAllocPagetables: "
"ERROR failed to map page tables");
return IMG_FALSE;
}
sDevPAddr = SysCpuPAddrToDevPAddr
(PVRSRV_DEVICE_TYPE_SGX, sCpuPAddr);
}
OSMemSet(ppsPTInfoList[i]->PTPageCpuVAddr, 0,
SGX_MMU_PAGE_SIZE);
PDUMPMALLOCPAGETABLE(ppsPTInfoList[i]->PTPageCpuVAddr,
PDUMP_PT_UNIQUETAG);
PDUMPPAGETABLE(ppsPTInfoList[i]->PTPageCpuVAddr,
SGX_MMU_PAGE_SIZE, IMG_TRUE,
PDUMP_PT_UNIQUETAG, PDUMP_PT_UNIQUETAG);
switch (pMMUHeap->psDevArena->DevMemHeapType) {
case DEVICE_MEMORY_HEAP_SHARED:
case DEVICE_MEMORY_HEAP_SHARED_EXPORTED:
{
struct MMU_CONTEXT *psMMUContext =示例9: SysInitialise
//.........这里部分代码省略.........
#else
psTimingInfo->bEnableActivePM = IMG_FALSE;
#endif
psTimingInfo->ui32ActivePowManLatencyms = SYS_SGX_ACTIVE_POWER_LATENCY_MS;
psTimingInfo->ui32uKernelFreq = SYS_SGX_PDS_TIMER_FREQ;
#endif
gpsSysSpecificData->ui32SrcClockDiv = 3;
eError = SysLocateDevices(gpsSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysInitialise: Failed to locate devices"));
(IMG_VOID)SysDeinitialise(gpsSysData);
gpsSysData = IMG_NULL;
return eError;
}
SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LOCATEDEV);
#if defined(SGX_OCP_REGS_ENABLED)
{
IMG_SYS_PHYADDR sOCPRegsSysPBase;
IMG_CPU_PHYADDR sOCPRegsCpuPBase;
sOCPRegsSysPBase.uiAddr = SYS_OMAP3430_OCP_REGS_SYS_PHYS_BASE;
sOCPRegsCpuPBase = SysSysPAddrToCpuPAddr(sOCPRegsSysPBase);
gpvOCPRegsLinAddr = OSMapPhysToLin(sOCPRegsCpuPBase,
SYS_OMAP3430_OCP_REGS_SIZE,
PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
IMG_NULL);
if (gpvOCPRegsLinAddr == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR,"SysInitialise: Failed to map OCP registers"));
return PVRSRV_ERROR_BAD_MAPPING;
}
SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_OCPREGS);
}
#endif
eError = PVRSRVRegisterDevice(gpsSysData, SGXRegisterDevice,
DEVICE_SGX_INTERRUPT, &gui32SGXDeviceID);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysInitialise: Failed to register device!"));
(IMG_VOID)SysDeinitialise(gpsSysData);
gpsSysData = IMG_NULL;
return eError;
}
SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_REGDEV);
psDeviceNode = gpsSysData->psDeviceNodeList;
while(psDeviceNode)
{示例10: PVRSRVSaveRestoreLiveSegments
/*!
******************************************************************************
@Function PVRSRVSaveRestoreLiveSegments
@Input pArena - the arena the segment was originally allocated from.
pbyBuffer - the system memory buffer set to null to get the size needed.
puiBufSize - size of system memory buffer.
bSave - IMG_TRUE if a save is required
@Description
Function to save or restore Resources Live segments
******************************************************************************/
PVRSRV_ERROR IMG_CALLCONV PVRSRVSaveRestoreLiveSegments(IMG_HANDLE hArena, IMG_PBYTE pbyBuffer,
IMG_SIZE_T *puiBufSize, IMG_BOOL bSave)
{
IMG_SIZE_T uiBytesSaved = 0;
IMG_PVOID pvLocalMemCPUVAddr;
RA_SEGMENT_DETAILS sSegDetails;
if (hArena == IMG_NULL)
{
return (PVRSRV_ERROR_INVALID_PARAMS);
}
sSegDetails.uiSize = 0;
sSegDetails.sCpuPhyAddr.uiAddr = 0;
sSegDetails.hSegment = 0;
/* walk the arena segments and write live one to the buffer */
while (RA_GetNextLiveSegment(hArena, &sSegDetails))
{
if (pbyBuffer == IMG_NULL)
{
/* calc buffer required */
uiBytesSaved += sizeof(sSegDetails.uiSize) + sSegDetails.uiSize;
}
else
{
if ((uiBytesSaved + sizeof(sSegDetails.uiSize) + sSegDetails.uiSize) > *puiBufSize)
{
return (PVRSRV_ERROR_OUT_OF_MEMORY);
}
PVR_DPF((
PVR_DBG_MESSAGE,
"PVRSRVSaveRestoreLiveSegments: Base " CPUPADDR_FMT " size %" SIZE_T_FMT_LEN "x",
sSegDetails.sCpuPhyAddr.uiAddr,
sSegDetails.uiSize));
/* Map the device's local memory area onto the host. */
pvLocalMemCPUVAddr = OSMapPhysToLin(sSegDetails.sCpuPhyAddr,
sSegDetails.uiSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
if (pvLocalMemCPUVAddr == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVSaveRestoreLiveSegments: Failed to map local memory to host"));
return (PVRSRV_ERROR_OUT_OF_MEMORY);
}
if (bSave)
{
/* write segment size then segment data */
OSMemCopy(pbyBuffer, &sSegDetails.uiSize, sizeof(sSegDetails.uiSize));
pbyBuffer += sizeof(sSegDetails.uiSize);
OSMemCopy(pbyBuffer, pvLocalMemCPUVAddr, sSegDetails.uiSize);
pbyBuffer += sSegDetails.uiSize;
}
else
{
IMG_UINT32 uiSize;
/* reag segment size and validate */
OSMemCopy(&uiSize, pbyBuffer, sizeof(sSegDetails.uiSize));
if (uiSize != sSegDetails.uiSize)
{
PVR_DPF((PVR_DBG_ERROR, "PVRSRVSaveRestoreLiveSegments: Segment size error"));
}
else
{
pbyBuffer += sizeof(sSegDetails.uiSize);
OSMemCopy(pvLocalMemCPUVAddr, pbyBuffer, sSegDetails.uiSize);
pbyBuffer += sSegDetails.uiSize;
}
}
uiBytesSaved += sizeof(sSegDetails.uiSize) + sSegDetails.uiSize;
OSUnMapPhysToLin(pvLocalMemCPUVAddr,
sSegDetails.uiSize,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
}
}
//.........这里部分代码省略.........
示例11: PVRSRVSaveRestoreLiveSegments
enum PVRSRV_ERROR PVRSRVSaveRestoreLiveSegments(void *hArena, u8 *pbyBuffer,
u32 *puiBufSize, IMG_BOOL bSave)
{
u32 uiBytesSaved = 0;
void *pvLocalMemCPUVAddr;
struct RA_SEGMENT_DETAILS sSegDetails;
if (hArena == NULL)
return PVRSRV_ERROR_INVALID_PARAMS;
sSegDetails.uiSize = 0;
sSegDetails.sCpuPhyAddr.uiAddr = 0;
sSegDetails.hSegment = NULL;
while (RA_GetNextLiveSegment(hArena, &sSegDetails))
if (pbyBuffer == NULL) {
uiBytesSaved +=
sizeof(sSegDetails.uiSize) + sSegDetails.uiSize;
} else {
if ((uiBytesSaved + sizeof(sSegDetails.uiSize) +
sSegDetails.uiSize) > *puiBufSize)
return PVRSRV_ERROR_OUT_OF_MEMORY;
PVR_DPF(PVR_DBG_MESSAGE,
"PVRSRVSaveRestoreLiveSegments: "
"Base %08x size %08x",
sSegDetails.sCpuPhyAddr.uiAddr,
sSegDetails.uiSize);
pvLocalMemCPUVAddr = (void __force *)
OSMapPhysToLin(sSegDetails.sCpuPhyAddr,
sSegDetails.uiSize,
PVRSRV_HAP_KERNEL_ONLY |
PVRSRV_HAP_UNCACHED, NULL);
if (pvLocalMemCPUVAddr == NULL) {
PVR_DPF(PVR_DBG_ERROR,
"PVRSRVSaveRestoreLiveSegments: "
"Failed to map local memory to host");
return PVRSRV_ERROR_OUT_OF_MEMORY;
}
if (bSave) {
OSMemCopy(pbyBuffer, &sSegDetails.uiSize,
sizeof(sSegDetails.uiSize));
pbyBuffer += sizeof(sSegDetails.uiSize);
OSMemCopy(pbyBuffer, pvLocalMemCPUVAddr,
sSegDetails.uiSize);
pbyBuffer += sSegDetails.uiSize;
} else {
u32 uiSize;
OSMemCopy(&uiSize, pbyBuffer,
sizeof(sSegDetails.uiSize));
if (uiSize != sSegDetails.uiSize) {
PVR_DPF(PVR_DBG_ERROR,
"PVRSRVSaveRestoreLiveSegments:"
" Segment size error");
} else {
pbyBuffer += sizeof(sSegDetails.uiSize);
OSMemCopy(pvLocalMemCPUVAddr, pbyBuffer,
sSegDetails.uiSize);
pbyBuffer += sSegDetails.uiSize;
}
}
uiBytesSaved +=
sizeof(sSegDetails.uiSize) + sSegDetails.uiSize;
OSUnMapPhysToLin((void __force __iomem *)
pvLocalMemCPUVAddr,
sSegDetails.uiSize,
PVRSRV_HAP_KERNEL_ONLY |
PVRSRV_HAP_UNCACHED, NULL);
}
if (pbyBuffer == NULL)
*puiBufSize = uiBytesSaved;
return PVRSRV_OK;
}示例12: DisableSystemClocks
IMG_VOID DisableSystemClocks(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
IMG_BOOL bPowerLock;
#if defined(DEBUG) || defined(TIMING)
IMG_CPU_PHYADDR TimerRegPhysBase;
IMG_HANDLE hTimerDisable;
IMG_UINT32 *pui32TimerDisable;
#endif
PVR_TRACE(("DisableSystemClocks: Disabling System Clocks"));
DisableSGXClocks(psSysData);
bPowerLock = PowerLockWrappedOnCPU(psSysSpecData);
if (bPowerLock)
{
PowerLockUnwrap(psSysSpecData);
}
#if defined(PDUMP) && !defined(NO_HARDWARE) && defined(CONSTRAINT_NOTIFICATIONS)
{
int res;
PVR_TRACE(("DisableSystemClocks: Removing SGX OPP constraint"));
res = constraint_remove(psSysSpecData->pVdd2Handle);
if (res != 0)
{
PVR_DPF((PVR_DBG_WARNING, "DisableSystemClocks: constraint_remove failed (%d)", res));
}
}
#endif
#if defined(CONSTRAINT_NOTIFICATIONS)
UnRegisterConstraintNotifications();
#endif
#if defined(DEBUG) || defined(TIMING)
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerDisable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerDisable);
if (pui32TimerDisable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSystemClocks: OSMapPhysToLin failed"));
}
else
{
*pui32TimerDisable = 0;
OSUnMapPhysToLin(pui32TimerDisable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerDisable);
}
clk_disable(psSysSpecData->psGPT11_ICK);
clk_disable(psSysSpecData->psGPT11_FCK);
#endif
#if defined(CONSTRAINT_NOTIFICATIONS)
constraint_put(psSysSpecData->pVdd2Handle);
#endif
if (bPowerLock)
{
PowerLockWrap(psSysSpecData);
}
}示例13: EnableSystemClocks
//.........这里部分代码省略.........
psSysSpecData->psGPT11_FCK = psCLK;
if(cpu_is_ti816x()) {
psCLK = clk_get(NULL, "gpt6_ick");
} else {
psCLK = clk_get(NULL, "gpt7_ick");
}
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock"));
goto ExitUnRegisterConstraintNotifications;
}
psSysSpecData->psGPT11_ICK = psCLK;
rate = clk_get_rate(psSysSpecData->psGPT11_FCK);
PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate)));
res = clk_enable(psSysSpecData->psGPT11_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res));
goto ExitUnRegisterConstraintNotifications;
}
res = clk_enable(psSysSpecData->psGPT11_ICK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res));
goto ExitDisableGPT11FCK;
}
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_TSICR_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
rate = *pui32TimerEnable;
if(!(rate & 4))
{
PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)"));
*pui32TimerEnable = rate | 4;
}
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)示例14: AcquireGPTimer
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
#if defined(PVR_OMAP3_TIMING_PRCM)
struct clk *psCLK;
IMG_INT res;
struct clk *sys_ck;
IMG_INT rate;
#endif
PVRSRV_ERROR eError;
IMG_CPU_PHYADDR sTimerRegPhysBase;
IMG_HANDLE hTimerEnable;
IMG_UINT32 *pui32TimerEnable;
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
PVR_ASSERT(psSysSpecData->sTimerRegPhysBase.uiAddr == 0);
#endif
#if defined(PVR_OMAP3_TIMING_PRCM)
psCLK = clk_get(NULL, "gpt7_fck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock"));
goto ExitError;
}
psSysSpecData->psGPT11_FCK = psCLK;
psCLK = clk_get(NULL, "gpt7_ick");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock"));
goto ExitError;
}
psSysSpecData->psGPT11_ICK = psCLK;
rate = clk_get_rate(psSysSpecData->psGPT11_FCK);
PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate)));
res = clk_enable(psSysSpecData->psGPT11_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res));
goto ExitError;
}
res = clk_enable(psSysSpecData->psGPT11_ICK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res));
goto ExitDisableGPT11FCK;
}
#endif
sTimerRegPhysBase.uiAddr = SYS_TI335x_GP7TIMER_TSICR_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
if(!(*pui32TimerEnable & 4))
{
PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)"));
*pui32TimerEnable |= 4;
}
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
sTimerRegPhysBase.uiAddr = SYS_TI335x_GP7TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
*pui32TimerEnable = 3;
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
//.........这里部分代码省略.........
示例15: SysInitialise
//.........这里部分代码省略.........
gpsSysData->sDeviceID[i].bInUse = IMG_FALSE;
}
gpsSysData->psDeviceNodeList = IMG_NULL;
gpsSysData->psQueueList = IMG_NULL;
eError = SysInitialiseCommon(gpsSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysInitialise: Failed in SysInitialiseCommon"));
SysDeinitialise(gpsSysData);
gpsSysData = IMG_NULL;
return eError;
}
/*
Locate the devices within the system, specifying
the physical addresses of each devices components
(regs, mem, ports etc.)
*/
eError = SysLocateDevices(gpsSysData);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysInitialise: Failed to locate devices"));
SysDeinitialise(gpsSysData);
gpsSysData = IMG_NULL;
return eError;
}
SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LOCATEDEV);
/*
Map the Atlas and PDP registers.
*/
gpsSysData->pvSOCRegsBase = OSMapPhysToLin(gsSOCRegsCpuPBase,
SYS_ATLAS_REG_REGION_SIZE,
PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
IMG_NULL);
/*
Do some initial register setup
*/
eError = SysInitRegisters();
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysInitRegisters: Failed to initialise registers"));
SysDeinitialise(gpsSysData);
gpsSysData = IMG_NULL;
return eError;
}
SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_INITREG);
#if defined(READ_TCF_HOST_MEM_SIGNATURE)
SysTestTCFHostMemSig(gsSGXDeviceMap.sRegsCpuPBase,
gsSGXDeviceMap.sLocalMemCpuPBase);
#endif
/*
Register devices with the system
This also sets up their memory maps/heaps
*/
eError = PVRSRVRegisterDevice(gpsSysData, SGXRegisterDevice,
SysGetSGXInterruptBit(), &gui32SGXDeviceID);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysInitialise: Failed to register device!"));
SysDeinitialise(gpsSysData);