本文整理汇总了C++中OSL_DELAY函数的典型用法代码示例。如果您正苦于以下问题:C++ OSL_DELAY函数的具体用法?C++ OSL_DELAY怎么用?C++ OSL_DELAY使用的例子?那么, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了OSL_DELAY函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: adm_adclk
/* Advance clock(s) */
static void
adm_adclk(adm_info_t *adm, int clocks)
{
int i;
for (i = 0; i < clocks; i ++) {
/* Clock high */
si_gpioout(adm->sih, adm->eesk, adm->eesk, GPIO_DRV_PRIORITY);
OSL_DELAY(EECK_EDGE_TIME);
/* Clock low */
si_gpioout(adm->sih, adm->eesk, 0, GPIO_DRV_PRIORITY);
OSL_DELAY(EECK_EDGE_TIME);
}
}
示例2: pcie2_mdiosetblock
static bool
pcie2_mdiosetblock(pcicore_info_t *pi, uint blk)
{
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
uint mdiodata, mdioctrl, i = 0;
uint pcie_serdes_spinwait = 200;
mdioctrl = MDIOCTL2_DIVISOR_VAL | (0x1F << MDIOCTL2_REGADDR_SHF);
W_REG(pi->osh, &pcieregs->u.pcie2.mdiocontrol, mdioctrl);
mdiodata = (blk << MDIODATA2_DEVADDR_SHF) | MDIODATA2_DONE;
W_REG(pi->osh, &pcieregs->u.pcie2.mdiowrdata, mdiodata);
PR28829_DELAY();
/* retry till the transaction is complete */
while (i < pcie_serdes_spinwait) {
if (!(R_REG(pi->osh, &(pcieregs->u.pcie2.mdiowrdata)) & MDIODATA2_DONE)) {
break;
}
OSL_DELAY(1000);
i++;
}
if (i >= pcie_serdes_spinwait) {
PCI_ERROR(("pcie_mdiosetblock: timed out\n"));
return FALSE;
}
return TRUE;
}
示例3: pcie_mdiosetblock
static bool
pcie_mdiosetblock(pcicore_info_t *pi, uint blk)
{
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
uint mdiodata, i = 0;
uint pcie_serdes_spinwait = 200;
mdiodata = MDIODATA_START | MDIODATA_WRITE | (MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) | \
(MDIODATA_BLK_ADDR << MDIODATA_REGADDR_SHF) | MDIODATA_TA | (blk << 4);
W_REG(pi->osh, &pcieregs->mdiodata, mdiodata);
PR28829_DELAY();
/* retry till the transaction is complete */
while (i < pcie_serdes_spinwait) {
if (R_REG(pi->osh, &(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
break;
}
OSL_DELAY(1000);
i++;
}
if (i >= pcie_serdes_spinwait) {
PCI_ERROR(("pcie_mdiosetblock: timed out\n"));
return FALSE;
}
return TRUE;
}
示例4: adm_disout
/* Disable outputs to the chip */
static void
adm_disout(adm_info_t *adm, uint32 pins)
{
/* Disable GPIO outputs */
si_gpioouten(adm->sih, pins, 0, GPIO_DRV_PRIORITY);
OSL_DELAY(EECK_EDGE_TIME);
}
示例5: dma_txreset
void
dma_txreset(dma_info_t *di)
{
uint32 status;
DMA_TRACE(("%s: dma_txreset\n", di->name));
/* address PR8249/PR7577 issue */
/* suspend tx DMA first */
W_REG(&di->regs->xmtcontrol, XC_SE);
SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED &&
status != XS_XS_IDLE &&
status != XS_XS_STOPPED,
10000);
/* PR2414 WAR: DMA engines are not disabled until transfer finishes */
W_REG(&di->regs->xmtcontrol, 0);
SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED,
10000);
if (status != XS_XS_DISABLED) {
DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
}
/* wait for the last transaction to complete */
OSL_DELAY(300);
}
示例6: reset_release_wait
static void
reset_release_wait(void)
{
int gpio;
uint32 gpiomask;
int i=0;
if ((gpio = nvram_resetgpio_init ((void *)sih)) < 0)
return;
/* Reset button is active low */
gpiomask = (uint32)1 << gpio;
while (1) {
if ((i%100000) < 30000) {
LEDON();
}
else {
LEDOFF();
}
i++;
if (i==0xffffff) {
i = 0;
}
if (si_gpioin(sih) & gpiomask) {
OSL_DELAY(RESET_DEBOUNCE_TIME);
if (si_gpioin(sih) & gpiomask)
break;
}
}
}
示例7: dhd_customer_gpio_wlan_ctrl
/* Customer function to control hw specific wlan gpios */
void
dhd_customer_gpio_wlan_ctrl(int onoff)
{
switch (onoff) {
case WLAN_RESET_OFF:
WL_TRACE(("%s: call customer specific GPIO to insert WLAN RESET\n",
__FUNCTION__));
#ifdef FIH_HW
bcm4330_wifi_suspend(); //FIH-ADD+
#endif
#ifdef CUSTOMER_HW
bcm_wlan_power_off(2);
#endif /* CUSTOMER_HW */
#ifdef CUSTOMER_HW2
wifi_set_power(0, 0);
#endif
//WL_ERROR(("=========== WLAN placed in RESET ========\n"));
break;
case WLAN_RESET_ON:
WL_TRACE(("%s: callc customer specific GPIO to remove WLAN RESET\n",
__FUNCTION__));
#ifdef FIH_HW
bcm4330_wifi_resume(); //FIH-ADD+
#endif
#ifdef CUSTOMER_HW
bcm_wlan_power_on(2);
#endif /* CUSTOMER_HW */
#ifdef CUSTOMER_HW2
wifi_set_power(1, 0);
#endif
//WL_ERROR(("=========== WLAN going back to live ========\n"));
break;
case WLAN_POWER_OFF:
WL_TRACE(("%s: call customer specific GPIO to turn off WL_REG_ON\n",
__FUNCTION__));
#ifdef FIH_HW
wifi_power(0); //FIH-ADD+
#endif
#ifdef CUSTOMER_HW
bcm_wlan_power_off(1);
#endif /* CUSTOMER_HW */
break;
case WLAN_POWER_ON:
WL_TRACE(("%s: call customer specific GPIO to turn on WL_REG_ON\n",
__FUNCTION__));
#ifdef FIH_HW
wifi_power(1); //FIH-ADD+
#endif
#ifdef CUSTOMER_HW
bcm_wlan_power_on(1);
/* Lets customer power to get stable */
OSL_DELAY(200);
#endif /* CUSTOMER_HW */
break;
}
}
示例8: bcm_mdelay
void bcm_mdelay(uint ms)
{
uint i;
for (i = 0; i < ms; i++) {
OSL_DELAY(1000);
}
}
示例9: adm_enout
/* Enable outputs with specified value to the chip */
static void
adm_enout(adm_info_t *adm, uint32 pins, uint val)
{
/* Prepare GPIO output value */
si_gpioout(adm->sih, pins, val, GPIO_DRV_PRIORITY);
/* Enable GPIO outputs */
si_gpioouten(adm->sih, pins, pins, GPIO_DRV_PRIORITY);
OSL_DELAY(EECK_EDGE_TIME);
}
示例10: pciegen1_mdioop
static int
pciegen1_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write, uint *val)
{
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
uint mdiodata;
uint i = 0;
uint pcie_serdes_spinwait = 10;
if (!PCIE_GEN1(pi->sih))
ASSERT(0);
/* enable mdio access to SERDES */
W_REG(pi->osh, (&pcieregs->u.pcie1.mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
if (pi->sih->buscorerev >= 10) {
/* new serdes is slower in rw, using two layers of reg address mapping */
if (!pcie_mdiosetblock(pi, physmedia))
return 1;
mdiodata = (MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
(regaddr << MDIODATA_REGADDR_SHF);
pcie_serdes_spinwait *= 20;
} else {
mdiodata = (physmedia << MDIODATA_DEVADDR_SHF_OLD) |
(regaddr << MDIODATA_REGADDR_SHF_OLD);
}
if (!write)
mdiodata |= (MDIODATA_START | MDIODATA_READ | MDIODATA_TA);
else
mdiodata |= (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA | *val);
W_REG(pi->osh, &pcieregs->u.pcie1.mdiodata, mdiodata);
PR28829_DELAY();
/* retry till the transaction is complete */
while (i < pcie_serdes_spinwait) {
if (R_REG(pi->osh, &(pcieregs->u.pcie1.mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
if (!write) {
PR28829_DELAY();
*val = (R_REG(pi->osh, &(pcieregs->u.pcie1.mdiodata)) &
MDIODATA_MASK);
}
/* Disable mdio access to SERDES */
W_REG(pi->osh, (&pcieregs->u.pcie1.mdiocontrol), 0);
return 0;
}
OSL_DELAY(1000);
i++;
}
PCI_ERROR(("pcie_mdioop: timed out op: %d\n", write));
/* Disable mdio access to SERDES */
W_REG(pi->osh, (&pcieregs->u.pcie1.mdiocontrol), 0);
return 1;
}
示例11: dhd_customer_gpio_wlan_ctrl
/* Customer function to control hw specific wlan gpios */
void
dhd_customer_gpio_wlan_ctrl(int onoff)
{
switch (onoff) {
case WLAN_RESET_OFF:
WL_TRACE(("%s: call customer specific GPIO to insert WLAN RESET\n",
__FUNCTION__));
#if defined(CONFIG_LGE_BCM432X_PATCH)
gpio_set_value(CONFIG_BCM4329_GPIO_WL_RESET, 0);
#endif
#ifdef CUSTOMER_HW
bcm_wlan_power_off(2);
#endif /* CUSTOMER_HW */
#ifdef CUSTOMER_HW2
wifi_set_power(0, 0);
#endif
WL_ERROR(("=========== WLAN placed in RESET ========\n"));
break;
case WLAN_RESET_ON:
WL_TRACE(("%s: callc customer specific GPIO to remove WLAN RESET\n",
__FUNCTION__));
#if defined(CONFIG_LGE_BCM432X_PATCH)
gpio_set_value(CONFIG_BCM4329_GPIO_WL_RESET, 1);
mdelay(150); //mingi
#endif
#ifdef CUSTOMER_HW
bcm_wlan_power_on(2);
#endif /* CUSTOMER_HW */
#ifdef CUSTOMER_HW2
wifi_set_power(1, 0);
#endif
WL_ERROR(("=========== WLAN going back to live ========\n"));
break;
case WLAN_POWER_OFF:
WL_TRACE(("%s: call customer specific GPIO to turn off WL_REG_ON\n",
__FUNCTION__));
#ifdef CUSTOMER_HW
bcm_wlan_power_off(1);
#endif /* CUSTOMER_HW */
break;
case WLAN_POWER_ON:
WL_TRACE(("%s: call customer specific GPIO to turn on WL_REG_ON\n",
__FUNCTION__));
#ifdef CUSTOMER_HW
bcm_wlan_power_on(1);
#endif /* CUSTOMER_HW */
/* Lets customer power to get stable */
OSL_DELAY(500);
break;
}
}
示例12: adm_write
/* Write a bit stream to the chip */
static void
adm_write(adm_info_t *adm, int cs, uint8 *buf, uint bits)
{
uint i, len = (bits + 7) / 8;
uint8 mask;
/* CS high/low */
if (cs)
si_gpioout(adm->sih, adm->eecs, adm->eecs, GPIO_DRV_PRIORITY);
else
si_gpioout(adm->sih, adm->eecs, 0, GPIO_DRV_PRIORITY);
OSL_DELAY(EECK_EDGE_TIME);
/* Byte assemble from MSB to LSB */
for (i = 0; i < len; i++) {
/* Bit bang from MSB to LSB */
for (mask = 0x80; mask && bits > 0; mask >>= 1, bits --) {
/* Clock low */
si_gpioout(adm->sih, adm->eesk, 0, GPIO_DRV_PRIORITY);
OSL_DELAY(EECK_EDGE_TIME);
/* Output on rising edge */
if (mask & buf[i])
si_gpioout(adm->sih, adm->eedi, adm->eedi, GPIO_DRV_PRIORITY);
else
si_gpioout(adm->sih, adm->eedi, 0, GPIO_DRV_PRIORITY);
OSL_DELAY(EEDI_SETUP_TIME);
/* Clock high */
si_gpioout(adm->sih, adm->eesk, adm->eesk, GPIO_DRV_PRIORITY);
OSL_DELAY(EECK_EDGE_TIME);
}
}
/* Clock low */
si_gpioout(adm->sih, adm->eesk, 0, GPIO_DRV_PRIORITY);
OSL_DELAY(EECK_EDGE_TIME);
/* CS low */
if (cs)
si_gpioout(adm->sih, adm->eecs, 0, GPIO_DRV_PRIORITY);
}
示例13: dhd_customer_gpio_wlan_ctrl
/* Customer function to control hw specific wlan gpios */
void
dhd_customer_gpio_wlan_ctrl(int onoff)
{
switch (onoff) {
case WLAN_RESET_OFF:
WL_TRACE(("%s: call customer specific GPIO to insert WLAN RESET\n",
__FUNCTION__));
#ifdef CUSTOMER_HW
bcm_wlan_power_off(2);
#endif /* CUSTOMER_HW */
#ifdef CUSTOMER_HW2
wifi_set_power(0, 0);
#endif
WL_ERROR(("=========== WLAN placed in RESET ========\n"));
break;
case WLAN_RESET_ON:
WL_TRACE(("%s: callc customer specific GPIO to remove WLAN RESET\n",
__FUNCTION__));
#ifdef CUSTOMER_HW
bcm_wlan_power_on(2);
#endif /* CUSTOMER_HW */
#ifdef CUSTOMER_HW2
wifi_set_power(1, 0);
#endif
WL_ERROR(("=========== WLAN going back to live ========\n"));
break;
case WLAN_POWER_OFF:
WL_TRACE(("%s: call customer specific GPIO to turn off WL_REG_ON\n",
__FUNCTION__));
#ifdef CUSTOMER_HW
bcm_wlan_power_off(1);
#endif /* CUSTOMER_HW */
remove_proc_entry("q_wlan", NULL);
q_wlan_flag = 0;
break;
case WLAN_POWER_ON:
WL_TRACE(("%s: call customer specific GPIO to turn on WL_REG_ON\n",
__FUNCTION__));
entry = create_proc_read_entry("q_wlan", 0, NULL, q_proc_call, NULL);
if (!entry)
printk("cl: unable to create proc file.\n");
#ifdef CUSTOMER_HW
bcm_wlan_power_on(1);
#endif
/* Lets customer power to get stable */
OSL_DELAY(50);
break;
}
}
示例14: pcie_watchdog_reset
void pcie_watchdog_reset(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs)
{
uint32 val, i, lsc;
uint16 cfg_offset[] = {PCIECFGREG_STATUS_CMD, PCIECFGREG_PM_CSR,
PCIECFGREG_MSI_CAP, PCIECFGREG_MSI_ADDR_L,
PCIECFGREG_MSI_ADDR_H, PCIECFGREG_MSI_DATA,
PCIECFGREG_LINK_STATUS_CTRL2, PCIECFGREG_RBAR_CTRL,
PCIECFGREG_PML1_SUB_CTRL1, PCIECFGREG_REG_BAR2_CONFIG,
PCIECFGREG_REG_BAR3_CONFIG};
uint32 origidx = si_coreidx(sih);
/* Disable/restore ASPM Control to protect the watchdog reset */
W_REG(osh, &sbpcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
lsc = R_REG(osh, &sbpcieregs->configdata);
val = lsc & (~PCIE_ASPM_ENAB);
W_REG(osh, &sbpcieregs->configdata, val);
si_setcore(sih, PCIE2_CORE_ID, 0);
si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, 4);
OSL_DELAY(100000);
#ifdef BCMQT
OSL_DELAY(200000);
#endif /* BCMQT */
W_REG(osh, &sbpcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
W_REG(osh, &sbpcieregs->configdata, lsc);
/* Write configuration registers back to the shadow registers
* cause shadow registers are cleared out after watchdog reset.
*/
for (i = 0; i < ARRAYSIZE(cfg_offset); i++) {
W_REG(osh, &sbpcieregs->configaddr, cfg_offset[i]);
val = R_REG(osh, &sbpcieregs->configdata);
W_REG(osh, &sbpcieregs->configdata, val);
}
si_setcoreidx(sih, origidx);
}
示例15: flash_poll
static int
flash_poll(unsigned long off, uint16 data)
{
unsigned long addr;
int cnt = FLASH_TRIES;
uint16 st;
ASSERT(flashutl_desc != NULL);
if (flashutl_desc->type == AMD || flashutl_desc->type == SST) {
/* AMD style poll checkes the address being written */
addr = FLASH_ADDR(off);
while ((st = flash_readword(addr)) != data && cnt != 0) {
OSL_DELAY(10);
cnt--;
}
if (cnt == 0) {
DPRINT(("%s: timeout, off %lx, read 0x%x, expected 0x%x\n",
__FUNCTION__, off, st, data));
return -1;
}
} else {
/* INTEL style poll is at second word of the block being written */
addr = FLASH_ADDR(block(off, BLOCK_BASE)+sizeof(uint16));
while (((st = flash_readword(addr)) & DONE) == 0 && cnt != 0) {
OSL_DELAY(10);
cnt--;
}
if (cnt == 0) {
DPRINT(("%s: timeout, error status = 0x%x\n", __FUNCTION__, st));
return -1;
}
}
return 0;
}