C++ NVIC_DisableIRQ函数代码示例

void USBHALHost::init() {
    NVIC_DisableIRQ(USB_IRQn);
    
    //Cut power
    LPC_SC->PCONP &= ~(1UL<<31);
    wait_ms(100);

    // turn on power for USB
    LPC_SC->PCONP       |= (1UL<<31);

    // Enable USB host clock, port selection and AHB clock
    LPC_USB->USBClkCtrl |= CLOCK_MASK;

    // Wait for clocks to become available
    while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK);

    // it seems the bits[0:1] mean the following
    // 0: U1=device, U2=host
    // 1: U1=host, U2=host
    // 2: reserved
    // 3: U1=host, U2=device
    // NB: this register is only available if OTG clock (aka "port select") is enabled!!
    // since we don't care about port 2, set just bit 0 to 1 (U1=host)
    LPC_USB->OTGStCtrl |= 1;

    // now that we've configured the ports, we can turn off the portsel clock
    LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;

    // configure USB D+/D- pins
    // P0[29] = USB_D+, 01
    // P0[30] = USB_D-, 01
    LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
    LPC_PINCON->PINSEL1 |=  ((1<<26) | (1<<28));

    LPC_USB->HcControl       = 0; // HARDWARE RESET
    LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero
    LPC_USB->HcBulkHeadED    = 0; // Initialize Bulk list head to Zero

    // Wait 100 ms before apply reset
    wait_ms(100);

    // software reset
    LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
    
    // Write Fm Interval and Largest Data Packet Counter
    LPC_USB->HcFmInterval    = DEFAULT_FMINTERVAL;
    LPC_USB->HcPeriodicStart = FI * 90 / 100;

    // Put HC in operational state
    LPC_USB->HcControl  = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
    // Set Global Power
    LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;

    LPC_USB->HcHCCA = (uint32_t)(usb_hcca);
    
    // Clear Interrrupt Status
    LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;

    LPC_USB->HcInterruptEnable  = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;

    // Enable the USB Interrupt
    NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr));
    LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
    LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;

    NVIC_EnableIRQ(USB_IRQn);

    // Check for any connected devices
    if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
        //Device connected
        wait_ms(150);
        USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1);
        deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
    }
}

void timer_irq_disable(tim_t dev)
{
    NVIC_DisableIRQ(timer_config[dev].irq);
}

void gpio_irq_disable(gpio_irq_t *obj) {
    NVIC_DisableIRQ(EINT3_IRQn);
}

void eth_arch_disable_interrupts(void) {
    NVIC_DisableIRQ(ENET_IRQn);
}

//.........这里部分代码省略.........
			tasks[current_task].stack->r0 = current_task;
			break;
		case 0x3: /* write */
			_write(&tasks[current_task], tasks, task_count, pipes);
			break;
		case 0x4: /* read */
			_read(&tasks[current_task], tasks, task_count, pipes);
			break;
		case 0x5: /* interrupt_wait */
			/* Enable interrupt */
			NVIC_EnableIRQ(tasks[current_task].stack->r0);
			/* Block task waiting for interrupt to happen */
			tasks[current_task].status = TASK_WAIT_INTR;
			break;
		case 0x6: /* getpriority */
			{
				int who = tasks[current_task].stack->r0;
				if (who > 0 && who < (int)task_count)
					tasks[current_task].stack->r0 = tasks[who].priority;
				else if (who == 0)
					tasks[current_task].stack->r0 = tasks[current_task].priority;
				else
					tasks[current_task].stack->r0 = -1;
			} break;
		case 0x7: /* setpriority */
			{
				int who = tasks[current_task].stack->r0;
				int value = tasks[current_task].stack->r1;
				value = (value < 0) ? 0 : ((value > PRIORITY_LIMIT) ? PRIORITY_LIMIT : value);
				if (who > 0 && who < (int)task_count)
					tasks[who].priority = value;
				else if (who == 0)
					tasks[current_task].priority = value;
				else {
					tasks[current_task].stack->r0 = -1;
					break;
				}
				tasks[current_task].stack->r0 = 0;
			} break;
		case 0x8: /* mknod */
			if (tasks[current_task].stack->r0 < PIPE_LIMIT)
				tasks[current_task].stack->r0 =
					_mknod(&pipes[tasks[current_task].stack->r0],
						   tasks[current_task].stack->r2);
			else
				tasks[current_task].stack->r0 = -1;
			break;
		case 0x9: /* sleep */
			if (tasks[current_task].stack->r0 != 0) {
				tasks[current_task].stack->r0 += tick_count;
				tasks[current_task].status = TASK_WAIT_TIME;
			}
			break;
		default: /* Catch all interrupts */
			if ((int)tasks[current_task].stack->r8 < 0) {
				unsigned int intr = -tasks[current_task].stack->r8 - 16;

				if (intr == SysTick_IRQn) {
					/* Never disable timer. We need it for pre-emption */
					timeup = 1;
					tick_count++;
				}
				else {
					/* Disable interrupt, interrupt_wait re-enables */
					NVIC_DisableIRQ(intr);
				}
				/* Unblock any waiting tasks */
				for (i = 0; i < task_count; i++)
					if ((tasks[i].status == TASK_WAIT_INTR && tasks[i].stack->r0 == intr) ||
					    (tasks[i].status == TASK_WAIT_TIME && tasks[i].stack->r0 == tick_count))
						tasks[i].status = TASK_READY;
			}
		}

		/* Put waken tasks in ready list */
		for (task = wait_list; task != NULL;) {
			struct task_control_block *next = task->next;
			if (task->status == TASK_READY)
				task_push(&ready_list[task->priority], task);
			task = next;
		}
		/* Select next TASK_READY task */
		for (i = 0; i < (size_t)tasks[current_task].priority && ready_list[i] == NULL; i++);
		if (tasks[current_task].status == TASK_READY) {
			if (!timeup && i == (size_t)tasks[current_task].priority)
				/* Current task has highest priority and remains execution time */
				continue;
			else
				task_push(&ready_list[tasks[current_task].priority], &tasks[current_task]);
		}
		else {
			task_push(&wait_list, &tasks[current_task]);
		}
		while (ready_list[i] == NULL)
			i++;
		current_task = task_pop(&ready_list[i])->pid;
	}

	return 0;
}

/*****************************************************************************
Função que recebe o touch pressionado do capacitivo 4x4
*****************************************************************************/
void cmd_rcv_touch(char *par) 
{
	char i,touch,str_IdIr[4],str_aux[50],flag_send_ir = __TRUE;	 

	memset(str_IdIr,0,sizeof(str_IdIr));
	memset(str_aux,0,sizeof(str_aux));
	str_IdIr[0] = par[1];
	str_IdIr[1] = par[2];
	touch = atoi(str_IdIr);	
    
	if(!(touchEnaDis & (1<<touch)))
		return;

	NVIC_DisableIRQ(UART2_IRQn);
	NVIC_DisableIRQ(UART0_IRQn);
	
	if(touch > 23 && (par[0]-48))
	{
		sprintf(buf_tx,"ERROR %u",ERROR_PARAMETER);
		return;
	}

	if(par[0] - 48)	/*Transforma em inteiro*/
	{
		/*Desliga led anterior (IRs) caso ainda esteja ligado*/
		for(i=TOUCH_0;i<=TOUCH_23;i++)
		{
			if(i == TOUCH_11 && !ir_state.bit.PwrPainel)
				out_leds |= (1<<TOUCH_11);
			else
				out_leds &= ~(1 << i);
		}
			
		touch_led_press = touch;
		out_leds |= (1 << touch_led_press);
		atualiza_saidas();

		if(rcv_cmd != RCV_CMD_TCP_CLIENT && rcv_cmd != RCV_CMD_TCP_SERVER)
			beep(BEEP_PULSO);

		/*(TV)->ID0:Source...ID1:CH-...ID2:CH+...ID3:ON...ID4:OFF...ID5:Vol-...ID6:Vol+*/
		
		/*(HOME)->ID7:Source...ID8:VOL-...ID9:VOL+...ID10:ON...ID11:OFF...ID12:PLAY...ID13:PAUSE...ID14:BACK...ID15:NEXT*/
			/*ID16: Cursor Left...ID17: Cursor Righ...ID18: Cursor Down*/
		
		/*(AR)->ID19:16°...ID20:17°............ID33:30°...ID34:ON...ID35:OFF..ID36:SWING ON..ID37:SWING OFF*/

		if(touch == TOUCH_0)	/*Touch referente ao Power da TV*/
		{
			if(!ir_state.bit.PwrTv)strcpy(str_IdIr,ADDR_TV_ON);		/*IR power tv on*/
			else				   strcpy(str_IdIr,ADDR_TV_OFF);	/*IR power tv off*/

			ir_state.bit.PwrTv = !ir_state.bit.PwrTv;
			sprintf(str_aux,"[Touch (%u) POWER %s TV]\r",touch,(ir_state.bit.PwrTv) ? "ON":"OFF");	/*String para debug*/

		}else
		if(touch == TOUCH_1)	/*Touch referente ao Source da TV*/
		{
			strcpy(str_IdIr,ADDR_TV_SCR);		/*IR source tv*/
			sprintf(str_aux,"[SOURCE TV]\r");	/*String para debug*/
				
		}else
		if(touch == TOUCH_2)	/*Touch referente ao CH- da TV*/
		{
			strcpy(str_IdIr,ADDR_TV_CH_DOWN);	/*IR ch- tv*/
			sprintf(str_aux,"[CH- TV]\r");		/*String para debug*/	
			
		}else
		if(touch == TOUCH_3)	/*Touch referente ao CH+ da TV*/									
		{
			strcpy(str_IdIr,ADDR_TV_CH_UP);		/*IR ch+ tv*/
			sprintf(str_aux,"[CH+ TV]\r");		/*String para debug*/	

		}else 
		if(touch == TOUCH_4)	/*Touch referente ao Power Home*/
		{
			if(!ir_state.bit.PwrHome)strcpy(str_IdIr,ADDR_HOME_ON); 	/*IR Power home on*/
			else				     strcpy(str_IdIr,ADDR_HOME_OFF); 	/*IR Power home off*/

			ir_state.bit.PwrHome = !ir_state.bit.PwrHome;
			sprintf(str_aux,"[POWER %s HOME]\r",(ir_state.bit.PwrHome) ? "ON":"OFF");	/*String para debug*/

		}else
		if(touch == TOUCH_5)	/*Touch referente ao Source do Home*/
		{
			strcpy(str_IdIr,ADDR_HOME_SCR);		/*IR source home*/
			sprintf(str_aux,"[SOURCE HOME]\r");	/*String para debug*/

		}else
		if(touch == TOUCH_6)	/*Touch referente ao Volume- da Tv*/
		{
			strcpy(str_IdIr,ADDR_TV_VOL_DOWN);	/*IR vol- tv*/
			sprintf(str_aux,"[VOL- TV]\r");		/*String para debug*/
			
			/*Envia repetidamente o IR apenas se pressionar no teclado. Pelo software executa o IR apenas uma vez*/
			if(rcv_cmd == RCV_CMD_UART_2)		
			{
//.........这里部分代码省略.........

/**
  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
  * @param  IRQn External interrupt number .
  *         This parameter can be an enumerator of IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)  
  * @retval None
  */
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
  /* Disable interrupt */
  NVIC_DisableIRQ(IRQn);
}

/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
    uint32_t i;

    /* Unlock protected registers */
    SYS_UnlockReg();

    /* Init System, IP clock and multi-function I/O */
    SYS_Init();

    /* Init UART0 for printf */
    UART0_Init();

    /* Lock protected registers */
    SYS_LockReg();;

    /*
        This sample code is I2C SLAVE mode and it simulates EEPROM function
    */
    printf("\n");
    printf("+---------------------------------------------------------------------------+\n");
    printf("| NUC029xEE I2C Driver Sample Code (Slave) for wake-up & access Slave test  |\n");
    printf("|                                                                           |\n");
    printf("| I2C Master (I2C0) <---> I2C Slave(I2C0)                                   |\n");
    printf("+---------------------------------------------------------------------------+\n");

    printf("Configure I2C0 as a slave.\n");
    printf("The I/O connection for I2C0:\n");
    printf("I2C0_SDA(PA.8), I2C0_SCL(PA.9)\n");

    /* Init I2C0 */
    I2C0_Init();

    for(i = 0; i < 0x100; i++)
    {
        g_au8SlvData[i] = 0;
    }

    /* I2C function to Transmit/Receive data as slave */
    s_I2C0HandlerFn = I2C_SlaveTRx;
		
    /* Set I2C0 enter Not Address SLAVE mode */
    I2C_SET_CONTROL_REG(I2C0, I2C_I2CON_SI_AA);

    /* Unlock protected registers */
    SYS_UnlockReg();

    /* Enable power wake-up interrupt */
    CLK->PWRCON |= CLK_PWRCON_PD_WU_INT_EN_Msk;
    NVIC_EnableIRQ(PWRWU_IRQn);

    /* Enable I2C wake-up */
    I2C0-> I2CWKUPCON |= I2C_I2CWKUPCON_WKUPEN_Msk;

    /* Enable Chip enter power down mode */
    CLK->PWRCON |= CLK_PWRCON_PD_WAIT_CPU_Msk;

    /* Processor use deep sleep */
    SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;

    /* System power down enable */
    CLK->PWRCON |= CLK_PWRCON_PWR_DOWN_EN_Msk;

    printf("\n");
    printf("Enter PD 0x%x 0x%x\n", I2C0->I2CON , I2C0->I2CSTATUS);
    printf("\n");
    printf("CHIP enter power down status.\n");
    /* Waiting for UART printf finish*/
    while(((UART0->FSR) & UART_FSR_TE_FLAG_Msk) == 0);

    if(((I2C0->I2CON)&I2C_I2CON_SI_Msk) != 0)
    {
        I2C_SET_CONTROL_REG(I2C0, I2C_I2CON_SI);
    }

    /*  Use WFI instruction to idle the CPU. NOTE:
        If ICE is attached, system will wakeup immediately because ICE is a wakeup event. */
    __WFI();
    __NOP();
    __NOP();
    __NOP();

    while((g_u8SlvPWRDNWK & g_u8SlvI2CWK) == 0);    
    printf("Power-down Wake-up INT 0x%x\n", ((CLK->PWRCON) & CLK_PWRCON_PD_WU_STS_Msk));		
    printf("I2C0 WAKE INT 0x%x\n", I2C0->I2CWKUPSTS);
		
    /* Disable power wake-up interrupt */
    CLK->PWRCON &= ~CLK_PWRCON_PD_WU_INT_EN_Msk;
    NVIC_DisableIRQ(PWRWU_IRQn);

    /* Lock protected registers */
    SYS_LockReg();

    printf("\n");
    printf("Slave wake-up from power down status.\n");

    printf("\n");
    printf("Slave Waiting for receiving data.\n");

//.........这里部分代码省略.........

OSStatus platform_uart_deinit( platform_uart_driver_t* driver )
{
  uint8_t          uart_number;
  OSStatus          err = kNoErr;

  platform_mcu_powersave_disable();

  require_action_quiet( ( driver != NULL ), exit, err = kParamErr);

  uart_number = platform_uart_get_port_number( driver->peripheral->port );

  /* Disable USART */
  USART_Cmd( driver->peripheral->port, DISABLE );

  /* Deinitialise USART */
  USART_DeInit( driver->peripheral->port );

  /**************************************************************************
   * De-initialise STM32 DMA and interrupt
   **************************************************************************/

  /* Deinitialise DMA streams */
  DMA_DeInit( driver->peripheral->tx_dma_config.stream );
  DMA_DeInit( driver->peripheral->rx_dma_config.stream );

  /* Disable TC (transfer complete) interrupt at the source */
  DMA_ITConfig( driver->peripheral->tx_dma_config.stream, DMA_INTERRUPT_FLAGS, DISABLE );
  DMA_ITConfig( driver->peripheral->rx_dma_config.stream, DMA_INTERRUPT_FLAGS, DISABLE );

  /* Disable transmit DMA interrupt at Cortex-M3 */
  NVIC_DisableIRQ( driver->peripheral->tx_dma_config.irq_vector );

  /**************************************************************************
   * De-initialise STM32 USART interrupt
   **************************************************************************/

  USART_ITConfig( driver->peripheral->port, USART_IT_RXNE, DISABLE );

  /* Disable UART interrupt vector on Cortex-M3 */
  NVIC_DisableIRQ( driver->peripheral->rx_dma_config.irq_vector );

  /* Disable registers clocks */
  uart_peripheral_clock_functions[uart_number]( uart_peripheral_clocks[uart_number], DISABLE );

#ifndef NO_MICO_RTOS
  mico_rtos_deinit_semaphore( &driver->rx_complete );
  mico_rtos_deinit_semaphore( &driver->tx_complete );
  mico_rtos_deinit_mutex( &driver->tx_mutex );
#else
  driver->rx_complete = false;
  driver->tx_complete = false;
#endif
  driver->rx_size              = 0;
  driver->tx_size              = 0;
  driver->last_transmit_result = kNoErr;
  driver->last_receive_result  = kNoErr;

exit:
    platform_mcu_powersave_enable();
    return err;
}

static
int
usart_configure_as_uart (sBSPACMperiphUARTstate * usp,
                         const sBSPACMperiphUARTconfiguration * cfgp)
{
  USART_TypeDef * usart;
  const sBSPACMdeviceEFM32periphUARTdevcfg * devcfgp;

  if (! (usp && usp->uart)) {
    return -1;
  }
  usart = (USART_TypeDef *)usp->uart;

  /* For a USART the devcfgp object is actual a
   * sBSPACMdeviceEFM32periphUSARTdevcfg, but that structure simply
   * extends the UART part of the configuration. */
  devcfgp = (const sBSPACMdeviceEFM32periphUARTdevcfg *)usp->devcfg.ptr;

  /* If enabling configuration, enable the high-frequency peripheral
   * clock and the clock for the uart itself.
   *
   * If disabling configuration, disable the interrupts. */
  if (cfgp) {
    CMU_ClockEnable(cmuClock_HFPER, true);
    CMU_ClockEnable(devcfgp->common.clock, true);
  } else {
    NVIC_DisableIRQ(devcfgp->rx_irqn);
    NVIC_DisableIRQ(devcfgp->tx_irqn);
    NVIC_ClearPendingIRQ(devcfgp->rx_irqn);
    NVIC_ClearPendingIRQ(devcfgp->tx_irqn);
  }
  USART_Reset(usart);
  if (usp->rx_fifo_ni_) {
    fifo_reset(usp->rx_fifo_ni_);
  }
  if (usp->tx_fifo_ni_) {
    fifo_reset(usp->tx_fifo_ni_);
  }
  usp->tx_state_ = 0;

  if (cfgp) {
    unsigned int baud_rate = cfgp->speed_baud;

    if (0 == baud_rate) {
      baud_rate = 115200;
    }
    /* Configure the USART for 8N1.  Set TXBL at half-full. */
    usart->FRAME = USART_FRAME_DATABITS_EIGHT | USART_FRAME_PARITY_NONE | USART_FRAME_STOPBITS_ONE;
    usart->CTRL |= USART_CTRL_TXBIL_HALFFULL;
    USART_BaudrateAsyncSet(usart, 0, baud_rate, usartOVS16);
    CMU_ClockEnable(cmuClock_GPIO, true);
  } else {
    /* Done with device; turn it off */
    CMU_ClockEnable(devcfgp->common.clock, false);
  }

  /* Enable or disable UART pins. To avoid false start, when enabling
   * configure TX as high.  This relies on a comment in the EMLIB code
   * that manipulating registers of disabled modules has no effect
   * (unlike TM4C where it causes a HardFault).  We'll see. */
  vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.rx_pinmux, !!cfgp, 1);
  vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.tx_pinmux, !!cfgp, 0);

  if (cfgp) {
    usart->ROUTE = USART_ROUTE_RXPEN | USART_ROUTE_TXPEN | devcfgp->common.location;

    /* Clear and enable RX interrupts.  TX interrupts are enabled at the
     * peripheral when there's something to transmit.  TX and RX are
     * enabled at the NVIC now. */
    usart->IFC = _USART_IF_MASK;
    usart->IEN = USART_IF_RXDATAV;
    NVIC_ClearPendingIRQ(devcfgp->rx_irqn);
    NVIC_ClearPendingIRQ(devcfgp->tx_irqn);
    NVIC_EnableIRQ(devcfgp->rx_irqn);
    NVIC_EnableIRQ(devcfgp->tx_irqn);

    /* Configuration complete; enable the USART */
    usart->CMD = USART_CMD_RXEN | USART_CMD_TXEN;
  }

  return 0;
}

void dbg_setup_uart_default(uint32_t baudrate)
{
        uint32_t fDiv;
        uint32_t regVal;
        
        NVIC_DisableIRQ(UART_IRQn);
        
        /* Set 1.6 UART RXD */
        IOCON_PIO1_6 &= ~IOCON_PIO1_6_FUNC_MASK;
        IOCON_PIO1_6 |= IOCON_PIO1_6_FUNC_UART_RXD;
        
        /* Set 1.7 UART TXD */
        IOCON_PIO1_7 &= ~IOCON_PIO1_7_FUNC_MASK;      
        IOCON_PIO1_7 |= IOCON_PIO1_7_FUNC_UART_TXD;
        
        /* Enable UART clock */
        SCB_SYSAHBCLKCTRL |= (SCB_SYSAHBCLKCTRL_UART);
        SCB_UARTCLKDIV = SCB_UARTCLKDIV_DIV1;     /* divided by 1 */
        
        /* 8 bits, no Parity, 1 Stop bit */
        UART_U0LCR = (UART_U0LCR_Word_Length_Select_8Chars |
                      UART_U0LCR_Stop_Bit_Select_1Bits |
                      UART_U0LCR_Parity_Disabled |
                      UART_U0LCR_Parity_Select_OddParity |
                      UART_U0LCR_Break_Control_Disabled |
                      UART_U0LCR_Divisor_Latch_Access_Enabled);
        
        /* Baud rate */
        regVal = SCB_UARTCLKDIV;
        fDiv = (((CFG_CPU_CCLK * SCB_SYSAHBCLKDIV)/regVal)/16)/baudrate;
        
        UART_U0DLM = fDiv / 256;
        UART_U0DLL = fDiv % 256;
        
        /* Set DLAB back to 0 */
        UART_U0LCR = (UART_U0LCR_Word_Length_Select_8Chars |
                      UART_U0LCR_Stop_Bit_Select_1Bits |
                      UART_U0LCR_Parity_Disabled |
                      UART_U0LCR_Parity_Select_OddParity |
                      UART_U0LCR_Break_Control_Disabled |
                      UART_U0LCR_Divisor_Latch_Access_Disabled);
        
        /* Enable and reset TX and RX FIFO. */
        UART_U0FCR = (UART_U0FCR_FIFO_Enabled | 
                      UART_U0FCR_Rx_FIFO_Reset | 
                      UART_U0FCR_Tx_FIFO_Reset); 
        
        /* Read to clear the line status. */
        regVal = UART_U0LSR;
        
        /* Ensure a clean start, no data in either TX or RX FIFO. */
        while (( UART_U0LSR & (UART_U0LSR_THRE|UART_U0LSR_TEMT)) != (UART_U0LSR_THRE|UART_U0LSR_TEMT) );
        while ( UART_U0LSR & UART_U0LSR_RDR_DATA )
        {
                /* Dump data from RX FIFO */
                regVal = UART_U0RBR;
        }
        
        /* Enable the UART Interrupt */
        NVIC_EnableIRQ(UART_IRQn);
        UART_U0IER = UART_U0IER_RBR_Interrupt_Enabled | UART_U0IER_RLS_Interrupt_Enabled;
        
        return;

}

static int
leuart_configure (sBSPACMperiphUARTstate * usp,
                  const sBSPACMperiphUARTconfiguration * cfgp)
{
  LEUART_TypeDef * leuart;
  const sBSPACMdeviceEFM32periphLEUARTdevcfg * devcfgp;

  if (! (usp && usp->uart)) {
    return -1;
  }
  leuart = (LEUART_TypeDef *)usp->uart;
  devcfgp = (const sBSPACMdeviceEFM32periphLEUARTdevcfg *)usp->devcfg.ptr;

  /* Configure LFB's source, enable the low-energy peripheral clock, and the clock for the
   * leuart itself */
  if (cfgp) {
    /* LFB is required for LEUART.  Power-up is LFRCO which doesn't
     * work so good; if we were told a source to use, override
     * whatever was there. */
    if (devcfgp->lfbsel) {
      CMU_ClockSelectSet(cmuClock_LFB, devcfgp->lfbsel);
    }
    CMU_ClockEnable(cmuClock_CORELE, true);
    CMU_ClockEnable(devcfgp->common.clock, true);
  } else {
    NVIC_DisableIRQ(devcfgp->irqn);
    NVIC_ClearPendingIRQ(devcfgp->irqn);
  }
  LEUART_Reset(leuart);
  leuart->FREEZE = LEUART_FREEZE_REGFREEZE;
  leuart->CMD = LEUART_CMD_RXDIS | LEUART_CMD_TXDIS;
  if (usp->rx_fifo_ni_) {
    fifo_reset(usp->rx_fifo_ni_);
  }
  if (usp->tx_fifo_ni_) {
    fifo_reset(usp->tx_fifo_ni_);
  }
  usp->tx_state_ = 0;

  if (cfgp) {
    unsigned int speed_baud = cfgp->speed_baud;
    if (0 == speed_baud) {
      speed_baud = 9600;
    }
    /* Configure the LEUART for rate at 8N1. */
    leuart->CTRL = LEUART_CTRL_DATABITS_EIGHT | LEUART_CTRL_PARITY_NONE | LEUART_CTRL_STOPBITS_ONE;
    LEUART_BaudrateSet(leuart, 0, speed_baud);
    CMU_ClockEnable(cmuClock_GPIO, true);
  }

  /* Enable or disable UART pins. To avoid false start, when enabling
   * configure TX as high.  This relies on a comment in the EMLIB code
   * that manipulating registers of disabled modules has no effect
   * (unlike TM4C where it causes a HardFault).  We'll see. */
  vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.rx_pinmux, !!cfgp, 1);
  vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.tx_pinmux, !!cfgp, 0);

  if (cfgp) {
    leuart->ROUTE = LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | devcfgp->common.location;

    /* Clear and enable RX interrupts at the device.  Device TX
     * interrupts are enabled at the peripheral when there's something
     * to transmit.  Clear then enable interrupts at the NVIC. */
    leuart->IFC = _LEUART_IF_MASK;
    leuart->IEN = LEUART_IF_RXDATAV;
    NVIC_ClearPendingIRQ(devcfgp->irqn);
    NVIC_EnableIRQ(devcfgp->irqn);

    /* Configuration complete; enable the LEUART, and release the
     * registers to synchronize. */
    leuart->CMD = LEUART_CMD_RXEN | LEUART_CMD_TXEN;
    leuart->FREEZE = 0;
  } else {
    CMU_ClockEnable(devcfgp->common.clock, false);
  }
  return 0;
}

static
hBSPACMperiphUART
spi_configure (sBSPACMperiphUARTstate * usp,
               const sBSPACMperiphUARTconfiguration * cfgp)
{
  USART_TypeDef * usart;
  const sBSPACMdeviceEFM32periphUSARTdevcfg * devcfgp;

  if (! (usp && usp->uart)) {
    return NULL;
  }
  usart = (USART_TypeDef *)usp->uart;
  devcfgp = (const sBSPACMdeviceEFM32periphUSARTdevcfg *)usp->devcfg.ptr;

  /* If enabling configuration, enable the high-frequency peripheral
   * clock and the clock for the uart itself.
   *
   * If disabling configuration, disable the interrupts. */
  if (cfgp) {
    CMU_ClockEnable(cmuClock_HFPER, true);
    CMU_ClockEnable(devcfgp->uart.common.clock, true);
  } else {
    NVIC_DisableIRQ(devcfgp->uart.rx_irqn);
    NVIC_DisableIRQ(devcfgp->uart.tx_irqn);
    NVIC_ClearPendingIRQ(devcfgp->uart.rx_irqn);
    NVIC_ClearPendingIRQ(devcfgp->uart.tx_irqn);
  }
  USART_Reset(usart);
  if (usp->rx_fifo_ni_) {
    fifo_reset(usp->rx_fifo_ni_);
  }
  if (usp->tx_fifo_ni_) {
    fifo_reset(usp->tx_fifo_ni_);
  }
  usp->tx_state_ = 0;

  if (cfgp) {
    /* Setting baudrate */
    usart->CLKDIV = 128 * (SystemCoreClock / 1000000UL - 2);

    /* Configure USART */
    /* Using synchronous (USART) mode, MSB first */
    usart->CTRL = USART_CTRL_SYNC | USART_CTRL_MSBF;
    // NOT AUTOCS
    // usart->CTRL |= USART_CTRL_AUTOCS
    /* Clearing old transfers/receptions, and disabling interrupts */
    usart->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX;
    usart->IEN = 0;

    /* Enabling Master, TX and RX */
    CMU_ClockEnable(cmuClock_GPIO, true);
  } else {
    /* Done with device; turn it off */
    CMU_ClockEnable(devcfgp->uart.common.clock, false);
  }

  /* Enable or disable UART pins. To avoid false start, when enabling
   * configure TX as high.  This relies on a comment in the EMLIB code
   * that manipulating registers of disabled modules has no effect
   * (unlike TM4C where it causes a HardFault).  We'll see. */
  vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->uart.common.rx_pinmux, !!cfgp, 0);
  vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->uart.common.tx_pinmux, !!cfgp, 0);
  vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->clk_pinmux, !!cfgp, 0);
  vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->cs_pinmux, !!cfgp, 1);

  if (cfgp) {
    /* Enabling pins and setting location */
    usart->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN | USART_ROUTE_CSPEN | devcfgp->uart.common.location;

    /* Clear and enable RX interrupts.  TX interrupts are enabled at the
     * peripheral when there's something to transmit.  TX and RX are
     * enabled at the NVIC now. */
    usart->IFC = _USART_IF_MASK;
    //usart->IEN = USART_IF_RXDATAV;
    NVIC_ClearPendingIRQ(devcfgp->uart.rx_irqn);
    NVIC_ClearPendingIRQ(devcfgp->uart.tx_irqn);
    NVIC_EnableIRQ(devcfgp->uart.rx_irqn);
    NVIC_EnableIRQ(devcfgp->uart.tx_irqn);

    /* Configuration complete; enable the USART */
    usart->CMD = USART_CMD_MASTEREN | USART_CMD_TXEN | USART_CMD_RXEN;
  }

  return usp;
}

/*..........................................................................*/
uint8_t QS_onStartup(void const *arg) {
    static uint8_t qsBuf[QS_BUF_SIZE];            /* buffer for Quantum Spy */
    QS_initBuf(qsBuf, sizeof(qsBuf));

    UARTInit(QS_BAUD_RATE); /*initialize the UART with the desired baud rate*/
    NVIC_DisableIRQ(UART_IRQn);/*do not use the interrupts (QS uses polling)*/
    LPC_UART->IER = 0;

    QS_tickPeriod_ = (QSTimeCtr)(SystemCoreClock / BSP_TICKS_PER_SEC);
    QS_tickTime_ = QS_tickPeriod_;        /* to start the timestamp at zero */

                                                 /* setup the QS filters... */
    QS_FILTER_ON(QS_ALL_RECORDS);

//    QS_FILTER_OFF(QS_QEP_STATE_EMPTY);
//    QS_FILTER_OFF(QS_QEP_STATE_ENTRY);
//    QS_FILTER_OFF(QS_QEP_STATE_EXIT);
//    QS_FILTER_OFF(QS_QEP_STATE_INIT);
//    QS_FILTER_OFF(QS_QEP_INIT_TRAN);
//    QS_FILTER_OFF(QS_QEP_INTERN_TRAN);
//    QS_FILTER_OFF(QS_QEP_TRAN);
//    QS_FILTER_OFF(QS_QEP_IGNORED);

    QS_FILTER_OFF(QS_QF_ACTIVE_ADD);
    QS_FILTER_OFF(QS_QF_ACTIVE_REMOVE);
    QS_FILTER_OFF(QS_QF_ACTIVE_SUBSCRIBE);
    QS_FILTER_OFF(QS_QF_ACTIVE_UNSUBSCRIBE);
    QS_FILTER_OFF(QS_QF_ACTIVE_POST_FIFO);
    QS_FILTER_OFF(QS_QF_ACTIVE_POST_LIFO);
    QS_FILTER_OFF(QS_QF_ACTIVE_GET);
    QS_FILTER_OFF(QS_QF_ACTIVE_GET_LAST);
    QS_FILTER_OFF(QS_QF_EQUEUE_INIT);
    QS_FILTER_OFF(QS_QF_EQUEUE_POST_FIFO);
    QS_FILTER_OFF(QS_QF_EQUEUE_POST_LIFO);
    QS_FILTER_OFF(QS_QF_EQUEUE_GET);
    QS_FILTER_OFF(QS_QF_EQUEUE_GET_LAST);
    QS_FILTER_OFF(QS_QF_MPOOL_INIT);
    QS_FILTER_OFF(QS_QF_MPOOL_GET);
    QS_FILTER_OFF(QS_QF_MPOOL_PUT);
    QS_FILTER_OFF(QS_QF_PUBLISH);
    QS_FILTER_OFF(QS_QF_NEW);
    QS_FILTER_OFF(QS_QF_GC_ATTEMPT);
    QS_FILTER_OFF(QS_QF_GC);
//    QS_FILTER_OFF(QS_QF_TICK);
    QS_FILTER_OFF(QS_QF_TIMEEVT_ARM);
    QS_FILTER_OFF(QS_QF_TIMEEVT_AUTO_DISARM);
    QS_FILTER_OFF(QS_QF_TIMEEVT_DISARM_ATTEMPT);
    QS_FILTER_OFF(QS_QF_TIMEEVT_DISARM);
    QS_FILTER_OFF(QS_QF_TIMEEVT_REARM);
    QS_FILTER_OFF(QS_QF_TIMEEVT_POST);
    QS_FILTER_OFF(QS_QF_CRIT_ENTRY);
    QS_FILTER_OFF(QS_QF_CRIT_EXIT);
    QS_FILTER_OFF(QS_QF_ISR_ENTRY);
    QS_FILTER_OFF(QS_QF_ISR_EXIT);

//    QS_FILTER_OFF(QS_QK_MUTEX_LOCK);
//    QS_FILTER_OFF(QS_QK_MUTEX_UNLOCK);
    QS_FILTER_OFF(QS_QK_SCHEDULE);

    return (uint8_t)1;                                    /* return success */
}

/**
 *
 * @brief Disable an interrupt line
 *
 * Disable an interrupt line. After this call, the CPU will stop receiving
 * interrupts for the specified <irq>.
 *
 * @return N/A
 */
void z_arch_irq_disable(unsigned int irq)
{
	NVIC_DisableIRQ((IRQn_Type)irq);
}