C++ MSTP函数代码示例

/*******************************************************************************
* Outline      : Stopping the peripherals which start operations after a reset
* Header       : r_init_stop_module.h
* Function Name: R_INIT_StopModule
* Description  : Configure the setting to enter module-stop state.
* Arguments    : none
* Return Value : none
*******************************************************************************/
void R_INIT_StopModule(void)
{
    /* ---- Enable write protection ---- */
    /* PRCR - Protect Register 
    b15:b8 PRKEY - PRC Key Code - A5h 
                  (The write value should be A5h to permission writing PRCi bit)
    b1     PRC1 - Protect Bit 1 - Write enabled */
    SYSTEM.PRCR.WORD = 0xA502;
    
    /* ---- Set transition to module-stop state ---- */
#if MSTP_STATE_DMACDTC == MODULE_STOP_ENABLE
    MSTP(DTC) = 1;            /* DMAC/DTC trans to module-stop state */
#endif
#if MSTP_STATE_EXDMAC == MODULE_STOP_ENABLE
    MSTP(EXDMAC) = 1;         /* EXDMAC trans to module-stop state */
#endif
#if MSTP_STATE_RAM0 == MODULE_STOP_ENABLE
    MSTP(RAM0) = 1;           /* RAM0 trans to module-stop state  */
#endif
#if MSTP_STATE_RAM1 == MODULE_STOP_ENABLE
    MSTP(RAM1) = 1;           /* RAM1 trans to module-stop state  */
#endif
    
    /* ---- Disable write protection ---- */
    /* PRCR - Protect Register 
    b15:b8 PRKEY - PRC Key Code - A5h 
                  (The write value should be A5h to permission writing PRCi bit)
    b1     PRC1 - Protect Bit 1 - Write disabled*/
    SYSTEM.PRCR.WORD = 0xA500;
}

/******************************************************************************
* Function name : cmt_init
* Description   : Create one-shot timers based on PCLK / 3
* Arguments     : None
* Return Value  : None
******************************************************************************/
void cmt_init(void)
{
    #ifdef PLATFORM_BOARD_RDKRX63N
	SYSTEM.PRCR.WORD = 0xA50B; /* Protect off */
    #endif
    
    /* Cancel CMT module stop state. */
    MSTP(CMT0) = 0;  
    
	MSTP(CMT1) = 0;
	
    #ifdef PLATFORM_BOARD_RDKRX63N
	SYSTEM.PRCR.WORD = 0xA500; /* Protect on  */
    #endif  

    /* Compare Match Timer Control Register (CMCR) 
    b15:b8  reserved:   Read/Write value always 0
    b7      reserved:   Read undef. Write value always 1
    b6      CMIE:       Compare Match Interrupt Enable                
    b5:b2   reserved:   Read/Write value always 0
    b1:b0   CKS:        clock select   3 = count on PCLK / 512  
    */
    CMT0.CMCR.WORD = 0x0003; /* Just set clock divisor for now. */
    CMT1.CMCR.WORD = 0x0003; 
    CMT2.CMCR.WORD = 0x0003;
	    
    /* Compare Match Timer Counter (CMCNT)
    b15:b0  16-bit readable/writable up-counter to generate interrupt requests.
    */
    CMT0.CMCNT = 0x00;      /* Clear the count (default value). */
    CMT1.CMCNT = 0x00;      
    CMT2.CMCNT = 0x00;
	    
    /* Compare Match Timer Constant Register (CMCOR))
    b15:b0  16-bit register sets the value for a compare match with CMCNT.
    */ 
    CMT0.CMCOR = 0xFFFF;    /* Set to max (default value). */
    CMT1.CMCOR = 0xFFFF;    
	CMT2.CMCOR = 0xFFFF;

    IR (CMT0, CMI0);        /* Interrupt reset.  */ 
    IR (CMT1, CMI1);
	IR (CMT2, CMI2);
    
    IPR(CMT0, CMI0) = 4;    /* Interrupt priority set. */
    IPR(CMT1, CMI1) = 4; 
    IPR(CMT2, CMI2) = 4;
	       
    IEN(CMT0, CMI0) = 1;    /* Interrupt enable. */
    IEN(CMT1, CMI1) = 1;        
    IEN(CMT2, CMI2) = 1;
	
} /* End of function cmt_init() */

/* The RX port uses this callback function to configure its tick interrupt.
This allows the application to choose the tick interrupt source. */
void vApplicationSetupTimerInterrupt( void )
{
const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL;

    /* Disable register write protection. */
    SYSTEM.PRCR.WORD = ulEnableRegisterWrite;

	/* Enable compare match timer 0. */
	MSTP( CMT0 ) = 0;

	/* Interrupt on compare match. */
	CMT0.CMCR.BIT.CMIE = 1;

	/* Set the compare match value. */
	CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 );

	/* Divide the PCLK by 8. */
	CMT0.CMCR.BIT.CKS = 0;

	/* Enable the interrupt... */
	_IEN( _CMT0_CMI0 ) = 1;

	/* ...and set its priority to the application defined kernel priority. */
	_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;

	/* Start the timer. */
	CMT.CMSTR0.BIT.STR0 = 1;

    /* Reneable register protection. */
    SYSTEM.PRCR.WORD = ulDisableRegisterWrite;
}

void MTU5W_Setup() {
	// Unlock ports
#ifdef PLATFORM_BOARD_RDKRX63N
	SYSTEM.PRCR.WORD = 0xA50B;
#endif

	/* Setup echo read port PD5 (pin 18 on jn2) input */
	// Input data register
	PORTD.PIDR.BIT.B5 = 0x0;
	// Direction register (input)
	PORTD.PDR.BIT.B5 = 0x0;
	// Mode register (peripheral)
	PORTD.PMR.BIT.B5 = 0x1;

	// Turn on MTU5
	MSTP(MTU5) = 0;

	// Set MTU5 pre-scaler to PCLK/16
	MTU5.TCRW.BIT.TPSC = 0x02;
	// Make MTU5W count
	MTU5.TIORW.BYTE= 0x1d;
	// Enable interrupt on input detected
//	MTU5.TIER.BIT.TGIE5W = 0x1;
	// Use pin with timer
	MPC.PD5PFS.BIT.PSEL = 0x01;

	// Ensure timer is stopped
	MTU5W_Stop();

	// Lock ports
#ifdef PLATFORM_BOARD_RDKRX63N
	SYSTEM.PRCR.WORD = 0xA500;
#endif
}

void vApplicationSetupTimerInterrupt(void)
{
   //Disable protection
   SYSTEM.PRCR.WORD = 0xA50B;
   //Cancel CMT0 module stop state
   MSTP(CMT0) = 0;
   //Enable protection
   SYSTEM.PRCR.WORD = 0xA500;

   //Select PCLK/8 clock
   CMT0.CMCR.BIT.CKS = 0;
   //Set the compare match value
   CMT0.CMCOR = ((PCLK_HZ / configTICK_RATE_HZ) - 1) / 8;

   //Interrupt on compare match
   CMT0.CMCR.BIT.CMIE = 1;

   //Set interrupt priority
   _IPR(_CMT0_CMI0) = configKERNEL_INTERRUPT_PRIORITY;
   //Enable compare match interrupt
   _IEN(_CMT0_CMI0) = 1;

   //Start timer
   CMT.CMSTR0.BIT.STR0 = 1;
}

/******************************************************************************
Function Name   : vApplicationSetupTimerInterrupt
Description     : setup tick timer
Arguments       : none
Return value    : none
******************************************************************************/
void vApplicationSetupTimerInterrupt( void )
{
    /* protect off */
    SYSTEM.PRCR.WORD = 0xA502;

    /* Enable compare match timer 0. */
    MSTP( CMT0 ) = 0;

    /* Interrupt on compare match. */
    //CMT0.CMCR.BIT.CMIE = 1;
    /* Divide the PCLK by 8. */
    //CMT0.CMCR.BIT.CKS = 0;
    CMT0.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @48MHz
    /* Set the compare match value. */
    CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1);

    /* Enable the interrupt... */
    _IEN( _CMT0_CMI0 ) = 1;
    
    /* ...and set its priority to the application defined kernel priority. */
    _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
    
    /* Start the timer. */
    CMT.CMSTR0.BIT.STR0 = 1;

    /* protect on */
    SYSTEM.PRCR.WORD = 0xA500;

}

HalSci5::HalSci5(){
	int i;

	PORTC.ICR.BIT.B2 = 1;
	PORTC.DDR.BIT.B2 = 0;
	PORTC.DDR.BIT.B3 = 1;

	MSTP(SCI5) = 0;

	SCI5.SCR.BYTE = 0x00;

	SCI5.SMR.BYTE = 0x00;

	SCI5.SCMR.BIT.SMIF= 0;
	SCI5.SCMR.BIT.SINV= 0;
	SCI5.SCMR.BIT.SDIR= 0;

	SCI5.BRR = 12;
	//SCI5.SEMR.BIT.ABCS = 1;
	for(i=0;i<0x800000;i++);
	SCI5.SCR.BYTE = 0x30;

	SCI5.SCR.BIT.TE=1;
	SCI5.SCR.BIT.TIE=1;

	SCI5.SCR.BIT.RE=1;
	SCI5.SCR.BIT.RIE=1;


	IEN(SCI5,RXI5)=0;
	IEN(SCI5,TXI5)=1;
	IPR(SCI5,TXI5)=GeneralConfig::gpsIpr;
	IPR(SCI5,RXI5)=GeneralConfig::gpsIpr;
}

/******************************************************************************
* ID : 61.0
* Outline : YRDKRX62N_RSPIConfig
* Include : YRDKRX62N_RSPI0.h
* Function Name: YRDKRX62N_RSPIConfig
* Description : Setup and ready the RSPI0 for communications.
* Argument : none
* Return Value : none
* Calling Functions : YRDKRX62N_RSPIOpen
******************************************************************************/
void YRDKRX62N_RSPIConfig(void)
{
    MSTP(RSPI0) = 0 ;

    /* Select proper bank of pins for SPI0 */
    IOPORT.PFGSPI.BIT.RSPIS = 0 ;
    /* SCK (PC.5) is active */
    IOPORT.PFGSPI.BIT.RSPCKE = 1 ;

    /* SSL3 (PC.2) is inactive (toggled as GPIO instead) */
    IOPORT.PFGSPI.BIT.SSL3E = 0 ;
    /* MOSI (PC.6) is active */
    IOPORT.PFGSPI.BIT.MOSIE = 1 ;

    /* Set up chip select pin */
    /* Make it an output */
    PORTC.DDR.BIT.B2 = 1 ;
    /* Set level to inactive */
    PORTC.DR.BIT.B2 = 1 ;

    /* MISO as an input */
    PORTC.DDR.BIT.B7 = 1 ;
    /* Enable input buffer for peripheral */
    PORTC.DR.BIT.B7 = 1 ;

    /* MOSI as an output */
    PORTC.DDR.BIT.B6 = 1 ;
    /* Enable input buffer for peripheral */
    PORTC.DR.BIT.B6 = 1 ;

    /* SCK as an output */
    PORTC.DDR.BIT.B5 = 1 ;
    /* Set level to inactive */
    PORTC.DR.BIT.B5 = 1 ;

    /* Initialize SPI (per flowchart in hardware manual) */
    /* No loopback, CMos Output */
    RSPI0.SPPCR.BYTE = 0x00 ;
    /* Full Speed is 0x00  255 works */
    RSPI0.SPBR.BYTE = 0x00 ;
    /* 16-bit data 1 frame 1 chip select */
    RSPI0.SPDCR.BYTE = 0x00 ;
    /* 2 clock delay before next access to SPI device */
    RSPI0.SPCKD.BYTE = 0x00 ;
    /* 2 clock delay after de-asserting SSL */
    RSPI0.SSLND.BYTE = 0x00 ;
    /* 2 clock delay before next access to SPI device */
    RSPI0.SPND.BYTE = 0x00 ;
    /* No parity no idle interrupts */
    RSPI0.SPCR2.BYTE = 0x00 ;
    /* MSB first 8-bit data, keep SSL low */
    RSPI0.SPCMD0.WORD = 0x0700 ;
    /* Enable RSPI 3wire in master mode with RSPI Enable Transmit Only and Interupt */
    RSPI0.SPCR.BYTE = 0x6B ;
    /* SSL3A Polarity */
    RSPI0.SSLP.BYTE = 0x08 ;
    /* One frame. */
    RSPI0.SPSCR.BYTE = 0x00 ;
}

/***********************************************************************************************************************
* Function Name: power_on_off
* Description  : Switches power to an MTU channel.  Required by FIT spec.
* Arguments    : channel -
*                   Which channel to use.
*                on_or_off -
*                   What it says.
* Return Value : none
***********************************************************************************************************************/
void power_on_off (uint8_t on_or_off)
{
    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR);

    MSTP(MTU) = on_or_off; // All channels are on the same module stop register.

    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR);
}

/*---------------------------------------------------------------------------*
 * Routine:  IADCConfig
 *---------------------------------------------------------------------------*
 * Description:
 *      Setup the ADC for reading but don't start it
 * Outputs:
 *      T_RX63N_ADC_Workspace *aW -- Particular ADC workspace
 *      ADC_RequestSingle *aRequest -- Configuration of ADC device
 *---------------------------------------------------------------------------*/
static void IADCConfig(
                T_RX63N_ADC_Workspace *p,
                ADC_RequestSingle *aRequest)
{
	// Ensure the power is on
	MSTP(S12AD) = 0;
	
	S12AD.ADCSR.BIT.ADST = 0;	//	0: Stops a scan conversion process.
								//	1: Starts a scan conversion process.
	
	S12AD.ADCSR.BIT.EXTRG = 0; 	//	0: 	Scan conversion is started by a timer 
								//		source selected by the A/D start
								//		trigger select register (ADSTRGR).
								//	1:	Scan conversion is started by an 
								//		external trigger (ADTRG0#).
								
	S12AD.ADCSR.BIT.TRGE = 0;	//	0: 	Disables scan conversion to be started 
								//		by an external trigger (ADTRG0#) or a 
								//		trigger of MTU or TMR.
								//	1: 	Enables scan conversion to be started 
								//		by an external trigger (ADTRG0#) or a 
								//		trigger of MTU or TMR.
	
	S12AD.ADCSR.BIT.CKS = 0;	//	00: PCLK/8
								//	01: PCLK/4
								//	10: PCLK/2
								//	11: PCLK
								
	S12AD.ADCSR.BIT.ADIE = 0;	//	0: 	Disables ADI interrupt generation 
								//		upon scan conversion completion.
								//	1: 	Enables ADI interrupt generation 
								//		upon scan conversion completion.
								
	S12AD.ADCSR.BIT.ADCS = 0;	//	0: 	Single-cycle scan mode
								//	1: 	Continuous scan mode
								
	S12AD.ADCER.BIT.ACE = 0;	//	0: 	Disables automatic clearing of the 
								//		A/D data register n (ADDRn) after 
								//		it has been read.
								//	1: 	Enables automatic clearing of the 
								//		A/D data register n (ADDRn) after 
								//		it has been read.
							
	S12AD.ADCER.BIT.ADRFMT = 0;	//	0: 	Right-alignment is selected for the 
								//		A/D data register n (ADDRn) format.
								//	1: 	Left-alignment is selected for the 
								//		A/D data register n (ADDRn) format.					
	
	// A/D Channel Select
	if(aRequest->iADCChannel < 16) {
		S12AD.ADANS0.WORD = 1<<aRequest->iADCChannel;
		S12AD.ADANS1.WORD = 0;
	} else {
		S12AD.ADANS0.WORD = 0;
		S12AD.ADANS1.WORD = 1<<(aRequest->iADCChannel-16);
	}
}

void vInitialiseTimerForIntQueueTest( void )
{
uint32_t ulCompareMatchValue;
const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL;

	/* Disable CMI2 and CMI3 interrupts. */
	VIC.IEC0.LONG = ( 1UL << 23UL ) | ( 1UL << 24UL );

	/* Cancel CMT stop state in LPC. */
	r_rst_write_enable();
	MSTP( CMT1 ) = 0U;
	r_rst_write_disable();

	/* Interrupt on compare match. */
	CMT2.CMCR.BIT.CMIE = 1;
	CMT3.CMCR.BIT.CMIE = 1;

	/* Calculate the compare match value. */
	ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider;
	ulCompareMatchValue /= ulCMTClockDivider;
	ulCompareMatchValue /= tmrCMT_1_CHANNEL_0_HZ;
	ulCompareMatchValue -= 1UL;
	CMT2.CMCOR = ( unsigned short ) ulCompareMatchValue;

	ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider;
	ulCompareMatchValue /= ulCMTClockDivider;
	ulCompareMatchValue /= tmrCMT_1_CHANNEL_1_HZ;
	ulCompareMatchValue -= 1UL;
	CMT3.CMCOR = ( unsigned short ) ulCompareMatchValue;

	/* Divide the PCLK by 8. */
	CMT2.CMCR.BIT.CKS = 0;
	CMT3.CMCR.BIT.CKS = 0;

	/* Clear count to 0. */
	CMT2.CMCNT = 0;
	CMT3.CMCNT = 0;

	/* Set CMI2 and CMI3 edge detection type. */
	VIC.PLS0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL );

	/* Set CMI2 and CMI3 priority levels so they nest. */
	VIC.PRL23.LONG = _CMT_PRIORITY_LEVEL2;
	VIC.PRL24.LONG = _CMT_PRIORITY_LEVEL9;

	/* Set CMI2 and CMI3 interrupt address. */
	VIC.VAD23.LONG = ( uint32_t ) vCMT_1_Channel_0_ISR_Entry;
	VIC.VAD24.LONG = ( uint32_t ) vCMT_1_Channel_1_ISR_Entry;

    /* Enable CMI2 and CMI3 interrupts in ICU. */
	VIC.IEN0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL );

    /* Start CMT1 channel 0 and 1 count. */
    CMT.CMSTR1.BIT.STR2 = 1U;
	CMT.CMSTR1.BIT.STR3 = 1U;
}

RX63N_CAN::RX63N_CAN()
{
	port = &PORT3;
	CANx = &CAN0;
	MSTP(CAN0) = 0;
	transmission_config();
	pin_config();

	CAN_MODE_HALT();
	default_mailbox_config();
	CAN_MODE_TEST(0x3, true);  /*Test Mode*/
	CAN_MODE_OPERATION();
};

/***********************************************************************************************************************
* Function Name: R_RSPI1_Create
* Description  : This function initializes the RSPI1 module.
* Arguments    : None
* Return Value : None
***********************************************************************************************************************/
void R_RSPI1_Create(void)
{
    /* Disable RSPI interrupts */
    VIC.IEC2.LONG = 0x00200000UL; /* Disable SPTI1 interrupt */
    VIC.IEC2.LONG = 0x00400000UL; /* Disable SPEI1 interrupt */
    VIC.IEC2.LONG = 0x00800000UL; /* Disable SPII1 interrupt */

    /* Set interrupt detection type */
    VIC.PLS2.LONG |= 0x00200000UL; /* Set SPTI1 edge detection interrupt */

    /* Cancel RSPI module stop state */
    MSTP(RSPI1) = 0U;

    /* Disable RSPI function */
    RSPI1.SPCR.BIT.SPE = 0U;

    /* Set control registers */
    RSPI1.SPPCR.BYTE = _RSPI_MOSI_LEVEL_HIGH | _RSPI_MOSI_FIXING_MOIFV_BIT | _RSPI_OUTPUT_PIN_CMOS | _RSPI_LOOPBACK_DISABLED | _RSPI_LOOPBACK2_DISABLED;
    RSPI1.SPBR = _RSPI1_DIVISOR;
    RSPI1.SPDCR.BYTE = _RSPI_ACCESS_LONGWORD | _RSPI_FRAMES_1;
    RSPI1.SPSCR.BYTE = _RSPI_SEQUENCE_LENGTH_1;
    RSPI1.SSLP.BYTE = _RSPI_SSL0_POLARITY_LOW | _RSPI_SSL1_POLARITY_LOW;
    RSPI1.SPCKD.BYTE = _RSPI_RSPCK_DELAY_1;
    RSPI1.SSLND.BYTE = _RSPI_SSL_NEGATION_DELAY_1;
    RSPI1.SPND.BYTE = _RSPI_NEXT_ACCESS_DELAY_1;
    RSPI1.SPCR2.BYTE = _RSPI_PARITY_DISABLE;
    RSPI1.SPCMD0.WORD = _RSPI_RSPCK_SAMPLING_EVEN | _RSPI_RSPCK_POLARITY_HIGH | _RSPI_BASE_BITRATE_1 | 
                        _RSPI_SIGNAL_ASSERT_SSL0 | _RSPI_SSL_KEEP_DISABLE | _RSPI_DATA_LENGTH_BITS_8 | 
                        _RSPI_MSB_FIRST | _RSPI_NEXT_ACCESS_DELAY_DISABLE | _RSPI_NEGATION_DELAY_DISABLE | 
                        _RSPI_RSPCK_DELAY_DISABLE;

    /* Set SPTI1 priority level */
    VIC.PRL85.LONG = _RSPI_PRIORITY_LEVEL6;
    
    /* Set SPEI1 priority level */
    VIC.PRL86.LONG = _RSPI_PRIORITY_LEVEL5;
    
    /* Set SPII1 priority level */
    VIC.PRL87.LONG = _RSPI_PRIORITY_LEVEL7;
    
    /* Set SPTI1 interrupt address */
    VIC.VAD85.LONG = (uint32_t)r_rspi1_transmit_interrupt;
    
    /* Set SPEI1 interrupt address */
    VIC.VAD86.LONG = (uint32_t)r_rspi1_error_interrupt;
    
    /* Set SPII1 interrupt address */
    VIC.VAD87.LONG = (uint32_t)r_rspi1_idle_interrupt;
    
    RSPI1.SPCR.BYTE = _RSPI_MODE_SPI | _RSPI_TRANSMIT_ONLY | _RSPI_MASTER_MODE;
}

static void prvSetupTimerInterrupt( void )
{
	/* Unlock. */
	SYSTEM.PRCR.WORD = portUNLOCK_KEY;

	/* Enable CMT0. */
	MSTP( CMT0 ) = 0;

	/* Lock again. */
	SYSTEM.PRCR.WORD = portLOCK_KEY;

	/* Interrupt on compare match. */
	CMT0.CMCR.BIT.CMIE = 1;

	/* Set the compare match value. */
	CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;

	/* Divide the PCLK. */
	#if portCLOCK_DIVISOR == 512
	{
		CMT0.CMCR.BIT.CKS = 3;
	}
	#elif portCLOCK_DIVISOR == 128
	{
		CMT0.CMCR.BIT.CKS = 2;
	}
	#elif portCLOCK_DIVISOR == 32
	{
		CMT0.CMCR.BIT.CKS = 1;
	}
	#elif portCLOCK_DIVISOR == 8
	{
		CMT0.CMCR.BIT.CKS = 0;
	}
	#else
	{
		#error Invalid portCLOCK_DIVISOR setting
	}
	#endif


	/* Enable the interrupt... */
	_IEN( _CMT0_CMI0 ) = 1;

	/* ...and set its priority to the application defined kernel priority. */
	_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;

	/* Start the timer. */
	CMT.CMSTR0.BIT.STR0 = 1;
}

/***********************************************************************************************************************
* Function Name: R_CMT0_Create
* Description  : This function initializes the CMT0 channel.
* Arguments    : None
* Return Value : None
***********************************************************************************************************************/
void R_CMT0_Create(void)
{
    /* Disable CMI interrupt */
    IEN(CMT0, CMI0) = 0U;

    /* Cancel CMT stop state in LPC */
    MSTP(CMT0) = 0U;

    /* Set control registers */
    CMT0.CMCR.WORD = _0002_CMT_CMCR_CKS_PCLK128 | _0040_CMT_CMCR_CMIE_ENABLE;
    CMT0.CMCOR = _B71B_CMT0_CMCOR_VALUE;

    /* Set CMI0 priority level */
    IPR(CMT0,CMI0) = _08_CMT_PRIORITY_LEVEL8;
}