本文整理汇总了C++中MIPI_OUTP函数的典型用法代码示例。如果您正苦于以下问题：C++ MIPI_OUTP函数的具体用法？C++ MIPI_OUTP怎么用？C++ MIPI_OUTP使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了MIPI_OUTP函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: mdss_dsi_isr
irqreturn_t mdss_dsi_isr(int irq, void *ptr)
{
u32 isr;
u32 isr0 = 0;
struct mdss_dsi_ctrl_pdata *ctrl =
(struct mdss_dsi_ctrl_pdata *)ptr;
if (!ctrl) {
pr_err("%s unable to access ctrl\n", __func__);
return IRQ_HANDLED;
}
if (!ctrl->ctrl_base) {
pr_err("%s:%d DSI base adr no Initialized",
__func__, __LINE__);
return IRQ_HANDLED;
}
isr = MIPI_INP(ctrl->ctrl_base + 0x0110);/* DSI_INTR_CTRL */
MIPI_OUTP(ctrl->ctrl_base + 0x0110, isr);
if (ctrl->shared_pdata.broadcast_enable)
if ((ctrl->panel_data.panel_info.pdest == DISPLAY_2)
&& (left_ctrl_pdata != NULL)) {
isr0 = MIPI_INP(left_ctrl_pdata->ctrl_base
+ 0x0110);/* DSI_INTR_CTRL */
MIPI_OUTP(left_ctrl_pdata->ctrl_base + 0x0110, isr0 & (~DSI_INTR_CMD_MDP_DONE));
}
pr_debug("%s: isr=%x, isr0=%x", __func__, isr, isr0);
if (isr & DSI_INTR_ERROR) {
#if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
xlog(__func__, ctrl->ndx, ctrl->mdp_busy, isr, 0, 0, 0x97);
#endif
pr_err("%s: isr[%d]=%x %x", __func__, ctrl->ndx, isr, (int)DSI_INTR_ERROR);
mdss_dsi_error(ctrl);
}
if (isr & DSI_INTR_VIDEO_DONE) {
spin_lock(&ctrl->mdp_lock);
mdss_dsi_disable_irq_nosync(ctrl, DSI_VIDEO_TERM);
complete(&ctrl->video_comp);
spin_unlock(&ctrl->mdp_lock);
}
if (isr & DSI_INTR_CMD_DMA_DONE) {
spin_lock(&ctrl->mdp_lock);
#if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
xlog(__func__,ctrl->ndx, ctrl->mdp_busy, isr, 0, 0, 0x98);
#endif
mdss_dsi_disable_irq_nosync(ctrl, DSI_CMD_TERM);
complete(&ctrl->dma_comp);
spin_unlock(&ctrl->mdp_lock);
}
if (isr & DSI_INTR_CMD_MDP_DONE) {
spin_lock(&ctrl->mdp_lock);
#if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
xlog(__func__, ctrl->ndx, ctrl->mdp_busy, isr, 0, 0, 0x99);
#endif
ctrl->mdp_busy = false;
mdss_dsi_disable_irq_nosync(ctrl, DSI_MDP_TERM);
complete(&ctrl->mdp_comp);
spin_unlock(&ctrl->mdp_lock);
}
if (isr & DSI_INTR_BTA_DONE) {
spin_lock(&ctrl->mdp_lock);
mdss_dsi_disable_irq_nosync(ctrl, DSI_BTA_TERM);
complete(&ctrl->bta_comp);
spin_unlock(&ctrl->mdp_lock);
}
return IRQ_HANDLED;
}示例2: mdss_dsi_dfps_config
static int mdss_dsi_dfps_config(struct mdss_panel_data *pdata, int new_fps)
{
int rc = 0;
struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
u32 dsi_ctrl;
pr_debug("%s+:\n", __func__);
if (pdata == NULL) {
pr_err("%s: Invalid input data\n", __func__);
return -EINVAL;
}
ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
panel_data);
if (!ctrl_pdata->panel_data.panel_info.dynamic_fps) {
pr_err("%s: Dynamic fps not enabled for this panel\n",
__func__);
return -EINVAL;
}
if (new_fps !=
ctrl_pdata->panel_data.panel_info.mipi.frame_rate) {
if (pdata->panel_info.dfps_update
== DFPS_IMMEDIATE_PORCH_UPDATE_MODE) {
u32 hsync_period, vsync_period;
u32 new_dsi_v_total, current_dsi_v_total;
vsync_period =
mdss_panel_get_vtotal(&pdata->panel_info);
hsync_period =
mdss_panel_get_htotal(&pdata->panel_info);
current_dsi_v_total =
MIPI_INP((ctrl_pdata->ctrl_base) + 0x2C);
new_dsi_v_total =
((vsync_period - 1) << 16) | (hsync_period - 1);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x2C,
(current_dsi_v_total | 0x8000000));
if (new_dsi_v_total & 0x8000000) {
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x2C,
new_dsi_v_total);
} else {
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x2C,
(new_dsi_v_total | 0x8000000));
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x2C,
(new_dsi_v_total & 0x7ffffff));
}
pdata->panel_info.mipi.frame_rate = new_fps;
} else {
rc = mdss_dsi_clk_div_config
(&ctrl_pdata->panel_data.panel_info, new_fps);
if (rc) {
pr_err("%s: unable to initialize the clk dividers\n",
__func__);
return rc;
}
ctrl_pdata->pclk_rate =
pdata->panel_info.mipi.dsi_pclk_rate;
ctrl_pdata->byte_clk_rate =
pdata->panel_info.clk_rate / 8;
if (pdata->panel_info.dfps_update
== DFPS_IMMEDIATE_CLK_UPDATE_MODE) {
dsi_ctrl = MIPI_INP((ctrl_pdata->ctrl_base) +
0x0004);
pdata->panel_info.mipi.frame_rate = new_fps;
dsi_ctrl &= ~0x2;
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x0004,
dsi_ctrl);
mdss_dsi_controller_cfg(true, pdata);
mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 0);
mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 1);
dsi_ctrl |= 0x2;
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x0004,
dsi_ctrl);
}
}
} else {
pr_debug("%s: Panel is already at this FPS\n", __func__);
}
return rc;
}示例3: mdss_dsi_ulps_config_sub
static int mdss_dsi_ulps_config_sub(struct mdss_dsi_ctrl_pdata *ctrl_pdata,
int enable)
{
int ret = 0;
struct mdss_panel_data *pdata = NULL;
struct mipi_panel_info *pinfo = NULL;
u32 lane_status = 0;
u32 active_lanes = 0;
if (!ctrl_pdata) {
pr_err("%s: invalid input\n", __func__);
return -EINVAL;
}
pdata = &ctrl_pdata->panel_data;
if (!pdata) {
pr_err("%s: Invalid panel data\n", __func__);
return -EINVAL;
}
pinfo = &pdata->panel_info.mipi;
if (!__mdss_dsi_ulps_feature_enabled(pdata)) {
pr_debug("%s: ULPS feature not supported. enable=%d\n",
__func__, enable);
return -ENOTSUPP;
}
if (enable && !ctrl_pdata->ulps) {
/* No need to configure ULPS mode when entering suspend state */
if (!pdata->panel_info.panel_power_on) {
pr_err("%s: panel off. returning\n", __func__);
goto error;
}
if (__mdss_dsi_clk_enabled(ctrl_pdata, DSI_LINK_CLKS)) {
pr_err("%s: cannot enter ulps mode if dsi clocks are on\n",
__func__);
ret = -EPERM;
goto error;
}
ret = mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 1);
if (ret) {
pr_err("%s: Failed to enable clocks. rc=%d\n",
__func__, ret);
goto error;
}
/*
* ULPS Entry Request.
* Wait for a short duration to ensure that the lanes
* enter ULP state.
*/
MIPI_OUTP(ctrl_pdata->ctrl_base + 0x0AC, 0x01F);
usleep(100);
/* Check to make sure that all active data lanes are in ULPS */
if (pinfo->data_lane3)
active_lanes |= BIT(11);
if (pinfo->data_lane2)
active_lanes |= BIT(10);
if (pinfo->data_lane1)
active_lanes |= BIT(9);
if (pinfo->data_lane0)
active_lanes |= BIT(8);
active_lanes |= BIT(12); /* clock lane */
lane_status = MIPI_INP(ctrl_pdata->ctrl_base + 0xA8);
if (lane_status & active_lanes) {
pr_err("%s: ULPS entry req failed. Lane status=0x%08x\n",
__func__, lane_status);
ret = -EINVAL;
mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 0);
goto error;
}
/* Enable MMSS DSI Clamps */
MIPI_OUTP(ctrl_pdata->mmss_misc_io.base + 0x14, 0x3FF);
MIPI_OUTP(ctrl_pdata->mmss_misc_io.base + 0x14, 0x83FF);
wmb();
MIPI_OUTP(ctrl_pdata->mmss_misc_io.base + 0x108, 0x1);
/* disable DSI controller */
mdss_dsi_controller_cfg(0, pdata);
mdss_dsi_clk_ctrl(ctrl_pdata, DSI_ALL_CLKS, 0);
ctrl_pdata->ulps = true;
} else if (ctrl_pdata->ulps) {
ret = mdss_dsi_clk_ctrl(ctrl_pdata, DSI_BUS_CLKS, 1);
if (ret) {
pr_err("%s: Failed to enable bus clocks. rc=%d\n",
__func__, ret);
goto error;
}
MIPI_OUTP(ctrl_pdata->mmss_misc_io.base + 0x108, 0x0);
mdss_dsi_phy_init(pdata);
__mdss_dsi_ctrl_setup(pdata);
mdss_dsi_sw_reset(pdata);
//.........这里部分代码省略.........
示例4: mdss_dsi_op_mode_config
void mdss_dsi_op_mode_config(int mode,
struct mdss_panel_data *pdata)
{
u32 dsi_ctrl, intr_ctrl;
struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
struct mdss_dsi_ctrl_pdata *mctrl = NULL;
if (pdata == NULL) {
pr_err("%s: Invalid input data\n", __func__);
return;
}
ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
panel_data);
/*
* In broadcast mode, the configuration for master controller
* would be done when the slave controller is configured
*/
if (mdss_dsi_is_master_ctrl(ctrl_pdata)) {
pr_debug("%s: Broadcast mode enabled. skipping config for ctrl%d\n",
__func__, ctrl_pdata->ndx);
return;
}
dsi_ctrl = MIPI_INP((ctrl_pdata->ctrl_base) + 0x0004);
/*If Video enabled, Keep Video and Cmd mode ON */
if (dsi_ctrl & 0x02)
dsi_ctrl &= ~0x05;
else
dsi_ctrl &= ~0x07;
if (mode == DSI_VIDEO_MODE) {
dsi_ctrl |= 0x03;
intr_ctrl = DSI_INTR_CMD_DMA_DONE_MASK | DSI_INTR_BTA_DONE_MASK;
} else { /* command mode */
dsi_ctrl |= 0x05;
if (pdata->panel_info.type == MIPI_VIDEO_PANEL)
dsi_ctrl |= 0x02;
intr_ctrl = DSI_INTR_CMD_DMA_DONE_MASK | DSI_INTR_ERROR_MASK |
DSI_INTR_CMD_MDP_DONE_MASK | DSI_INTR_BTA_DONE_MASK;
}
/* Ensure that for slave controller, master is also configured */
if (mdss_dsi_is_slave_ctrl(ctrl_pdata)) {
mctrl = mdss_dsi_get_master_ctrl();
if (mctrl) {
pr_debug("%s: configuring ctrl%d\n", __func__,
mctrl->ndx);
MIPI_OUTP(mctrl->ctrl_base + 0x0110, intr_ctrl);
MIPI_OUTP(mctrl->ctrl_base + 0x0004, dsi_ctrl);
} else {
pr_warn("%s: Unable to get master control\n",
__func__);
}
}
pr_debug("%s: configuring ctrl%d\n", __func__, ctrl_pdata->ndx);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x0110, intr_ctrl);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x0004, dsi_ctrl);
wmb();
}示例5: mipi_dsi_configure_serdes
static void mipi_dsi_configure_serdes(void)
{
void __iomem *cc;
/* PHY registers programemd thru S2P interface */
if (periph_base) {
MIPI_OUTP(periph_base + 0x2c, 0x000000b6);
MIPI_OUTP(periph_base + 0x2c, 0x000001b5);
MIPI_OUTP(periph_base + 0x2c, 0x000001b4);
MIPI_OUTP(periph_base + 0x2c, 0x000003b3);
MIPI_OUTP(periph_base + 0x2c, 0x000003a2);
MIPI_OUTP(periph_base + 0x2c, 0x000002a1);
MIPI_OUTP(periph_base + 0x2c, 0x000008a0);
MIPI_OUTP(periph_base + 0x2c, 0x00000d9f);
MIPI_OUTP(periph_base + 0x2c, 0x0000109e);
MIPI_OUTP(periph_base + 0x2c, 0x0000209d);
MIPI_OUTP(periph_base + 0x2c, 0x0000109c);
MIPI_OUTP(periph_base + 0x2c, 0x0000079a);
MIPI_OUTP(periph_base + 0x2c, 0x00000c99);
MIPI_OUTP(periph_base + 0x2c, 0x00002298);
MIPI_OUTP(periph_base + 0x2c, 0x000000a7);
MIPI_OUTP(periph_base + 0x2c, 0x000000a6);
MIPI_OUTP(periph_base + 0x2c, 0x000000a5);
MIPI_OUTP(periph_base + 0x2c, 0x00007fa4);
MIPI_OUTP(periph_base + 0x2c, 0x0000eea8);
MIPI_OUTP(periph_base + 0x2c, 0x000006aa);
MIPI_OUTP(periph_base + 0x2c, 0x00002095);
MIPI_OUTP(periph_base + 0x2c, 0x00000493);
MIPI_OUTP(periph_base + 0x2c, 0x00001092);
MIPI_OUTP(periph_base + 0x2c, 0x00000691);
MIPI_OUTP(periph_base + 0x2c, 0x00005490);
MIPI_OUTP(periph_base + 0x2c, 0x0000038d);
MIPI_OUTP(periph_base + 0x2c, 0x0000148c);
MIPI_OUTP(periph_base + 0x2c, 0x0000058b);
MIPI_OUTP(periph_base + 0x2c, 0x0000078a);
MIPI_OUTP(periph_base + 0x2c, 0x00001f89);
MIPI_OUTP(periph_base + 0x2c, 0x00003388);
MIPI_OUTP(periph_base + 0x2c, 0x00006387);
MIPI_OUTP(periph_base + 0x2c, 0x00004886);
MIPI_OUTP(periph_base + 0x2c, 0x00005085);
MIPI_OUTP(periph_base + 0x2c, 0x00000084);
MIPI_OUTP(periph_base + 0x2c, 0x0000da83);
MIPI_OUTP(periph_base + 0x2c, 0x0000b182);
MIPI_OUTP(periph_base + 0x2c, 0x00002f81);
MIPI_OUTP(periph_base + 0x2c, 0x00004080);
MIPI_OUTP(periph_base + 0x2c, 0x00004180);
MIPI_OUTP(periph_base + 0x2c, 0x000006aa);
}
cc = MIPI_DSI_BASE + 0x0130;
MIPI_OUTP(cc, 0x806c11c8);
MIPI_OUTP(cc, 0x804c11c8);
MIPI_OUTP(cc, 0x806d0080);
MIPI_OUTP(cc, 0x804d0080);
MIPI_OUTP(cc, 0x00000000);
MIPI_OUTP(cc, 0x807b1597);
MIPI_OUTP(cc, 0x805b1597);
MIPI_OUTP(cc, 0x807c0080);
MIPI_OUTP(cc, 0x805c0080);
MIPI_OUTP(cc, 0x00000000);
MIPI_OUTP(cc, 0x807911c8);
MIPI_OUTP(cc, 0x805911c8);
MIPI_OUTP(cc, 0x807a0080);
MIPI_OUTP(cc, 0x805a0080);
MIPI_OUTP(cc, 0x00000000);
MIPI_OUTP(cc, 0x80721555);
MIPI_OUTP(cc, 0x80521555);
MIPI_OUTP(cc, 0x80730000);
MIPI_OUTP(cc, 0x80530000);
MIPI_OUTP(cc, 0x00000000);
}示例6: mdss_dsi_cmds_rx
int mdss_dsi_cmds_rx(struct mdss_dsi_ctrl_pdata *ctrl,
struct dsi_cmd_desc *cmds, int rlen)
{
int cnt, len, diff, pkt_size, ret = 0;
struct dsi_buf *tp, *rp;
int no_max_pkt_size;
char cmd;
u32 dsi_ctrl, data;
int video_mode;
u32 left_dsi_ctrl = 0;
bool left_ctrl_restore = false;
int rx_flags = 0;
bool long_rd_rsp_chk = false;
if (ctrl->shared_pdata.broadcast_enable) {
if (ctrl->ndx == DSI_CTRL_0) {
pr_debug("%s: Broadcast mode. 1st ctrl\n",
__func__);
return 0;
}
}
if (ctrl->shared_pdata.broadcast_enable) {
if ((ctrl->ndx == DSI_CTRL_1)
&& (left_ctrl_pdata != NULL)) {
left_dsi_ctrl = MIPI_INP(left_ctrl_pdata->ctrl_base
+ 0x0004);
video_mode = left_dsi_ctrl & 0x02; /* VIDEO_MODE_EN */
if (video_mode) {
data = left_dsi_ctrl | 0x04; /* CMD_MODE_EN */
MIPI_OUTP(left_ctrl_pdata->ctrl_base + 0x0004,
data);
left_ctrl_restore = true;
}
}
}
/* turn on cmd mode
* for video mode, do not send cmds more than
* one pixel line, since it only transmit it
* during BLLP.
*/
dsi_ctrl = MIPI_INP((ctrl->ctrl_base) + 0x0004);
video_mode = dsi_ctrl & 0x02; /* VIDEO_MODE_EN */
if (video_mode) {
data = dsi_ctrl | 0x04; /* CMD_MODE_EN */
MIPI_OUTP((ctrl->ctrl_base) + 0x0004, data);
}
no_max_pkt_size = rx_flags & CMD_REQ_NO_MAX_PKT_SIZE;
if (no_max_pkt_size)
rlen = ALIGN(rlen, 4); /* Only support rlen = 4*n */
len = rlen;
diff = 0;
if (len < 2)
cnt = 4; /* short read */
else if (len == 2) {
/* Response could be a short or long read */
cnt = 8;
long_rd_rsp_chk = true;
} else {
if (len > MDSS_DSI_LEN)
len = MDSS_DSI_LEN; /* 8 bytes at most */
len = ALIGN(len, 4); /* len 4 bytes align */
diff = len - rlen;
/*
* add extra 2 bytes to len to have overall
* packet size is multipe by 4. This also make
* sure 4 bytes dcs headerlocates within a
* 32 bits register after shift in.
* after all, len should be either 6 or 10.
*/
len += 2;
cnt = len + 6; /* 4 bytes header + 2 bytes crc */
}
tp = &ctrl->tx_buf;
rp = &ctrl->rx_buf;
if (!no_max_pkt_size) {
/* packet size need to be set at every read */
pkt_size = len;
max_pktsize[0] = pkt_size;
mdss_dsi_buf_init(tp);
ret = mdss_dsi_cmd_dma_add(tp, &pkt_size_cmd);
if (!ret) {
pr_err("%s: failed to call\n",
__func__);
rp->len = 0;
goto end;
}
mdss_dsi_wait4video_eng_busy(ctrl);
mdss_dsi_enable_irq(ctrl, DSI_CMD_TERM);
ret = mdss_dsi_cmd_dma_tx(ctrl, tp);
if (IS_ERR_VALUE(ret)) {
//.........这里部分代码省略.........
示例7: mdss_dsi_isr
irqreturn_t mdss_dsi_isr(int irq, void *ptr)
{
u32 isr;
struct mdss_dsi_ctrl_pdata *ctrl =
(struct mdss_dsi_ctrl_pdata *)ptr;
struct mdss_dsi_ctrl_pdata *mctrl = NULL;
if (!ctrl->ctrl_base) {
pr_err("%s:%d DSI base adr no Initialized",
__func__, __LINE__);
return IRQ_HANDLED;
}
isr = MIPI_INP(ctrl->ctrl_base + 0x0110);/* DSI_INTR_CTRL */
MIPI_OUTP(ctrl->ctrl_base + 0x0110, isr);
if (mdss_dsi_is_slave_ctrl(ctrl)) {
mctrl = mdss_dsi_get_master_ctrl();
if (mctrl) {
u32 isr0;
isr0 = MIPI_INP(mctrl->ctrl_base + 0x0110);
if (isr0 & DSI_INTR_CMD_DMA_DONE)
MIPI_OUTP(mctrl->ctrl_base + 0x0110,
DSI_INTR_CMD_DMA_DONE);
} else {
pr_warn("%s: Unable to get master control\n",
__func__);
}
}
pr_debug("%s: ndx=%d isr=%x\n", __func__, ctrl->ndx, isr);
if (isr & DSI_INTR_ERROR) {
MDSS_XLOG(ctrl->ndx, ctrl->mdp_busy, isr, 0x97);
pr_err("%s: ndx=%d isr=%x\n", __func__, ctrl->ndx, isr);
mdss_dsi_error(ctrl);
}
if (isr & DSI_INTR_VIDEO_DONE) {
spin_lock(&ctrl->mdp_lock);
mdss_dsi_disable_irq_nosync(ctrl, DSI_VIDEO_TERM);
complete(&ctrl->video_comp);
spin_unlock(&ctrl->mdp_lock);
}
if (isr & DSI_INTR_CMD_DMA_DONE) {
MDSS_XLOG(ctrl->ndx, ctrl->mdp_busy, isr, 0x98);
spin_lock(&ctrl->mdp_lock);
mdss_dsi_disable_irq_nosync(ctrl, DSI_CMD_TERM);
complete(&ctrl->dma_comp);
spin_unlock(&ctrl->mdp_lock);
}
if (isr & DSI_INTR_CMD_MDP_DONE) {
MDSS_XLOG(ctrl->ndx, ctrl->mdp_busy, isr, 0x99);
spin_lock(&ctrl->mdp_lock);
ctrl->mdp_busy = false;
mdss_dsi_disable_irq_nosync(ctrl, DSI_MDP_TERM);
complete(&ctrl->mdp_comp);
spin_unlock(&ctrl->mdp_lock);
}
if (isr & DSI_INTR_BTA_DONE) {
spin_lock(&ctrl->mdp_lock);
mdss_dsi_disable_irq_nosync(ctrl, DSI_BTA_TERM);
complete(&ctrl->bta_comp);
spin_unlock(&ctrl->mdp_lock);
}
return IRQ_HANDLED;
}示例8: mipi_dsi_off
static int mipi_dsi_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
struct msm_panel_info *pinfo;
uint32 dsi_ctrl;
#ifdef CONFIG_FB_MSM_LCD_NOTIFY
lcd_notifier_call_chain(LCD_EVENT_OFF_START, NULL);
#endif
pr_debug("%s+:\n", __func__);
mfd = platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (mdp_rev >= MDP_REV_41)
mutex_lock(&mfd->dma->ov_mutex);
else
down(&mfd->dma->mutex);
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
mipi_dsi_clk_enable();
/* make sure dsi_cmd_mdp is idle */
mipi_dsi_cmd_mdp_busy();
}
/*
* Desctiption: change to DSI_CMD_MODE since it needed to
* tx DCS dsiplay off comamnd to panel
* mipi_dsi_op_mode_config(DSI_CMD_MODE);
*/
if (mfd->panel_info.type == MIPI_CMD_PANEL) {
if (pinfo->lcd.vsync_enable) {
if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) {
if (MDP_REV_303 != mdp_rev)
gpio_free(vsync_gpio);
}
mipi_dsi_set_tear_off(mfd);
}
}
ret = panel_next_off(pdev);
spin_lock_bh(&dsi_clk_lock);
mipi_dsi_clk_disable();
/* disbale dsi engine */
dsi_ctrl = MIPI_INP(MIPI_DSI_BASE + 0x0000);
dsi_ctrl &= ~0x01;
MIPI_OUTP(MIPI_DSI_BASE + 0x0000, dsi_ctrl);
MIPI_OUTP(MIPI_DSI_BASE + 0x010c, 0); /* DSI_INTL_CTRL */
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
mipi_dsi_phy_ctrl(0);
mipi_dsi_ahb_ctrl(0);
spin_unlock_bh(&dsi_clk_lock);
mipi_dsi_unprepare_clocks();
usleep(5000);
#if defined (CONFIG_MIPI_DSI_RESET_LP11)
if (mipi_dsi_pdata && mipi_dsi_pdata->active_reset)
mipi_dsi_pdata->active_reset(0); /* low */
#endif
usleep(2000); /*1ms delay(minimum) required between reset low and AVDD off*/
#if defined(CONFIG_SUPPORT_SECOND_POWER)
if (mipi_dsi_pdata && mipi_dsi_pdata->panel_power_save)
mipi_dsi_pdata->panel_power_save(0);
#endif
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(0);
if (mdp_rev >= MDP_REV_41)
mutex_unlock(&mfd->dma->ov_mutex);
else
up(&mfd->dma->mutex);
#ifdef CONFIG_FB_MSM_LCD_NOTIFY
lcd_notifier_call_chain(LCD_EVENT_OFF_END, NULL);
#endif
pr_debug("%s-:\n", __func__);
return ret;
}示例9: mdss_dsi_ulps_config
int mdss_dsi_ulps_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata, int enable)
{
int ret = 0;
struct mdss_panel_data *pdata = NULL;
struct mdss_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 lane_status = 0, regval;
u32 active_lanes = 0, clamp_reg;
if (!ctrl_pdata) {
pr_err("%s: invalid input\n", __func__);
return -EINVAL;
}
if (&ctrl_pdata->mmss_misc_io == NULL) {
pr_err("%s: mmss_misc_io is NULL. ULPS not valid\n", __func__);
return -EINVAL;
}
pdata = &ctrl_pdata->panel_data;
if (!pdata) {
pr_err("%s: Invalid panel data\n", __func__);
return -EINVAL;
}
pinfo = &pdata->panel_info;
mipi = &pinfo->mipi;
if (!mdss_dsi_ulps_feature_enabled(pdata)) {
pr_debug("%s: ULPS feature not supported. enable=%d\n",
__func__, enable);
return -ENOTSUPP;
}
if (pinfo->cont_splash_enabled) {
pr_debug("%s: skip ULPS config with splash screen enabled\n",
__func__);
return 0;
}
active_lanes = BIT(4);
clamp_reg = BIT(8) | BIT(9);
if (mipi->data_lane0) {
active_lanes |= BIT(0);
clamp_reg |= (BIT(0) | BIT(1));
}
if (mipi->data_lane1) {
active_lanes |= BIT(1);
clamp_reg |= (BIT(2) | BIT(3));
}
if (mipi->data_lane2) {
active_lanes |= BIT(2);
clamp_reg |= (BIT(4) | BIT(5));
}
if (mipi->data_lane3) {
active_lanes |= BIT(3);
clamp_reg |= (BIT(6) | BIT(7));
}
pr_debug("%s: configuring ulps (%s) for ctrl%d, active lanes=0x%08x\n",
__func__, (enable ? "on" : "off"), ctrl_pdata->ndx,
active_lanes);
if (enable && !ctrl_pdata->ulps) {
MIPI_OUTP(ctrl_pdata->ctrl_base + 0x0AC, active_lanes);
usleep(100);
lane_status = MIPI_INP(ctrl_pdata->ctrl_base + 0xA8);
if (lane_status & (active_lanes << 8)) {
pr_err("%s: ULPS entry req failed for ctrl%d. Lane status=0x%08x\n",
__func__, ctrl_pdata->ndx, lane_status);
ret = -EINVAL;
goto error;
}
if (ctrl_pdata->ndx == DSI_CTRL_0) {
regval = MIPI_INP(ctrl_pdata->mmss_misc_io.base + 0x14);
MIPI_OUTP(ctrl_pdata->mmss_misc_io.base + 0x14,
regval | clamp_reg);
MIPI_OUTP(ctrl_pdata->mmss_misc_io.base + 0x14,
regval | (clamp_reg | BIT(15)));
} else if (ctrl_pdata->ndx == DSI_CTRL_1) {
regval = MIPI_INP(ctrl_pdata->mmss_misc_io.base + 0x14);
MIPI_OUTP(ctrl_pdata->mmss_misc_io.base + 0x14,
regval | (clamp_reg << 16));
MIPI_OUTP(ctrl_pdata->mmss_misc_io.base + 0x14,
regval | ((clamp_reg << 16) | BIT(31)));
}
wmb();
MIPI_OUTP(ctrl_pdata->mmss_misc_io.base + 0x108, 0x1);
ctrl_pdata->ulps = true;
} else if (ctrl_pdata->ulps) {
MIPI_OUTP(ctrl_pdata->mmss_misc_io.base + 0x108, 0x0);
mdss_dsi_phy_init(pdata);
__mdss_dsi_ctrl_setup(pdata);
//.........这里部分代码省略.........
示例10: mdss_dsi_cmds_tx
/*
* mdss_dsi_cmds_tx:
* thread context only
*/
int mdss_dsi_cmds_tx(struct mdss_dsi_ctrl_pdata *ctrl,
struct dsi_cmd_desc *cmds, int cnt)
{
u32 dsi_ctrl, data;
int video_mode, ret = 0;
u32 left_dsi_ctrl = 0;
bool left_ctrl_restore = false;
pr_debug("%s : ++ ctrl->ndx (%d) cmd cnt (%d)\n",__func__,ctrl->ndx,cnt);
if (ctrl->shared_pdata.broadcast_enable) {
if (ctrl->ndx == DSI_CTRL_0) {
pr_debug("%s: Broadcast mode. 1st ctrl\n",
__func__);
return 0;
}
}
if (ctrl->shared_pdata.broadcast_enable) {
if ((ctrl->ndx == DSI_CTRL_1)
&& (left_ctrl_pdata != NULL)) {
left_dsi_ctrl = MIPI_INP(left_ctrl_pdata->ctrl_base
+ 0x0004);
video_mode =
left_dsi_ctrl & 0x02; /* VIDEO_MODE_EN */
if (video_mode) {
data = left_dsi_ctrl | 0x04; /* CMD_MODE_EN */
MIPI_OUTP(left_ctrl_pdata->ctrl_base + 0x0004,
data);
left_ctrl_restore = true;
}
} else {
pr_err("%s no left_ctrl_pdata...\n",__func__);
}
}
/* turn on cmd mode
* for video mode, do not send cmds more than
* one pixel line, since it only transmit it
* during BLLP.
*/
dsi_ctrl = MIPI_INP((ctrl->ctrl_base) + 0x0004);
video_mode = dsi_ctrl & 0x02; /* VIDEO_MODE_EN */
if (video_mode) {
data = dsi_ctrl | 0x04; /* CMD_MODE_EN */
MIPI_OUTP((ctrl->ctrl_base) + 0x0004, data);
}
ret = mdss_dsi_cmds2buf_tx(ctrl, cmds, cnt);
if (IS_ERR_VALUE(ret)) {
pr_err("%s: failed to call\n",
__func__);
cnt = -EINVAL;
}
if (left_ctrl_restore)
MIPI_OUTP(left_ctrl_pdata->ctrl_base + 0x0004,
left_dsi_ctrl); /*restore */
if (video_mode)
MIPI_OUTP((ctrl->ctrl_base) + 0x0004,
dsi_ctrl); /* restore */
return cnt;
}示例11: mdss_dsi_cmds_rx
/*
* mdss_dsi_cmds_rx() - dcs read from panel
* @ctrl: dsi controller
* @cmds: read command descriptor
* @len: number of bytes to read back
*
* controller have 4 registers can hold 16 bytes of rxed data
* dcs packet: 4 bytes header + payload + 2 bytes crc
* 2 padding bytes add to payload to have payload length is mutipled by 4
* 1st read: 4 bytes header + 8 bytes payload + 2 padding + 2 crc
* 2nd read: 12 bytes payload + 2 padding + 2 crc
* 3rd read: 12 bytes payload + 2 padding + 2 crc
*
*/
int mdss_dsi_cmds_rx(struct mdss_dsi_ctrl_pdata *ctrl,
struct dsi_cmd_desc *cmds, int rlen)
{
int data_byte, rx_byte, dlen, end;
int short_response, diff, pkt_size, ret = 0;
struct dsi_buf *tp, *rp;
char cmd;
u32 dsi_ctrl, data;
int video_mode;
u32 left_dsi_ctrl = 0;
bool left_ctrl_restore = false;
if (ctrl->shared_pdata.broadcast_enable) {
if (ctrl->ndx == DSI_CTRL_0) {
pr_debug("%s: Broadcast mode. 1st ctrl\n",
__func__);
return 0;
}
}
if (ctrl->shared_pdata.broadcast_enable) {
if ((ctrl->ndx == DSI_CTRL_1)
&& (left_ctrl_pdata != NULL)) {
left_dsi_ctrl = MIPI_INP(left_ctrl_pdata->ctrl_base
+ 0x0004);
video_mode = left_dsi_ctrl & 0x02; /* VIDEO_MODE_EN */
if (video_mode) {
data = left_dsi_ctrl | 0x04; /* CMD_MODE_EN */
MIPI_OUTP(left_ctrl_pdata->ctrl_base + 0x0004,
data);
left_ctrl_restore = true;
}
}
}
/* turn on cmd mode
* for video mode, do not send cmds more than
* one pixel line, since it only transmit it
* during BLLP.
*/
dsi_ctrl = MIPI_INP((ctrl->ctrl_base) + 0x0004);
video_mode = dsi_ctrl & 0x02; /* VIDEO_MODE_EN */
if (video_mode) {
data = dsi_ctrl | 0x04; /* CMD_MODE_EN */
MIPI_OUTP((ctrl->ctrl_base) + 0x0004, data);
}
if (rlen == 0) {
short_response = 1;
rx_byte = 4;
} else {
short_response = 0;
data_byte = 8; /* first read */
/*
* add extra 2 padding bytes to have overall
* packet size is multipe by 4. This also make
* sure 4 bytes dcs headerlocates within a
* 32 bits register after shift in.
*/
pkt_size = data_byte + 2;
rx_byte = data_byte + 8; /* 4 header + 2 crc + 2 padding*/
}
tp = &ctrl->tx_buf;
rp = &ctrl->rx_buf;
end = 0;
mdss_dsi_buf_init(rp);
while (!end) {
pr_debug("%s: rlen=%d pkt_size=%d rx_byte=%d\n",
__func__, rlen, pkt_size, rx_byte);
if (!short_response) {
max_pktsize[0] = pkt_size;
mdss_dsi_buf_init(tp);
ret = mdss_dsi_cmd_dma_add(tp, &pkt_size_cmd);
if (!ret) {
pr_err("%s: failed to add max_pkt_size\n",
__func__);
rp->len = 0;
goto end;
}
mdss_dsi_wait4video_eng_busy(ctrl);
mdss_dsi_enable_irq(ctrl, DSI_CMD_TERM);
//.........这里部分代码省略.........
示例12: mipi_dsi_on
static int mipi_dsi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data;
u32 dummy_xres, dummy_yres;
int target_type = 0;
u32 tmp;
#if defined(CONFIG_FB_MSM_MIPI_RENESAS_TFT_VIDEO_FULL_HD_PT_PANEL)
static int is_booting = 1;
#endif
#ifdef CONFIG_FB_MSM_LCD_NOTIFY
lcd_notifier_call_chain(LCD_EVENT_ON_START, NULL);
#endif
pr_debug("%s+:\n", __func__);
#if defined(CONFIG_MIPI_SAMSUNG_ESD_REFRESH) || defined(CONFIG_ESD_ERR_FG_RECOVERY)
pdev_for_esd = pdev;
#endif
#if defined (CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_QHD_PT)
if (get_lcd_attached() == 0)
return ENODEV;
#endif
mfd = platform_get_drvdata(pdev);
fbi = mfd->fbi;
var = &fbi->var;
pinfo = &mfd->panel_info;
esc_byte_ratio = pinfo->mipi.esc_byte_ratio;
if (mipi_dsi_pdata && mipi_dsi_pdata->power_common)
mipi_dsi_pdata->power_common();
#if defined(CONFIG_SUPPORT_SECOND_POWER)
#if defined(CONFIG_FB_MSM_MIPI_RENESAS_TFT_VIDEO_FULL_HD_PT_PANEL)
if( is_booting == 1 )
{
is_booting = 0;
#if defined(CONFIG_MACH_JACTIVE_ATT) || defined(CONFIG_MACH_JACTIVE_EUR)
usleep(5000);
if (mipi_dsi_pdata && mipi_dsi_pdata->active_reset)
mipi_dsi_pdata->active_reset(0); /* low */
usleep(2000);
if (mipi_dsi_pdata && mipi_dsi_pdata->panel_power_save)
mipi_dsi_pdata->panel_power_save(0);
msleep(10);
#endif
}
#endif
if (mipi_dsi_pdata && mipi_dsi_pdata->panel_power_save)
mipi_dsi_pdata->panel_power_save(1);
#endif
#if !defined(CONFIG_SEC_PRODUCT_8930) && !defined(CONFIG_SEC_PRODUCT_8960)
if (system_rev == 6)
mdelay(500);
#endif
if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save)
mipi_dsi_pdata->dsi_power_save(1);
cont_splash_clk_ctrl(0);
mipi_dsi_prepare_clocks();
mipi_dsi_ahb_ctrl(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
mipi_dsi_phy_ctrl(1);
if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata)
target_type = mipi_dsi_pdata->target_type;
mipi_dsi_phy_init(0, &(mfd->panel_info), target_type);
mipi_dsi_clk_enable();
#if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_QHD_PT_PANEL)
mipi_dsi_configure_dividers(60);
#endif
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1);
MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0);
hbp = var->left_margin;
hfp = var->right_margin;
vbp = var->upper_margin;
vfp = var->lower_margin;
hspw = var->hsync_len;
vspw = var->vsync_len;
width = mfd->panel_info.xres;
//.........这里部分代码省略.........
示例13: mdss_dsi_cmd_dma_tx
static int mdss_dsi_cmd_dma_tx(struct mdss_dsi_ctrl_pdata *ctrl,
struct dsi_buf *tp)
{
int len, ret = 0;
int domain = MDSS_IOMMU_DOMAIN_UNSECURE;
char *bp;
unsigned long size, addr;
bp = tp->data;
len = ALIGN(tp->len, 4);
size = ALIGN(tp->len, SZ_4K);
if (is_mdss_iommu_attached()) {
int ret = msm_iommu_map_contig_buffer(tp->dmap,
mdss_get_iommu_domain(domain), 0,
size, SZ_4K, 0, &(addr));
if (IS_ERR_VALUE(ret)) {
pr_err("unable to map dma memory to iommu(%d)\n", ret);
return -ENOMEM;
}
} else {
addr = tp->dmap;
}
INIT_COMPLETION(ctrl->dma_comp);
if (ctrl->shared_pdata.broadcast_enable)
if ((ctrl->ndx == DSI_CTRL_1)
&& (left_ctrl_pdata != NULL)) {
MIPI_OUTP(left_ctrl_pdata->ctrl_base + 0x048, addr);
MIPI_OUTP(left_ctrl_pdata->ctrl_base + 0x04c, len);
}
MIPI_OUTP((ctrl->ctrl_base) + 0x048, addr);
MIPI_OUTP((ctrl->ctrl_base) + 0x04c, len);
wmb();
if (ctrl->shared_pdata.broadcast_enable)
if ((ctrl->ndx == DSI_CTRL_1)
&& (left_ctrl_pdata != NULL)) {
MIPI_OUTP(left_ctrl_pdata->ctrl_base + 0x090, 0x01);
}
MIPI_OUTP((ctrl->ctrl_base) + 0x090, 0x01); /* trigger */
wmb();
ret = wait_for_completion_timeout(&ctrl->dma_comp,
msecs_to_jiffies(DMA_TX_TIMEOUT));
if (ret == 0)
ret = -ETIMEDOUT;
else
ret = tp->len;
if (is_mdss_iommu_attached())
msm_iommu_unmap_contig_buffer(addr,
mdss_get_iommu_domain(domain), 0, size);
return ret;
}示例14: mdss_dsi_cmd_dma_tx
static int mdss_dsi_cmd_dma_tx(struct mdss_dsi_ctrl_pdata *ctrl,
struct dsi_buf *tp)
{
int len, ret = 0;
int domain = MDSS_IOMMU_DOMAIN_UNSECURE;
char *bp;
unsigned long size, addr;
struct mdss_dsi_ctrl_pdata *mctrl = NULL;
bp = tp->data;
len = ALIGN(tp->len, 4);
size = ALIGN(tp->len, SZ_4K);
if (is_mdss_iommu_attached()) {
ret = msm_iommu_map_contig_buffer(tp->dmap,
mdss_get_iommu_domain(domain), 0,
size, SZ_4K, 0, &(addr));
if (IS_ERR_VALUE(ret)) {
pr_err("unable to map dma memory to iommu(%d)\n", ret);
return -ENOMEM;
}
} else {
addr = tp->dmap;
}
INIT_COMPLETION(ctrl->dma_comp);
/* Ensure that for slave controller, master is also configured */
if (mdss_dsi_is_slave_ctrl(ctrl)) {
mctrl = mdss_dsi_get_master_ctrl();
if (mctrl) {
MIPI_OUTP(mctrl->ctrl_base + 0x048, addr);
MIPI_OUTP(mctrl->ctrl_base + 0x04c, len);
} else {
pr_warn("%s: Unable to get master control\n",
__func__);
}
}
MIPI_OUTP((ctrl->ctrl_base) + 0x048, addr);
MIPI_OUTP((ctrl->ctrl_base) + 0x04c, len);
wmb();
/* Trigger on master controller as well */
if (mctrl)
MIPI_OUTP(mctrl->ctrl_base + 0x090, 0x01);
MIPI_OUTP((ctrl->ctrl_base) + 0x090, 0x01);
wmb();
ret = wait_for_completion_timeout(&ctrl->dma_comp,
msecs_to_jiffies(DMA_TX_TIMEOUT));
if (ret == 0)
ret = -ETIMEDOUT;
else
ret = tp->len;
if (is_mdss_iommu_attached())
msm_iommu_unmap_contig_buffer(addr,
mdss_get_iommu_domain(domain), 0, size);
return ret;
}示例15: mipi_dsi_phy_init
void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
int target_type)
{
struct mipi_dsi_phy_ctrl *pd;
int i, off;
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);/* start phy sw reset */
msleep(100);
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);/* end phy w reset */
MIPI_OUTP(MIPI_DSI_BASE + 0x2cc, 0x0003);/* regulator_ctrl_0 */
MIPI_OUTP(MIPI_DSI_BASE + 0x2d0, 0x0001);/* regulator_ctrl_1 */
MIPI_OUTP(MIPI_DSI_BASE + 0x2d4, 0x0001);/* regulator_ctrl_2 */
MIPI_OUTP(MIPI_DSI_BASE + 0x2d8, 0x0000);/* regulator_ctrl_3 */
#ifdef DSI_POWER
MIPI_OUTP(MIPI_DSI_BASE + 0x2dc, 0x0100);/* regulator_ctrl_4 */
#endif
pd = (panel_info->mipi).dsi_phy_db;
off = 0x02cc; /* regulator ctrl 0 */
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
wmb();
off += 4;
}
off = 0x0260; /* phy timig ctrl 0 */
for (i = 0; i < 11; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
wmb();
off += 4;
}
off = 0x0290; /* ctrl 0 */
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
wmb();
off += 4;
}
off = 0x02a0; /* strength 0 */
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
wmb();
off += 4;
}
mipi_dsi_calibration();
off = 0x0204; /* pll ctrl 1, skip 0 */
for (i = 1; i < 21; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
wmb();
off += 4;
}
if (panel_info)
mipi_dsi_phy_pll_config(panel_info->clk_rate);
/* pll ctrl 0 */
MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
wmb();
}