C++ MAP_GPIOPinWrite函数代码示例

/**
 * Read Control Register (RCR)
 */
uint8_t enc_rcr(uint8_t reg) {
	MAP_GPIOPinWrite(ENC_CS_PORT, ENC_CS, 0);
	spi_send(reg);
	uint8_t b = spi_send(0xFF);
	MAP_GPIOPinWrite(ENC_CS_PORT, ENC_CS, ENC_CS);
	return b;
}

//*****************************************************************************
//
//! Initialize LEDs
//!
//! \param  none
//!
//! \return none
//!
//! \brief  Initializes LED Ports and Pins
//
//*****************************************************************************
void initLEDs()
{
	// Enable use of PORTF to toggle LED and disable interrupt on this port
	MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
    //
    // Unlock PF0 so we can change it to a GPIO input
    // Once we have enabled (unlocked) the commit register then re-lock it
    // to prevent further changes.  PF0 is muxed with NMI thus a special case.
    //
    HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY_DD;
    HWREG(GPIO_PORTF_BASE + GPIO_O_CR) |= 0x01;
    HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = 0;

    
	MAP_GPIOPinIntDisable(GPIO_PORTF_BASE, 0xFF);
	
	// Configure Red LED
	MAP_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1);
	MAP_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1, PIN_LOW); 
	
	// Configure Blue LED
	MAP_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_2);
	MAP_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, PIN_LOW); 
	
	// Configure Green LED
	MAP_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_3);
	MAP_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_3, PIN_LOW); 
	
    
    // Button inputs
	ROM_GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_4, GPIO_DIR_MODE_IN);
    ROM_GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_4, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);

}

void arch_GpioSet(uint_t nPort, uint_t nPin, uint_t nHL)
{

	if (nHL)
		MAP_GPIOPinWrite(arch_GpioPortBase(nPort), BITMASK(nPin), 0xFF);
	else
		MAP_GPIOPinWrite(arch_GpioPortBase(nPort), BITMASK(nPin), 0);
}

/**
 * Bit Field Clear.
 * Clear the bits of argument 'mask' in the register 'reg'.
 * Not valid for MAC and MII registers.
 */
void enc_bfc(uint8_t reg, uint8_t mask) {

	MAP_GPIOPinWrite(ENC_CS_PORT, ENC_CS, 0);
	spi_send(0xA0 | reg);
	spi_send(mask);

	MAP_GPIOPinWrite(ENC_CS_PORT, ENC_CS, ENC_CS);
}

//*****************************************************************************
//
// This function turns the USER LED ON/OFF
// 
//!
//! \param  ledNum is the LED Number
//!
//! \return none
//!
//! \brief  Turns a specific LED Off
//
//*****************************************************************************
void turnLedOn(char ledNum)
{
	
	switch (ledNum)
	{
		//RED
	case 1:
		//turn other blue and green LED off
		MAP_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, PIN_LOW);
		MAP_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_3, PIN_LOW);
		//turn RED LED on
		MAP_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1, PIN_HIGH);
		break;
		
		//Blue
	case 2:
		//turn other red and green LED off
		MAP_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1, PIN_LOW);
		MAP_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_3, PIN_LOW);
		//turn BLUE LED on
		MAP_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, PIN_HIGH);
		break;
		
		//Green
	case 3:
		//turn other red and blue LED off
		MAP_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1, PIN_LOW);
		MAP_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, PIN_LOW);
		//turn GREEN LED on
		MAP_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_3, PIN_HIGH);
		break;
	}
}

void WriteWlanPin( unsigned char val )
{
	if(val)
	{
  		MAP_GPIOPinWrite(SPI_GPIO_IRQ_BASE, SPI_EN_PIN,PIN_HIGH);
	}
	else
	{
  		MAP_GPIOPinWrite(SPI_GPIO_IRQ_BASE, SPI_EN_PIN, PIN_LOW);
	}
	
}

pio_type platform_pio_op( unsigned port, pio_type pinmask, int op )
{
    pio_type retval = 1, base = pio_base[ port ];

    switch( op )
    {
    case PLATFORM_IO_PORT_SET_VALUE:
        MAP_GPIOPinWrite( base, 0xFF, pinmask );
        break;

    case PLATFORM_IO_PIN_SET:
        MAP_GPIOPinWrite( base, pinmask, pinmask );
        break;

    case PLATFORM_IO_PIN_CLEAR:
        MAP_GPIOPinWrite( base, pinmask, 0 );
        break;

    case PLATFORM_IO_PORT_DIR_INPUT:
        pinmask = 0xFF;
    case PLATFORM_IO_PIN_DIR_INPUT:
        MAP_GPIOPinTypeGPIOInput( base, pinmask );
        break;

    case PLATFORM_IO_PORT_DIR_OUTPUT:
        pinmask = 0xFF;
    case PLATFORM_IO_PIN_DIR_OUTPUT:
        MAP_GPIOPinTypeGPIOOutput( base, pinmask );
        break;

    case PLATFORM_IO_PORT_GET_VALUE:
        retval = MAP_GPIOPinRead( base, 0xFF );
        break;

    case PLATFORM_IO_PIN_GET:
        retval = MAP_GPIOPinRead( base, pinmask ) ? 1 : 0;
        break;

    case PLATFORM_IO_PIN_PULLUP:
    case PLATFORM_IO_PIN_PULLDOWN:
        MAP_GPIOPadConfigSet( base, pinmask, GPIO_STRENGTH_8MA, op == PLATFORM_IO_PIN_PULLUP ? GPIO_PIN_TYPE_STD_WPU : GPIO_PIN_TYPE_STD_WPD );
        break;

    case PLATFORM_IO_PIN_NOPULL:
        MAP_GPIOPadConfigSet( base, pinmask, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD );
        break;

    default:
        retval = 0;
        break;
    }
    return retval;
}

/**
 * Read Buffer Memory.
 */
void enc_rbm(uint8_t *buf, uint16_t count) {

	MAP_GPIOPinWrite(ENC_CS_PORT, ENC_CS, 0);

	spi_send(0x20 | 0x1A);
	int i;
	for (i = 0; i < count; i++) {
		*buf = spi_send(0xFF);
		buf++;
	}

	MAP_GPIOPinWrite(ENC_CS_PORT, ENC_CS, ENC_CS);
}

/**
 * Write Buffer Memory.
 */
void enc_wbm(const uint8_t *buf, uint16_t count) {

	MAP_GPIOPinWrite(ENC_CS_PORT, ENC_CS, 0);

	spi_send(0x60 | 0x1A);
	int i;
	for (i = 0; i < count; i++) {
		spi_send(*buf);
		buf++;
	}


	MAP_GPIOPinWrite(ENC_CS_PORT, ENC_CS, ENC_CS);
}

void AntennaSelect(unsigned char ucAntNum)
{

    if(ucAntNum == 1)
    {
         MAP_GPIOPinWrite(GPIOA3_BASE, 0xC, 0x8);
    }
    else if(ucAntNum == 2)
    {
        MAP_GPIOPinWrite(GPIOA3_BASE, 0xC, 0x4);
    }

    return;
}

void antenna_select (antenna_type_t _antenna) {
    if (_antenna == ANTENNA_TYPE_INTERNAL) {
        MAP_GPIOPinWrite(GPIOA3_BASE, 0x0C, 0x04);
        // also configure the pull-up and pull-down accordingly
        HWREG(REG_PAD_CONFIG_26) = ((HWREG(REG_PAD_CONFIG_26) & ~PAD_TYPE_MASK)) | PIN_TYPE_STD_PU;
        HWREG(REG_PAD_CONFIG_27) = ((HWREG(REG_PAD_CONFIG_27) & ~PAD_TYPE_MASK)) | PIN_TYPE_STD_PD;
    } else {
        MAP_GPIOPinWrite(GPIOA3_BASE, 0x0C, 0x08);
        // also configure the pull-up and pull-down accordingly
        HWREG(REG_PAD_CONFIG_26) = ((HWREG(REG_PAD_CONFIG_26) & ~PAD_TYPE_MASK)) | PIN_TYPE_STD_PD;
        HWREG(REG_PAD_CONFIG_27) = ((HWREG(REG_PAD_CONFIG_27) & ~PAD_TYPE_MASK)) | PIN_TYPE_STD_PU;
    }
    antenna_type_selected = _antenna;
}

/// \method value([value])
/// Get or set the digital logic level of the pin:
///
///   - With no arguments, return 0 or 1 depending on the logic level of the pin.
///   - With `value` given, set the logic level of the pin.  `value` can be
///   anything that converts to a boolean.  If it converts to `True`, the pin
///   is set high, otherwise it is set low.
STATIC mp_obj_t pin_value(mp_uint_t n_args, const mp_obj_t *args) {
    pin_obj_t *self = args[0];
    if (n_args == 1) {
        // get the pin value
        return MP_OBJ_NEW_SMALL_INT(MAP_GPIOPinRead(self->port, self->bit) ? 1 : 0);
    } else {
        // set the pin value
        if (mp_obj_is_true(args[1])) {
            MAP_GPIOPinWrite(self->port, self->bit, self->bit);
        } else {
            MAP_GPIOPinWrite(self->port, self->bit, 0);
        }
        return mp_const_none;
    }
}

//*****************************************************************************
//
// Initializes the SSI port and determines if the TRF79x0 is available.
//
// This function must be called prior to any other function offered by the
// TRF79x0.  It configures the SSI port to run in Motorola/Freescale
// mode.
//
// \return None.
//
//*****************************************************************************
void
SSITRF79x0Init(void)
{
    //
    // Enable the peripherals used to drive the TRF79x0 on SSI.
    //
    MAP_SysCtlPeripheralEnable(TRF79X0_SSI_PERIPH);

    //
    // Enable the GPIO peripherals associated with the SSI.
    //
    MAP_SysCtlPeripheralEnable(TRF79X0_CLK_PERIPH);
    MAP_SysCtlPeripheralEnable(TRF79X0_RX_PERIPH);
    MAP_SysCtlPeripheralEnable(TRF79X0_TX_PERIPH);
    MAP_SysCtlPeripheralEnable(TRF79X0_CS_PERIPH);

    //
    // Configure the appropriate pins to be SSI instead of GPIO.  The CS
    // is configured as GPIO to support TRF79x0 SPI requirements for R/W
    // access.
    //
    MAP_GPIOPinConfigure(TRF79X0_CLK_CONFIG);
    MAP_GPIOPinConfigure(TRF79X0_RX_CONFIG);
    MAP_GPIOPinConfigure(TRF79X0_TX_CONFIG);
    MAP_GPIOPinTypeSSI(TRF79X0_CLK_BASE, TRF79X0_CLK_PIN);
    MAP_GPIOPinTypeSSI(TRF79X0_RX_BASE, TRF79X0_RX_PIN);
    MAP_GPIOPinTypeSSI(TRF79X0_TX_BASE, TRF79X0_TX_PIN);
    MAP_GPIOPinTypeGPIOOutput(TRF79X0_CS_BASE, TRF79X0_CS_PIN);

    MAP_GPIOPadConfigSet(TRF79X0_CLK_BASE, TRF79X0_CLK_PIN,
                         GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
    MAP_GPIOPadConfigSet(TRF79X0_RX_BASE, TRF79X0_RX_PIN,
                         GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
    MAP_GPIOPadConfigSet(TRF79X0_TX_BASE, TRF79X0_TX_PIN,
                         GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);

    //
    // Deassert the SSI chip selects TRF79x0.
    //
    MAP_GPIOPinWrite(TRF79X0_CS_BASE, TRF79X0_CS_PIN, TRF79X0_CS_PIN);

    //
    // Configure the SSI port for 2MHz operation.
    //
    MAP_SSIConfigSetExpClk(TRF79X0_SSI_BASE, g_ui32SysClk,
                           SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SSI_CLK_RATE,
                           8);

    if(RF_DAUGHTER_TRF7970) {
        //
        // Switch from SPH=0 to SPH=1.  Required for TRF7970.
        //
        HWREG(TRF79X0_SSI_BASE + SSI_O_CR0) |= SSI_CR0_SPH;
    }

    //
    // Enable the SSI controller.
    //
    MAP_SSIEnable(TRF79X0_SSI_BASE);
}

static void
enc28j60_comm_init(void) {
  MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
  MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
  MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
  MAP_GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, ENC_CS | ENC_RESET);
  MAP_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, SRAM_CS);
//  MAP_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, ENC_CS | ENC_RESET | SRAM_CS);
  MAP_GPIOPinTypeGPIOInput(GPIO_PORTE_BASE, ENC_INT);

  MAP_GPIOPinWrite(GPIO_PORTB_BASE, ENC_RESET, 0);
  MAP_GPIOPinWrite(ENC_CS_PORT, ENC_CS, ENC_CS);
  MAP_GPIOPinWrite(GPIO_PORTA_BASE, SRAM_CS, SRAM_CS);
  SysCtlDelay(((SysCtlClockGet() / 3) / 10)); //100ms delay
  MAP_GPIOPinWrite(GPIO_PORTB_BASE, ENC_RESET, ENC_RESET);
}

int main(){

	// System clock set to run at 50 MHz from PLL with crystal ref.
	// With EK-TM4C123GXL Launchpad, no need to change SYSCTL_XTAL_16MHZ to anything else
	MAP_SysCtlClockSet(SYSCTL_SYSDIV_4|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);
	MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
	MAP_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, LED_RED|LED_BLUE|LED_GREEN);

	while(1){
		MAP_GPIOPinWrite(GPIO_PORTF_BASE, LED_RED|LED_GREEN|LED_BLUE, LED_GREEN|LED_RED|LED_BLUE);
		// SysCtlDelay and ROM_SysCtlDelay behave differently, see http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/256106.aspx
		MAP_SysCtlDelay(2333333);	// Number of loop iterations to perform @ 3 cycles/loop using ROM. Not Accurate. Input = (DesiredTime*ClockFrequency)/3
		MAP_GPIOPinWrite(GPIO_PORTF_BASE, LED_RED|LED_GREEN|LED_BLUE, 0);
		MAP_SysCtlDelay(16333333);
	}
}