C++ MAKE_SBDFO函数代码示例

VOID
GfxFmDisableController (
  IN       AMD_CONFIG_PARAMS      *StdHeader
  )
{
  GnbLibPciRMW (
    MAKE_SBDFO (0, 0, 0, 0,D0F0x7C_ADDRESS),
    AccessS3SaveWidth32,
    0xffffffff,
    1 << D0F0x7C_ForceIntGFXDisable_OFFSET,
    StdHeader
    );
}

/**
 * Single socket call to determine if the BIOS is responsible for updating the
 * northbridge operating frequency and voltage.
 *
 * This function simply returns whether or not the executing core needs NB COF
 * VID programming.
 *
 * @param[in]  StdHeader              Config handle for library and services
 *
 * @retval     TRUE    BIOS needs to set up NB frequency and voltage
 * @retval     FALSE   BIOS does not need to set up NB frequency and voltage
 *
 */
BOOLEAN
GetSystemNbCofVidUpdateSingle (
  IN       AMD_CONFIG_PARAMS *StdHeader
  )
{
  BOOLEAN   Ignored;
  PCI_ADDR PciAddress;
  CPU_SPECIFIC_SERVICES *FamilySpecificServices;

  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
  return (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &Ignored, StdHeader));
}

/**
 * Return the number of cores (1 based count) on Node.
 *
 * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}
 *
 * @param[in]     Node   the Node that will be examined
 * @param[in]     Nb     this northbridge
 *
 * @return        the number of cores
 */
UINT8
Fam15Mod1xGetNumCoresOnNode (
  IN       UINT8       Node,
  IN       NORTHBRIDGE *Nb
  )
{
  UINT32 Result;
  UINT32 Leveling;
  UINT32 Cores;
  UINT8 i;
  PCI_ADDR Reg;

  ASSERT ((Node < MAX_NODES));
  // Read CmpCap
  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
                                 MakePciBusFromNode (Node),
                                 MakePciDeviceFromNode (Node),
                                 CPU_NB_FUNC_05,
                                 REG_NB_CAPABILITY_2_5X84);

  LibAmdPciReadBits (Reg, 7, 0, &Result, Nb->ConfigHandle);

  // Support Downcoring
  Cores = Result;
  Cores++;
  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
                                 MakePciBusFromNode (Node),
                                 MakePciDeviceFromNode (Node),
                                 CPU_NB_FUNC_03,
                                 REG_NB_DOWNCORE_3X190);
  LibAmdPciReadBits (Reg, 31, 0, &Leveling, Nb->ConfigHandle);
  for (i = 0; i < Cores; i++) {
    if ((Leveling & ((UINT32) 1 << i)) != 0) {
      Result--;
    }
  }
  return (UINT8) (Result + 1);
}

AGESA_STATUS
STATIC
PcieMapPortsPciAddresses (
    IN      PCIe_SILICON_CONFIG    *Silicon,
    IN      PCIe_PLATFORM_CONFIG   *Pcie
)
{
    AGESA_STATUS        Status;
    AGESA_STATUS        AgesaStatus;
    PCIe_WRAPPER_CONFIG *WrapperList;
    PCIe_ENGINE_CONFIG  *EngineList;
    AgesaStatus = AGESA_SUCCESS;
    WrapperList = PcieConfigGetChildWrapper (Silicon);
    while (WrapperList != NULL) {
        EngineList = PcieConfigGetChildEngine (WrapperList);
        while (EngineList != NULL) {
            if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
                Status = PcieFmMapPortPciAddress (EngineList);
                AGESA_STATUS_UPDATE (Status, AgesaStatus);
                if (Status == AGESA_SUCCESS) {
                    EngineList->Type.Port.Address.AddressValue = MAKE_SBDFO (
                                0,
                                Silicon->Address.Address.Bus,
                                EngineList->Type.Port.PortData.DeviceNumber,
                                EngineList->Type.Port.PortData.FunctionNumber,
                                0
                            );
                } else {
                    EngineList->Type.Port.PortData.PortPresent = OFF;
                    IDS_HDT_CONSOLE (PCIE_MISC, "  ERROR! Fail to allocate PCI address for PCIe port\n"
                                    );
                    //Report error
                    PutEventLog (
                        AGESA_ERROR,
                        GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION,
                        EngineList->Type.Port.PortData.DeviceNumber,
                        0,
                        0,
                        0,
                        GnbLibGetHeader (Pcie)
                    );
                }
            }
            EngineList = PcieLibGetNextDescriptor (EngineList);
        }
        WrapperList = PcieLibGetNextDescriptor (WrapperList);
    }
    return AgesaStatus;
}

/**
 * Return the Link to the Southbridge
 *
 * @HtNbMethod{::F_READ_SB_LINK}
 *
 * @param[in] Nb this northbridge
 *
 * @return the Link to the southbridge
 */
UINT8
ReadSouthbridgeLink (
  IN       NORTHBRIDGE *Nb
  )
{
  UINT32 Temp;
  PCI_ADDR Reg;
  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
                                 MakePciBusFromNode (0),
                                 MakePciDeviceFromNode (0),
                                 CPU_HTNB_FUNC_00,
                                 REG_UNIT_ID_0X64);
  LibAmdPciReadBits (Reg, 10, 8, &Temp, Nb->ConfigHandle);
  return (UINT8)Temp;
}

/**
 * Create IVHD entry
 *
 *
 * @param[in]  Ivhd            IVHD header pointer
 * @param[in]  StdHeader       Standard configuration header
 *
 */
VOID
SbCreateIvhdEntries (
     OUT   IVRS_IVHD_ENTRY            *Ivhd,
  IN       AMD_CONFIG_PARAMS          *StdHeader
  )
{
  PCI_ADDR  Start;
  PCI_ADDR  End;
  PCI_ADDR  PciAddress;
  UINT32    Value;
  AMD_LATE_PARAMS        *LateParamsPtr;
  IDS_HDT_CONSOLE (GNB_TRACE, "SbCreateIvhdEntries Entry\n");
  LateParamsPtr = (AMD_LATE_PARAMS *) StdHeader;
  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 4, 0);
// P2P alias entry
  GnbLibPciRead (PciAddress.AddressValue | 0x18, AccessWidth32, &Value, StdHeader);
  Start.AddressValue = MAKE_SBDFO (0, (Value >> 8) & 0xff, 0, 0, 0);
  End.AddressValue = MAKE_SBDFO (0, (Value >> 16) & 0xff, 0x1f, 0x7, 0);
  GnbIvhdAddDeviceAliasRangeEntry (Start, End, PciAddress, 0, Ivhd, StdHeader);
  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0, 0);
// HPET
  GnbIvhdAddSpecialDeviceEntry (IvhdSpecialDeviceHpet, PciAddress, 0, 0, Ivhd, StdHeader);

// APIC
  if (LateParamsPtr->GnbLateConfiguration.FchIoapicId != 0xff) {
    GnbIvhdAddSpecialDeviceEntry (
      IvhdSpecialDeviceIoapic,
      PciAddress,
      LateParamsPtr->GnbLateConfiguration.FchIoapicId,
      0xD7,
      Ivhd,
      StdHeader
      );
  }
  IDS_HDT_CONSOLE (GNB_TRACE, "SbCreateIvhdEntries Exit\n");
}

AGESA_STATUS
GfxConfigPostInterface (
  IN       AMD_CONFIG_PARAMS        *StdHeader
  )
{
  GFX_PLATFORM_CONFIG       *Gfx;
  AMD_POST_PARAMS           *PostParamsPtr;
  AGESA_STATUS              Status;
  GNB_BUILD_OPTIONS_COMMON  *GnbCommonOptions;
  PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
  Status = AGESA_SUCCESS;
  IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Enter\n");
  Gfx = GnbAllocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
  ASSERT (Gfx != NULL);
  if (Gfx != NULL) {
    LibAmdMemFill (Gfx, 0x00, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
    GnbCommonOptions = (GNB_BUILD_OPTIONS_COMMON*) GnbFmGnbBuildOptions (StdHeader);
    if (GnbBuildOptions.IgfxModeAsPcieEp) {
      Gfx->GfxControllerMode = GfxControllerPcieEndpointMode;
      Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0);
    } else {
      Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode;
      Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0);
    }
    Gfx->StdHeader = (PVOID) StdHeader;
    Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio;
    Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport;
    Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate;
    Gfx->LcdBackLightControl = PostParamsPtr->PlatformConfig.LcdBackLightControl;
    Gfx->AmdPlatformType = UserOptions.CfgAmdPlatformType;
    Gfx->GmcClockGating = GnbCommonOptions->CfgGmcClockGating;
    Gfx->GmcPowerGating = GnbCommonOptions->GmcPowerGating;
    Gfx->UmaSteering = GnbCommonOptions->CfgUmaSteering;
    GNB_DEBUG_CODE (
      GfxConfigDebugDump (Gfx);
      );

/**
 *  Prepare a GNB ACG AZ Cmn entry on a family 15h Carrizo core.
 *
 * @param[in]    CurrentEntry       Current entry to process
 *
 * @return       Pointer to next table entry
 */
CS_RESTORATION_ENTRY_HEADER*
F15CzProcessAcgAzCmnIndexEntry (
  IN       CS_RESTORATION_ENTRY_HEADER  *CurrentEntry
  )
{
  PCI_ADDR           PciAddr;
  CS_GNB_ACG_AZ_CMN  *GnbAcgAzCmnEntry;

  GnbAcgAzCmnEntry = (CS_GNB_ACG_AZ_CMN *) CurrentEntry;
  if (GnbAcgAzCmnEntry->Header.SaveReadValue) {
    PciAddr.AddressValue = MAKE_SBDFO (0, 0, 9, 2, 0xE8);
    PspLibPciIndirectRead (PciAddr, (UINT32) GnbAcgAzCmnEntry->Address, AccessWidth32, &GnbAcgAzCmnEntry->Value);
  }
  GnbAcgAzCmnEntry++;
  return &GnbAcgAzCmnEntry->Header;
}

/**
 *  Prepare a GNB GBIF entry on a family 15h Carrizo core.
 *
 * @param[in]    CurrentEntry       Current entry to process
 *
 * @return       Pointer to next table entry
 */
CS_RESTORATION_ENTRY_HEADER*
F15CzProcessGnbGbifIndexEntry (
  IN       CS_RESTORATION_ENTRY_HEADER  *CurrentEntry
  )
{
  PCI_ADDR     PciAddr;
  CS_GNB_GBIF  *GnbGbifEntry;

  GnbGbifEntry = (CS_GNB_GBIF *) CurrentEntry;
  if (GnbGbifEntry->Header.SaveReadValue) {
    PciAddr.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xD0);
    PspLibPciIndirectRead (PciAddr, GnbGbifEntry->Address, AccessWidth32, &GnbGbifEntry->Value);
  }
  GnbGbifEntry++;
  return &GnbGbifEntry->Header;
}

/**
 *  Prepare a GNB ORB entry on a family 15h Carrizo core.
 *
 * @param[in]    CurrentEntry       Current entry to process
 *
 * @return       Pointer to next table entry
 */
CS_RESTORATION_ENTRY_HEADER*
F15CzProcessGnbOrbCfgEntry (
  IN       CS_RESTORATION_ENTRY_HEADER  *CurrentEntry
  )
{
  PCI_ADDR        PciAddr;
  CS_GNB_ORB_CFG  *GnbOrbCfgEntry;

  GnbOrbCfgEntry = (CS_GNB_ORB_CFG *) CurrentEntry;
  if (GnbOrbCfgEntry->Header.SaveReadValue) {
    PciAddr.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x94);
    PspLibPciIndirectRead (PciAddr, (UINT32) GnbOrbCfgEntry->Address, AccessWidth32, &GnbOrbCfgEntry->Value);
  }
  GnbOrbCfgEntry++;
  return &GnbOrbCfgEntry->Header;
}

/**
 * Get CSR phy self refresh power down mode.
 *
 *
 * @param[in] Channel    DCT controller index
 * @param[in] StdHeader  Standard configuration header
 * @retval    CsrPhySrPllPdMode
 */
UINT32
GfxLibGetCsrPhySrPllPdMode (
  IN       UINT8       Channel,
  IN       AMD_CONFIG_PARAMS      *StdHeader
  )
{
  D18F2x09C_x0D0FE00A_STRUCT     D18F2x09C_x0D0FE00A;

  GnbLibCpuPciIndirectRead (
    MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x98_ADDRESS : D18F2x198_ADDRESS),
    D18F2x09C_x0D0FE00A_ADDRESS,
    &D18F2x09C_x0D0FE00A.Value,
    StdHeader
    );

  return  D18F2x09C_x0D0FE00A.Field.CsrPhySrPllPdMode;
}

/**
 * Get disable DLL shutdown in self-refresh mode.
 *
 *
 * @param[in] Channel    DCT controller index
 * @param[in] StdHeader  Standard configuration header
 * @retval    DisDllShutdownSR
 */
UINT32
GfxLibGetDisDllShutdownSR (
  IN       UINT8       Channel,
  IN       AMD_CONFIG_PARAMS      *StdHeader
  )
{
  D18F2x90_STRUCT D18F2x090;

  GnbLibPciRead (
    MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x90_ADDRESS : D18F2x190_ADDRESS),
    AccessWidth32,
    &D18F2x090.Value,
    StdHeader
    );

  return  D18F2x090.Field.DisDllShutdownSR;
}

/**
 *  Prepare a GNB SPG CMN bits entry on a family 15h Carrizo core.
 *
 * @param[in]    CurrentEntry       Current entry to process
 *
 * @return       Pointer to next table entry
 */
CS_RESTORATION_ENTRY_HEADER*
F15CzProcessSpgCmnIndexBitsEntry (
  IN       CS_RESTORATION_ENTRY_HEADER  *CurrentEntry
  )
{
  PCI_ADDR              PciAddr;
  CS_GNB_SPG_CMN_BITS  *GnbSpgCmnBitsEntry;

  GnbSpgCmnBitsEntry = (CS_GNB_SPG_CMN_BITS *) CurrentEntry;
  if (GnbSpgCmnBitsEntry->Header.SaveReadValue) {
    PciAddr.AddressValue = MAKE_SBDFO (0, 0, 8, 0, 0xE8);
    PspLibPciIndirectRead (PciAddr, (UINT32) GnbSpgCmnBitsEntry->Address, AccessWidth32, &GnbSpgCmnBitsEntry->Value);
    GnbSpgCmnBitsEntry->Value &= ~GnbSpgCmnBitsEntry->Mask;
  }
  GnbSpgCmnBitsEntry++;
  return &GnbSpgCmnBitsEntry->Header;
}

VOID
GfxFillHtcData (
  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V6   *IntegratedInfoTable,
  IN       GFX_PLATFORM_CONFIG              *Gfx
  )
{
  D18F3x64_STRUCT  D18F3x64;

  GnbLibPciRead (
    MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x64_ADDRESS),
    AccessWidth32,
    &D18F3x64.Value,
    GnbLibGetHeader (Gfx)
    );
  IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52);
  IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2);
}

/**
 *  Prepare a GNB miscellaneous bits entry on a family 15h Carrizo core.
 *
 * @param[in]    CurrentEntry       Current entry to process
 *
 * @return       Pointer to next table entry
 */
CS_RESTORATION_ENTRY_HEADER*
F15CzProcessGnbMiscIndexBitsEntry (
  IN       CS_RESTORATION_ENTRY_HEADER  *CurrentEntry
  )
{
  PCI_ADDR          PciAddr;
  CS_GNB_MISC_BITS  *GnbMiscBitsEntry;

  GnbMiscBitsEntry = (CS_GNB_MISC_BITS *) CurrentEntry;
  if (GnbMiscBitsEntry->Header.SaveReadValue) {
    PciAddr.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x60);
    PspLibPciIndirectRead (PciAddr, GnbMiscBitsEntry->Address, AccessWidth32, &GnbMiscBitsEntry->Value);
    GnbMiscBitsEntry->Value &= ~GnbMiscBitsEntry->Mask;
  }
  GnbMiscBitsEntry++;
  return &GnbMiscBitsEntry->Header;
}