C++ LOCK_HARDWARE函数代码示例

/* Break the COW tie to the pbo.  Both the pbo and the region end up
 * with a copy of the data.
 */
void
intel_region_cow(struct intel_context *intel, struct intel_region *region)
{
   struct intel_buffer_object *pbo = region->pbo;
   GLboolean ok;

   intel_region_release_pbo(intel, region);

   assert(region->cpp * region->pitch * region->height == pbo->Base.Size);

   _DBG("%s %p (%d bytes)\n", __FUNCTION__, region, pbo->Base.Size);

   /* Now blit from the texture buffer to the new buffer: 
    */

   LOCK_HARDWARE(intel);
   ok = intelEmitCopyBlit(intel,
                          region->cpp,
                          region->pitch, pbo->buffer, 0, region->tiling,
                          region->pitch, region->buffer, 0, region->tiling,
                          0, 0, 0, 0,
                          region->pitch, region->height,
                          GL_COPY);
   assert(ok);
   UNLOCK_HARDWARE(intel);
}

void r128SpanRenderStart( GLcontext *ctx )
{
   r128ContextPtr rmesa = R128_CONTEXT(ctx);
   FLUSH_BATCH(rmesa);
   LOCK_HARDWARE(rmesa);
   r128WaitForIdleLocked( rmesa );
}

/* Upload data to a rectangular sub-region.  Lots of choices how to do this:
 *
 * - memcpy by span to current destination
 * - upload data as new buffer and blit
 *
 * Currently always memcpy.
 */
void
intel_region_data(struct intel_context *intel,
                  struct intel_region *dst,
                  GLuint dst_offset,
                  GLuint dstx, GLuint dsty,
                  const void *src, GLuint src_pitch,
                  GLuint srcx, GLuint srcy, GLuint width, GLuint height)
{
   _DBG("%s\n", __FUNCTION__);

   if (intel == NULL)
      return;

   if (dst->pbo) {
      if (dstx == 0 &&
          dsty == 0 && width == dst->pitch && height == dst->height)
         intel_region_release_pbo(intel, dst);
      else
         intel_region_cow(intel, dst);
   }

   LOCK_HARDWARE(intel);
   _mesa_copy_rect(intel_region_map(intel, dst) + dst_offset,
                   dst->cpp,
                   dst->pitch,
                   dstx, dsty, width, height, src, src_pitch, srcx, srcy);

   intel_region_unmap(intel, dst);
   UNLOCK_HARDWARE(intel);
}

void sisSpanRenderStart( GLcontext *ctx )
{
   sisContextPtr smesa = SIS_CONTEXT(ctx);

   SIS_FIREVERTICES(smesa);
   LOCK_HARDWARE();
   WaitEngIdle( smesa );
}

void i830FlushPrims( i830ContextPtr imesa )
{
   if (imesa->vertex_buffer) {
      LOCK_HARDWARE( imesa );
      i830FlushPrimsLocked( imesa );
      UNLOCK_HARDWARE( imesa );
   }
}

/* This waits for *everybody* to finish rendering -- overkill.
 */
void i810DmaFinish( i810ContextPtr imesa  ) 
{
   I810_FIREVERTICES( imesa );

   LOCK_HARDWARE( imesa );
   i810RegetLockQuiescent( imesa );
   UNLOCK_HARDWARE( imesa );
}

static void
nouveauSpanRenderStart( GLcontext *ctx )
{
   nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
   FIRE_RING();
   LOCK_HARDWARE(nmesa);
   nouveauWaitForIdleLocked( nmesa );
}

static void ffbDDFinish(GLcontext *ctx)
{
	ffbContextPtr fmesa = FFB_CONTEXT(ctx);

	LOCK_HARDWARE(fmesa);
	FFBWait(fmesa, fmesa->regs);
	UNLOCK_HARDWARE(fmesa);
}

/* Move locking out to get reasonable span performance.
 */
void intelSpanRenderStart( GLcontext *ctx )
{
   intelContextPtr intel = INTEL_CONTEXT(ctx);

   intelFlush(&intel->ctx);
   LOCK_HARDWARE(intel);
   intelWaitForIdle(intel);
}

static void radeonSpanRenderStart( GLcontext *ctx )
{
   radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
   //   R300_FIREVERTICES( rmesa );
   // old code has flush
   r300Flush(ctx);
   LOCK_HARDWARE( rmesa );
   radeonWaitForIdleLocked( rmesa );
}

int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint face )
{
   const int numLevels = t->base.lastLevel - t->base.firstLevel + 1;

   if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) {
      fprintf( stderr, "%s( %p, %p ) sz=%d lvls=%d-%d\n", __FUNCTION__,
	       (void *)rmesa->glCtx, (void *)t->base.tObj, t->base.totalSize,
	       t->base.firstLevel, t->base.lastLevel );
   }

   if ( !t || t->base.totalSize == 0 )
      return 0;

   LOCK_HARDWARE( rmesa );

   if ( t->base.memBlock == NULL ) {
      int heap;

      heap = driAllocateTexture( rmesa->texture_heaps, rmesa->nr_heaps,
				 (driTextureObject *) t );
      if ( heap == -1 ) {
	 UNLOCK_HARDWARE( rmesa );
	 return -1;
      }

      /* Set the base offset of the texture image */
      t->bufAddr = rmesa->radeonScreen->texOffset[heap] 
	   + t->base.memBlock->ofs;
      t->pp_txoffset = t->bufAddr;


      /* Mark this texobj as dirty on all units:
       */
      t->dirty_state = TEX_ALL;
   }


   /* Let the world know we've used this memory recently.
    */
   driUpdateTextureLRU( (driTextureObject *) t );
   UNLOCK_HARDWARE( rmesa );


   /* Upload any images that are new */
   if (t->base.dirty_images[face]) {
      int i;
      for ( i = 0 ; i < numLevels ; i++ ) {
         if ( (t->base.dirty_images[face] & (1 << (i+t->base.firstLevel))) != 0 ) {
            uploadSubImage( rmesa, t, i, 0, 0, t->image[face][i].width,
			    t->image[face][i].height, face );
         }
      }
      t->base.dirty_images[face] = 0;
   }

   return 0;
}

static void ffbBufferSize(GLframebuffer *buffer, GLuint *width, GLuint *height)
{
	GET_CURRENT_CONTEXT(ctx);
	ffbContextPtr fmesa = FFB_CONTEXT(ctx);

	LOCK_HARDWARE(fmesa);
	*width = fmesa->driDrawable->w;
	*height = fmesa->driDrawable->h;
	UNLOCK_HARDWARE(fmesa);
}

/* Make sure all commands have been sent to the hardware and have
 * completed processing.
 */
static void
sisFinish( GLcontext *ctx )
{
   sisContextPtr smesa = SIS_CONTEXT(ctx);

   SIS_FIREVERTICES(smesa);
   LOCK_HARDWARE();
   WaitEngIdle( smesa );
   UNLOCK_HARDWARE();
}

/* Even when doing full software rendering we need to
 * wrap render{start,finish} so that the hardware is kept
 * in sync (because multipass rendering changes the write
 * buffer etc.)
 */
static void ffbSWRenderStart(GLcontext *ctx)
{
	ffbContextPtr fmesa = FFB_CONTEXT(ctx);

	LOCK_HARDWARE(fmesa);
	fmesa->hw_locked = 1;

	if (fmesa->state_dirty != 0)
		ffbSyncHardware(fmesa);
}

/* Send all commands to the hardware.  If vertex buffers or indirect
 * buffers are in use, then we need to make sure they are sent to the
 * hardware.  All commands that are normally sent to the ring are
 * already considered `flushed'.
 */
static void mach64DDFlush( GLcontext *ctx )
{
   mach64ContextPtr mmesa = MACH64_CONTEXT(ctx);

   LOCK_HARDWARE( mmesa );
   FLUSH_DMA_LOCKED( mmesa );
   UNLOCK_HARDWARE( mmesa );

#if ENABLE_PERF_BOXES
   if ( mmesa->boxes ) {
      LOCK_HARDWARE( mmesa );
      mach64PerformanceBoxesLocked( mmesa );
      UNLOCK_HARDWARE( mmesa );
   }

   /* Log the performance counters if necessary */
   mach64PerformanceCounters( mmesa );
#endif
}