C++ IntRegister函数代码示例

static void USBAINTCConfigure(int usbInstance)
{   

	if(usbInstance)
	{
	    /* Registering the Interrupt Service Routine(ISR). */
	    IntRegister(SYS_INT_USB1, USB1HostIntHandler);

	    /* Setting the priority for the system interrupt in AINTC. */
	    IntPrioritySet(SYS_INT_USB1, 0, AINTC_HOSTINT_ROUTE_IRQ);

	    /* Enabling the system interrupt in AINTC. */
	    IntSystemEnable(SYS_INT_USB1);
	}
	else
	{
	    /* Registering the Interrupt Service Routine(ISR). */
	    IntRegister(SYS_INT_USB0, USB0HostIntHandler);

	    /* Setting the priority for the system interrupt in AINTC. */
	    IntPrioritySet(SYS_INT_USB0, 0, AINTC_HOSTINT_ROUTE_IRQ);

	    /* Enabling the system interrupt in AINTC. */
	    IntSystemEnable(SYS_INT_USB0);
	}
}

void _EDMAAppRegisterEdma3Interrupts()
{
    /* Enable IRQ in CPSR. */
    IntMasterIRQEnable();

    /* Intialize ARM interrupt controller */
    IntAINTCInit();

    /* Register Interrupts Here */

    /******************** Completion Interrupt ********************************/

    /* Registers Edma3ComplHandler0 Isr in Interrupt Vector Table of AINTC. */
    IntRegister(SYS_INT_EDMACOMPINT , _EDMAAppEdma3ccComplIsr);

    /* Set priority for system interrupt in AINTC */
    IntPrioritySet(SYS_INT_EDMACOMPINT, 0u, AINTC_HOSTINT_ROUTE_IRQ);

    /* Enable the EDMA CC0 system interrupt in AINTC.*/
    IntSystemEnable(SYS_INT_EDMACOMPINT);

    /********************** CC Error Interrupt ********************************/

    /*
    ** Registers the EDMA3_0 Channel Controller 0 Error Interrupt Isr in the
    ** Interrupt Vector Table of AINTC.
    */
    IntRegister(SYS_INT_EDMAERRINT , _EDMAAppEdma3ccErrIsr);

    /* Set priority for system interrupt in AINTC */
    IntPrioritySet(SYS_INT_EDMAERRINT, 0u, AINTC_HOSTINT_ROUTE_IRQ);

    /* Enable the EDMA CCERR system interrupt AINTC.*/
    IntSystemEnable(SYS_INT_EDMAERRINT);
}

int rt_hw_cpu_init(void)
{
    MAP_IntMasterDisable();
    IntRegister(FAULT_HARD, HardFault_Handler);	
    IntRegister(FAULT_PENDSV, PendSV_Handler);
    IntRegister(FAULT_SYSTICK, SysTick_Handler);
    
    // Enable lazy stacking for interrupt handlers.  This allows floating-point
    // instructions to be used within interrupt handlers, but at the expense of
    // extra stack usage.
    MAP_FPULazyStackingEnable();

    // Set the clocking to run directly from the external crystal/oscillator.
    // TODO: The SYSCTL_XTAL_ value must be changed to match the value of the
    // crystal on your board.
    SysClock = MAP_SysCtlClockFreqSet(
                (SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480),
                SYS_CLOCK_DEFAULT);

    MAP_SysTickDisable();
    MAP_SysTickPeriodSet(SysClock/ RT_TICK_PER_SECOND - 1);
    MAP_SysTickIntEnable();
    MAP_SysTickEnable();	

    return 0;
}

/* Interrupt mapping to AINTC and registering McSPI ISR */
void McSPIAintcConfigure(unsigned char instance)
{
	switch(instance)
	{
		case 0:
	    	//IntProtectionDisable();
			/* Register McSPIIsr interrupt handler */
			IntRegister(SYS_INT_SPI0INT, McSPI0Isr);

			/* Set Interrupt Priority */
			IntPrioritySet(SYS_INT_SPI0INT, 0, AINTC_HOSTINT_ROUTE_IRQ);

			/* Enable system interrupt in AINTC */
			IntSystemEnable(SYS_INT_SPI0INT);
	        //IntProtectionEnable();
			break;
		case 1:
	    	//IntProtectionDisable();
			/* Register McSPIIsr interrupt handler */
			IntRegister(SYS_INT_SPI1INT, McSPI1Isr);

			/* Set Interrupt Priority */
			IntPrioritySet(SYS_INT_SPI1INT, 0, AINTC_HOSTINT_ROUTE_IRQ);

			/* Enable system interrupt in AINTC */
			IntSystemEnable(SYS_INT_SPI1INT);
	        //IntProtectionEnable();
			break;
	}
}

/*
** configures arm interrupt controller to generate raster interrupt 
*/
void SetupIntc(void)
{
#ifdef _TMS320C6X
	IntDSPINTCInit();
	IntRegister(C674X_MASK_INT4, LCDIsr);
	IntEventMap(C674X_MASK_INT4, SYS_INT_LCDC_INT);
	IntEnable(C674X_MASK_INT4);
	IntGlobalEnable();
#else
    /* Initialize the ARM Interrupt Controller.*/
    IntAINTCInit();

    /* Register the ISR in the Interrupt Vector Table.*/
    IntRegister(SYS_INT_LCDINT, LCDIsr);

    /* Set the channnel number 2 of AINTC for LCD system interrupt.
     */
    IntChannelSet(SYS_INT_LCDINT, 2);

    /* Enable the System Interrupts for AINTC.*/
    IntSystemEnable(SYS_INT_LCDINT);
	IntSystemEnable(SYS_INT_I2CINT0); 
	
    /* Enable IRQ in CPSR.*/
    IntMasterIRQEnable();

    /* Enable the interrupts in GER of AINTC.*/
    IntGlobalEnable();

    /* Enable the interrupts in HIER of AINTC.*/
    IntIRQEnable();
#endif
}

//
// \brief  This function confiugres the AINTC to receive UART interrupts.
//
void CPDMAAINTCConfigure(int usbInstance)
{
	if(usbInstance)
	{
    	IntProtectionDisable();
		/* Registering the Interrupt Service Routine(ISR). */
		IntRegister(SYS_INT_USBSSINT, USB1HostIntHandler);

		/* Setting the priority for the system interrupt in AINTC. */
		IntPrioritySet(SYS_INT_USBSSINT, 0, AINTC_HOSTINT_ROUTE_IRQ);

		/* Enabling the system interrupt in AINTC. */
		IntSystemEnable(SYS_INT_USBSSINT);
        IntProtectionEnable();
	}
	else
	{
    	IntProtectionDisable();
	    /* Registering the Interrupt Service Routine(ISR). */
	    IntRegister(SYS_INT_USBSSINT, USB0HostIntHandler);

	    /* Setting the priority for the system interrupt in AINTC. */
	    IntPrioritySet(SYS_INT_USBSSINT, 0, AINTC_HOSTINT_ROUTE_IRQ);

	    /* Enabling the system interrupt in AINTC. */
	    IntSystemEnable(SYS_INT_USBSSINT);
        IntProtectionEnable();
	}
}

/*
** This function configures the AINTC to receive EDMA3 interrupts.
*/
static void EDMA3AINTCConfigure(void)
{
    /* Initializing the ARM Interrupt Controller. */
    IntAINTCInit();

    /* Registering EDMA3 Channel Controller transfer completion interrupt.  */
    IntRegister(EDMA_COMPLTN_INT_NUM, Edma3CompletionIsr);

    /* Setting the priority for EDMA3CC completion interrupt in AINTC. */
    IntPrioritySet(EDMA_COMPLTN_INT_NUM, 0, AINTC_HOSTINT_ROUTE_IRQ);

    /* Registering EDMA3 Channel Controller Error Interrupt. */
    IntRegister(EDMA_ERROR_INT_NUM, Edma3CCErrorIsr);

    /* Setting the priority for EDMA3CC Error interrupt in AINTC. */
    IntPrioritySet(EDMA_ERROR_INT_NUM, 0, AINTC_HOSTINT_ROUTE_IRQ);

    /* Enabling the EDMA3CC completion interrupt in AINTC. */
    IntSystemEnable(EDMA_COMPLTN_INT_NUM);
    
    /* Enabling the EDMA3CC Error interrupt in AINTC. */
    IntSystemEnable(EDMA_ERROR_INT_NUM);

    /* Registering HSMMC Interrupt handler */
    IntRegister(MMCSD_INT_NUM, HSMMCSDIsr);

    /* Setting the priority for EDMA3CC completion interrupt in AINTC. */
    IntPrioritySet(MMCSD_INT_NUM, 0, AINTC_HOSTINT_ROUTE_IRQ);

    /* Enabling the HSMMC interrupt in AINTC. */
    IntSystemEnable(MMCSD_INT_NUM);

    /* Enabling IRQ in CPSR of ARM processor. */
    IntMasterIRQEnable();
}

/*
** Configures arm/dsp interrupt controller to generate frame interrupt
*/
static void SetupIntc(void)
{
#ifdef _TMS320C6X
    /* Initialize the DSP interrupt controller */
    IntDSPINTCInit();

    /* Register VPIF ISR to vector table */
    IntRegister(C674X_MASK_INT5, VPIFIsr);

    /* Map system interrupt to DSP maskable interrupt for VPIF */
    IntEventMap(C674X_MASK_INT5, SYS_INT_VPIF_INT);

    /* Enable DSP maskable interrupt for VPIF */
    IntEnable(C674X_MASK_INT5);

    /* Register LCD ISR to vector table */
    IntRegister(C674X_MASK_INT6, LCDIsr);

    /* Map system interrupt to DSP maskable interrupt for LCD */
    IntEventMap(C674X_MASK_INT6, SYS_INT_LCDC_INT);

    /* Enable DSP maskable interrupt for LCD */
    IntEnable(C674X_MASK_INT6);

    /* Enable DSP interrupts */
    IntGlobalEnable();

#else
    /* Initialize the ARM Interrupt Controller.*/
    IntAINTCInit();

    /* Register the ISR in the Interrupt Vector Table.*/
    IntRegister(SYS_INT_VPIF, VPIFIsr);

    /* Set the channel number 2 of AINTC for LCD system interrupt.  */
    IntChannelSet(SYS_INT_VPIF, 2);

    /* Enable the System Interrupts for AINTC.*/
    IntSystemEnable(SYS_INT_VPIF);

    /* Register the ISR in the Interrupt Vector Table.*/
    IntRegister(SYS_INT_LCDINT, LCDIsr);

    /* Set the channnel number 2 of AINTC for LCD system interrupt.  */
    IntChannelSet(SYS_INT_LCDINT, 3);

    /* Enable the System Interrupts for AINTC.*/
    IntSystemEnable(SYS_INT_LCDINT);

    /* Enable IRQ in CPSR.*/
    IntMasterIRQEnable();

    /* Enable the interrupts in GER of AINTC.*/
    IntGlobalEnable();

    /* Enable the interrupts in HIER of AINTC.*/
    IntIRQEnable();
#endif
}

/* Configures AINTC to generate interrupt */
void I2CAINTCConfigure(new_twi* TwiStruct)
{
    /* Intialize the ARM Interrupt Controller(AINTC) */
    //IntAINTCInit();

    switch (TwiStruct->TwiNr)
    {
    case 0:
    	IntProtectionDisable();
        /* Registering the Interrupt Service Routine(ISR). */
        IntRegister(SYS_INT_I2C1_IRQ, I2C0Isr);

        /* Setting the priority for the system interrupt in AINTC. */
        IntPrioritySet(SYS_INT_I2C1_IRQ, TwiStruct->Priority, AINTC_HOSTINT_ROUTE_IRQ );

        /* Enabling the system interrupt in AINTC. */
        IntSystemEnable(SYS_INT_I2C1_IRQ);
        IntProtectionEnable();
    	break;
    case 1:
    	IntProtectionDisable();
        /* Registering the Interrupt Service Routine(ISR). */
        IntRegister(SYS_INT_I2C2_IRQ, I2C1Isr);

        /* Setting the priority for the system interrupt in AINTC. */
        IntPrioritySet(SYS_INT_I2C2_IRQ, TwiStruct->Priority, AINTC_HOSTINT_ROUTE_IRQ );

        /* Enabling the system interrupt in AINTC. */
        IntSystemEnable(SYS_INT_I2C2_IRQ);
        IntProtectionEnable();
    	break;
    case 2:
    	IntProtectionDisable();
        /* Registering the Interrupt Service Routine(ISR). */
        IntRegister(SYS_INT_I2C3_IRQ, I2C2Isr);

        /* Setting the priority for the system interrupt in AINTC. */
        IntPrioritySet(SYS_INT_I2C3_IRQ, TwiStruct->Priority, AINTC_HOSTINT_ROUTE_IRQ );

        /* Enabling the system interrupt in AINTC. */
        IntSystemEnable(SYS_INT_I2C3_IRQ);
        IntProtectionEnable();
    	break;
    case 3:
    	IntProtectionDisable();
        /* Registering the Interrupt Service Routine(ISR). */
        IntRegister(SYS_INT_I2C4_IRQ, I2C3Isr);

        /* Setting the priority for the system interrupt in AINTC. */
        IntPrioritySet(SYS_INT_I2C4_IRQ, TwiStruct->Priority, AINTC_HOSTINT_ROUTE_IRQ );

        /* Enabling the system interrupt in AINTC. */
        IntSystemEnable(SYS_INT_I2C4_IRQ);
        IntProtectionEnable();
    	break;
    }
}

/*
 * Public API
 */
void
ws_radio_init(void)
{
    WS_DEBUG("init\n");

    /* Reset state */
    memset(&radio_state, 0, sizeof(radio_state));

    /* Enable the clock */
    /* TODO: Power saving. We're basically leaving the radio on all the time */
    SysCtrlPeripheralReset(SYS_CTRL_PERIPH_RFC);
    SysCtrlPeripheralEnable(SYS_CTRL_PERIPH_RFC);
    SysCtrlPeripheralSleepEnable(SYS_CTRL_PERIPH_RFC);
    SysCtrlPeripheralDeepSleepEnable(SYS_CTRL_PERIPH_RFC);

    /* Configure CCA */
    HWREG(RFCORE_XREG_CCACTRL0) = CC2538_RFCORE_CCA_THRES;

    /* User Manual 23.15 - TX and RX settings */
    HWREG(RFCORE_XREG_AGCCTRL1) = CC2538_RFCORE_AGC_TARGET;
    HWREG(RFCORE_XREG_TXFILTCFG) = CC2538_RFCORE_TX_AA_FILTER;
    HWREG(ANA_REGS_BASE + ANA_REGS_O_IVCTRL) = CC2538_RFCORE_BIAS_CURRENT;
    HWREG(RFCORE_XREG_FSCAL1) = CC2538_RFCORE_FREQ_CAL;

    /* Enable auto CRC calculation (hardware) */
    HWREG(RFCORE_XREG_FRMCTRL0) = RFCORE_XREG_FRMCTRL0_AUTOCRC;

    /* Enable auto ACK */
    HWREG(RFCORE_XREG_FRMCTRL0) |= RFCORE_XREG_FRMCTRL0_AUTOACK;

    /* Configure the FIFOP signal to trigger when there are one or more
     * complete frames in the RX FIFO */
    HWREG(RFCORE_XREG_FIFOPCTRL) = WS_RADIO_MAX_PACKET_LEN;

    /* Set the TX output power */
    HWREG(RFCORE_XREG_TXPOWER) = CC2538_RFCORE_TX_POWER;

    /* Interrupt wth FIFOP signal */
    HWREG(RFCORE_XREG_RFIRQM0) = 0x04;
    IntRegister(INT_RFCORERTX, &rf_isr);
    IntEnable(INT_RFCORERTX);

    /* Interrupt with all RF ERROR signals */
    HWREG(RFCORE_XREG_RFERRM) = 0x7f;
    IntRegister(INT_RFCOREERR, &rf_err_isr);
    IntEnable(INT_RFCOREERR);

    /* Configure the frame filtering */
    HWREG(RFCORE_XREG_FRMFILT0) &= ~RFCORE_XREG_FRMFILT0_MAX_FRAME_VERSION_M;
    HWREG(RFCORE_XREG_FRMFILT0) |= WS_MAC_MAX_FRAME_VERSION <<
        RFCORE_XREG_FRMFILT0_MAX_FRAME_VERSION_S;
    /* Don't bother filtering out the source addresses */
    HWREG(RFCORE_XREG_SRCMATCH) &= ~RFCORE_XREG_SRCMATCH_SRC_MATCH_EN;
}

/*
** Sets up the interrupts for EDMA in AINTC
*/
static void EDMA3IntSetup(void)
{
#ifdef _TMS320C6X
    IntRegister(C674X_MASK_INT5, EDMA3CCComplIsr);
    IntEventMap(C674X_MASK_INT5, SYS_INT_EDMA3_0_CC0_INT1);
    IntEnable(C674X_MASK_INT5);
#else
    IntRegister(SYS_INT_CCINT0, EDMA3CCComplIsr);
    IntChannelSet(SYS_INT_CCINT0, INT_CHANNEL_EDMACC);
    IntSystemEnable(SYS_INT_CCINT0);
#endif
}

/*
** Sets up the I2C interrupt in the AINTC
*/
void I2C0IntRegister(unsigned int channel)
{
#ifdef _TMS320C6X
	IntRegister(C674X_MASK_INT5, I2C0Isr);
	IntEventMap(C674X_MASK_INT5, SYS_INT_I2C0_INT);
	IntEnable(C674X_MASK_INT5);
#else
    /* Register the ISR in the Interrupt Vector Table.*/
    IntRegister(SYS_INT_I2CINT0, I2C0Isr);
    IntChannelSet(SYS_INT_I2CINT0, channel);
#endif
}

/*
** Sets up the I2C interrupt in the AINTC
*/
static void I2CCodecIntSetup(unsigned int sysIntNum, unsigned int channel)
{
#ifdef _TMS320C6X
	IntRegister(C674X_MASK_INT4, I2CCodecIsr);
	IntEventMap(C674X_MASK_INT4, sysIntNum);
	IntEnable(C674X_MASK_INT4);
#else
    /* Register the ISR in the Interrupt Vector Table.*/
    IntRegister(sysIntNum, I2CCodecIsr);
    IntChannelSet(sysIntNum, channel);
    IntSystemEnable(sysIntNum);
#endif
}

/*******************************************************************************
** Name: SpiDevInit
** Input:HDC dev
** Return: rk_err_t
** Owner:Aaron.sun
** Date: 2014.5.30
** Time: 9:18:00
*******************************************************************************/
_DRIVER_SPI_SPIDEVICE_INIT_
INIT FUN rk_err_t SpiDevInit(SPI_DEVICE_CLASS * pstSpiDev)
{

	 //open uart clk
	if(((DEVICE_CLASS*)pstSpiDev)->DevID == 0)
	{
        ScuClockGateCtr(CLK_SPI0_GATE, 0);
        ScuClockGateCtr(PCLK_SPI0_GATE, 0);
        DelayMs(1);
        ScuClockGateCtr(CLK_SPI0_GATE, 1);
        ScuClockGateCtr(PCLK_SPI0_GATE, 1);
        ScuSoftResetCtr(SPI0_SRST, 1);
        DelayMs(1);
        ScuSoftResetCtr(SPI0_SRST, 0);
        //SetSPIFreq(0,PLL_MUX_CLK,96000000);
        SetSPIFreq(0,XIN24M,24000000);
        //open rst uart ip

	}
    else if(((DEVICE_CLASS*)pstSpiDev)->DevID == 1)
    {
        ScuClockGateCtr(CLK_SPI1_GATE, 1);
        ScuClockGateCtr(PCLK_SPI1_GATE, 1);
        SetSPIFreq(1,XIN24M,24000000);

        //open rst uart ip
        ScuSoftResetCtr(SPI1_SRST, 1);
        DelayMs(1);
        ScuSoftResetCtr(SPI1_SRST, 0);
    }
    SpiDevHwInit(((DEVICE_CLASS *)pstSpiDev)->DevID, pstSpiDev->CurCh);
    SPIInit(((DEVICE_CLASS *)pstSpiDev)->DevID,0, pstSpiDev->stConfig[pstSpiDev->CurCh].SpiRate,
            pstSpiDev->stConfig[pstSpiDev->CurCh].CtrlMode);

    if(((DEVICE_CLASS *)pstSpiDev)->DevID == 0)
    {
        IntRegister(INT_ID_SPI0,SpiDevIntIsr0);
        IntPendingClear(INT_ID_SPI0);
        IntEnable(INT_ID_SPI0);
    }
    else if(((DEVICE_CLASS*)pstSpiDev)->DevID == 1)
    {
        IntRegister(INT_ID_SPI1,SpiDevIntIsr1);
        IntPendingClear(INT_ID_SPI1);
        IntEnable(INT_ID_SPI1);
    }


    return RK_SUCCESS;
}

/*
** Sets up the error interrupts for McASP in AINTC
*/
static void McASPErrorIntSetup(void)
{
#ifdef _TMS320C6X
    IntRegister(C674X_MASK_INT6, McASPErrorIsr);
    IntEventMap(C674X_MASK_INT6, SYS_INT_MCASP0_INT);
    IntEnable(C674X_MASK_INT6);
#else
    /* Register the error ISR for McASP */
    IntRegister(SYS_INT_MCASPINT, McASPErrorIsr);

    IntChannelSet(SYS_INT_MCASPINT, INT_CHANNEL_MCASP);
    IntSystemEnable(SYS_INT_MCASPINT);
#endif
}