C++ IWDG_WriteAccessCmd函数代码示例

/** 
 * @brief Initialize the watchdog timer for a specified timeout
 *
 * It is important to note that this function returns the achieved timeout 
 * for this hardware.  For hardware independence this should be checked when
 * scheduling updates.  Other hardware dependent details may need to be 
 * considered such as a window time which sets a minimum update time, 
 * and this function should return a recommended delay for clearing.  
 *
 * For the STM32 nominal clock rate is 32 khz, but for the maximum clock rate of
 * 60 khz and a prescaler of 4 yields a clock rate of 15 khz.  The delay that is
 * set in the watchdog assumes the nominal clock rate, but the delay for FreeRTOS
 * to use is 75% of the minimal delay.
 *
 * @returns Maximum recommended delay between updates based on PIOS_WATCHDOG_TIMEOUT constant
 */
uint16_t PIOS_WDG_Init()
{
	uint16_t delay = ((uint32_t) PIOS_WATCHDOG_TIMEOUT * 60) / 16;
	if (delay > 0x0fff)
		delay = 0x0fff;
#if defined(PIOS_INCLUDE_WDG)
	DBGMCU_Config(DBGMCU_IWDG_STOP, ENABLE);	// make the watchdog stop counting in debug mode
	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
	IWDG_SetPrescaler(IWDG_Prescaler_16);
	IWDG_SetReload(delay);
	IWDG_ReloadCounter();
	IWDG_Enable();

	// watchdog flags now stored in backup registers
	PWR_BackupAccessCmd(ENABLE);

	wdg_configuration.bootup_flags = RTC_ReadBackupRegister(PIOS_WDG_REGISTER);

	/*
	 * Start from an empty set of registered flags so previous boots
	 * can't influence the current one
	 */
	RTC_WriteBackupRegister(PIOS_WDG_REGISTER, 0);
#endif
	return delay;
}

void PhotonWdgs::begin(bool _enableWwdg,bool _enableIwdg,unsigned long _timeout, TIMid id)
{
    if(!_enableWwdg && !_enableIwdg) {
        // nothing to do ...
        return;
    }
    PhotonWdgs::_aliveCount = 0;
    PhotonWdgs::_timeoutval = _timeout / 10;

    RCC_LSICmd(ENABLE); //LSI is needed for Watchdogs

    PhotonWdgs::_wdgTimer.begin(PhotonWdgs::_tickleWDGs, 20, hmSec, id);
    // OTA updates won't work with watchdog enabled
    System.disableUpdates();
    PhotonWdgs::_wwdgRunning = _enableWwdg;
    if(_enableWwdg) {
        RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE);
        WWDG_SetPrescaler(WWDG_Prescaler_8);
        WWDG_SetWindowValue(0x7F);
        WWDG_Enable(0x7F);
    }
    PhotonWdgs::_iwdgRunning = _enableIwdg;
    if(_enableIwdg) {
        IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
        IWDG_SetPrescaler(IWDG_Prescaler_256);
        IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
        IWDG_SetReload(0xFFF);
        IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
        IWDG_Enable();
    }
}

void	Watchdog(void) {
#ifdef	__PFM6__
			IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
			IWDG_ReloadCounter();
			IWDG_WriteAccessCmd(IWDG_WriteAccess_Disable);
#endif
}

/*******************************************************************************
函 数 名：void IWDG_Init(void)
功能描述：看门狗初始化						
入口参数：							
返回参数：
创建时间: 2011.6.24
********************************************************************************/
void IWDG_Init(void)
{
    IWDG_WriteAccessCmd( IWDG_WriteAccess_Enable );
    IWDG_SetPrescaler( IWDG_Prescaler_64);	//最小
    IWDG_SetReload( 0x138);		//40KHz内部时钟 (1/40000 * 64 * 0x138 = 0.5s)
    IWDG_WriteAccessCmd( IWDG_WriteAccess_Disable );
    IWDG_Enable();
    IWDG_ReloadCounter();
}

void	Watchdog_init(int t) {
#ifdef	__PFM6__
			IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
			IWDG_SetPrescaler(IWDG_Prescaler_32);
			IWDG_SetReload(t);
			while(IWDG_GetFlagStatus(IWDG_FLAG_RVU) == RESET);
			IWDG_ReloadCounter();
			IWDG_Enable();
			IWDG_WriteAccessCmd(IWDG_WriteAccess_Disable);
#endif
}

void IWDG_Init(void)
{

	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

	IWDG_SetPrescaler(IWDG_Prescaler_256);

	IWDG_SetReload(10);

  IWDG_WriteAccessCmd(IWDG_WriteAccess_Disable);

	IWDG_ReloadCounter();

	IWDG_Enable();
}

/**
  * @brief  Main program.
  * @param  None
  * @retval None
  */
void main(void)
{
  u8 i, cnt;
  disableInterrupts();
  Config();
  HBRIDGE_OFF;
  Errors_Init();
  RTMS_INIT(runtime_it_1ms);
  enableInterrupts();
  LED_GREEN_ON;
  // Wait for power supply settling
  Timeout_SetTimeout2(200);
  while(!Timeout_IsTimeout2());
  // END Wait for power supply settling
  LED_OFF;
  // Handle RESET flags
  if(RST_GetFlagStatus(RST_FLAG_IWDGF)) {
    BLINK_REDLED(1);
  }
  else if(RST_GetFlagStatus(RST_FLAG_ILLOPF)) {
    BLINK_REDLED(2);
  }
  RST_ClearFlag(RST_FLAG_POR_PDR | RST_FLAG_SWIMF | RST_FLAG_ILLOPF | RST_FLAG_IWDGF);
  while(ISBLINKING_REDLED);
  // END Handle RESET flags
  Retrieve_Check_ROM_Timer_Val();
  Timeout_SetTimeout1(HBRIDGE_CHARGE_TIME);
  
  IWDG_Enable();
  IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
  IWDG_SetPrescaler(IWDG_Prescaler_64);  /* 431.15ms for RL[7:0]= 0xFF */
  IWDG_SetReload(0xFF);
  IWDG_WriteAccessCmd(IWDG_WriteAccess_Disable);
  IWDG_ReloadCounter();
  
  LoadStateRequest = LOAD_NOT_POWERED;
  state = ST_WAIT_CAP_CHARGE;
  
  while (1)
  {
    TimerSwitch_StateMachine();
    Programming_Mode_Manager();
    Task_1000ms();
    Error_Handler();
    Display_Remaining_Time();
    IWDG_ReloadCounter();
  }
}

/**
 * @brief   iwdg config
 */
void IWDG_Configuration(void)
{
	/* Enable write access to IWDG_PR and IWDG_RLR registers */
	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

	/* IWDG counter clock: LSI/32 */
	IWDG_SetPrescaler(IWDG_Prescaler_32);

	/* Set counter reload value to obtain 250ms IWDG TimeOut.
	 Counter Reload Value = 250ms/IWDG counter clock period
						  = 250ms / (LSI/32)
						  = 0.25s / (LsiFreq/32)
						  = LsiFreq/(32 * 4)
						  = LsiFreq/128
	*/
//	IWDG_SetReload(LSI_FREQ / 128);

	// iwdg period is 1000mS
	IWDG_SetReload(LSI_FREQ / 32);

	/* Reload IWDG counter */
	IWDG_ReloadCounter();

	/* Enable IWDG (the LSI oscillator will be enabled by hardware) */
	IWDG_Enable();

}

void InitWatchdog(void){
	
	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
	IWDG_SetPrescaler(IWDG_Prescaler_4); 			
	IWDG_SetReload(0xFFF); 
	IWDG_Enable();
}

/**
  * @brief   Main program
  * @param  None
  * @retval None
  */
int main(void)
{	
	RCC_Configuration();
	GPIO_Configuration();
	USART_Configuration();	
	SysTick_Config(SystemCoreClock/10);
	// Enable the LSI OSC 
 	RCC_LSICmd(ENABLE);
	// Wait till LSI is ready 
	while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {};
	
 	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
	// IWDG counter clock: LSI/256 
	IWDG_SetPrescaler(IWDG_Prescaler_256);
	IWDG_SetReload(0x0FFF);
	// Reload IWDG counter 
	IWDG_ReloadCounter();
	// Enable IWDG (the LSI oscillator will be enabled by hardware) 
	IWDG_Enable(); 
	
	// Write memmory
	FLASH_UnlockBank1();
	FLASH_ErasePage(FLAG_ADDR);
	FLASH_ProgramWord(FLAG_ADDR,(u32)FLAG_UPDATED);
	FLASH_LockBank1();
	
	updateFW_control();
}

/**
 * Initializes the boards watchdog timer. If the behavior of the board is changed, this method may need to be
 * modified if the main control loop is changed.
 *
 * @param none
 * @retval none
 */
void Watchdog_Init(void) {
	/* Get the LSI frequency from TIM5 */
	LsiFreq = GetLSIFrequency();
	printf("LSI Frequency: %" PRIu32 "\n", LsiFreq);

	/* Enable write access to IWDG_PR and IWDG_RLR registers */
	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

	/* IWDG counter clock: LSI/32 */
	IWDG_SetPrescaler(IWDG_Prescaler_64);

	/* Set counter reload value to obtain 1s IWDG TimeOut.
	     IWDG counter clock Frequency = LsiFreq/32
	     Counter Reload Value = 250ms/IWDG counter clock period
	                          = 0.25s / (32/LsiFreq)
	                          = LsiFreq/(32 * 4)
	                          = LsiFreq/128
	 */
	IWDG_SetReload(LsiFreq/16);

	/* Reload IWDG counter */
	IWDG_ReloadCounter();

	/* Enable IWDG (the LSI oscillator will be enabled by hardware) */
	IWDG_Enable();
}

int LCDPANELProcessInit(void)
{
	rt_thread_t init_thread;
    rt_err_t result = RT_EOK;

	// 创建消息队列，分配队列存储空间
    result = rt_mq_init(&rx_mq, "mqt", &msg_pool[0], 32 - sizeof(void*), sizeof(msg_pool), RT_IPC_FLAG_FIFO);
   
    if (result != RT_EOK) 
    { 
        rt_kprintf("init message queue failed.\n"); 
        return result; 
    }

	IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);			// Enable write access to IWDG_PR and IWDG_RLR registers
	IWDG_SetPrescaler(IWDG_Prescaler_32);					// IWDG counter clock: 40KHz(LSI) / 32 = 1.25 KHz 
	IWDG_SetReload(1250);									// Set counter reload value to 1250 
	IWDG_ReloadCounter();									// Reload IWDG counter 
//	IWDG_Enable();											// Enable IWDG (the LSI oscillator will be enabled by hardware) 

	init_thread = rt_thread_create( "lcdpanel",
									LCDPANELProcess_thread_entry,
									RT_NULL,
									2048,10,10);

	if( init_thread != RT_NULL )
	{
		rt_thread_startup(init_thread);
	}

	return 0;
}

//==============================================================================
// 看門狗設定 : 用來當RESET 用
//==============================================================================
void IWDG_Config(unsigned char timeout)
{
  /* IWDG timeout equal to 250 ms (the timeout may varies due to LSI frequency
  dispersion) */
  /* Enable write access to IWDG_PR and IWDG_RLR registers */
  IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
  
  /* IWDG counter clock: LSI/32 */
  //IWDG_SetPrescaler(IWDG_Prescaler_32);
  /* IWDG counter clock: LSI/256 */
  IWDG_SetPrescaler(IWDG_Prescaler_256);
  
  /* Set counter reload value to obtain 250ms IWDG TimeOut.
  Counter Reload Value = 250ms/IWDG counter clock period
  = 250ms / (LSI/32)
  = 0.25s / (LsiFreq/32)
  = LsiFreq/(32 * 4)
  = LsiFreq/128
  */
  // IWDG_SetReload(LsiFreq/128);
  
  IWDG_SetReload(timeout);
  
  /* Reload IWDG counter */
  IWDG_ReloadCounter();
  
  /* Enable IWDG (the LSI oscillator will be enabled by hardware) */
  IWDG_Enable();
}

OSStatus PlatformWDGInitialize( uint32_t timeout_ms )
{
  plat_log_trace();
  OSStatus err = kNoErr;
// PLATFORM_TO_DO

  /* Get the LSI frequency:  TIM5 is used to measure the LSI frequency */
  LsiFreq = GetLSIFrequency();
   
  IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

  /* IWDG counter clock: LSI/32 */
  IWDG_SetPrescaler(IWDG_Prescaler_128);

  /* Set counter reload value to obtain 250ms IWDG TimeOut.
     Counter Reload Value = 250ms/IWDG counter clock period
                          = 250ms / (LSI/32)
                          = 0.25s / (LsiFreq/32)
                          = LsiFreq/(32 * 4)
                          = LsiFreq/128
   */
  IWDG_SetReload((uint16_t)(LsiFreq*timeout_ms/128000));

  /* Reload IWDG counter */
  IWDG_ReloadCounter();

  /* Enable IWDG (the LSI oscillator will be enabled by hardware) */
  IWDG_Enable();

  return err;
}

void WatchDogInit(void)
{    
  /* IWDG timeout equal to 250 ms (the timeout may varies due to LSI frequency
     dispersion) */
  /* Enable write access to IWDG_PR and IWDG_RLR registers */
  IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

  /* IWDG counter clock: LSI/32 */
    /*   prescaler            min/ms    max/ms
         4                        0.1             409.6
         8                        0.2             819.2
         16                      0.4             1638.4
         32                      0.8              3276.8
         64                      1.6              6553.5
         128                    3.2              13107.2
         256                    6.4              26214.4   
  */
  IWDG_SetPrescaler(IWDG_Prescaler_16);

  /* Set counter reload value to obtain 250ms IWDG TimeOut.
     Counter Reload Value = 250ms/IWDG counter clock period
                          = 250ms / (LSI/32)
                          = 0.25s / (LsiFreq/32)
                          = LsiFreq/(32 * 4)
                          = LsiFreq/128
   */
  IWDG_SetReload(0X4AAA);//(LsiFreq/128);

  /* Reload IWDG counter */
  IWDG_ReloadCounter();

  /* Enable IWDG (the LSI oscillator will be enabled by hardware) */
  IWDG_Enable();
}