C++ IS_DMA_ALL_PERIPH函数代码示例

/**
  * @brief  Checks whether the specified DMAy Streamx interrupt has occurred or not.
  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
  *          to 7 to select the DMA Stream.
  * @param  DMA_IT: specifies the DMA interrupt source to check.
  *          This parameter can be one of the following values:
  *            @arg DMA_IT_TCIFx:  Streamx transfer complete interrupt
  *            @arg DMA_IT_HTIFx:  Streamx half transfer complete interrupt
  *            @arg DMA_IT_TEIFx:  Streamx transfer error interrupt
  *            @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
  *            @arg DMA_IT_FEIFx:  Streamx FIFO error interrupt
  *         Where x can be 0 to 7 to select the DMA Stream.
  * @retval The new state of DMA_IT (SET or RESET).
  */
ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
{
  ITStatus bitstatus = RESET;
  DMA_TypeDef* DMAy;
  uint32_t tmpreg = 0, enablestatus = 0;

  /* Check the parameters */
  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
  assert_param(IS_DMA_GET_IT(DMA_IT));

  /* Determine the DMA to which belongs the stream */
  if (DMAy_Streamx < DMA2_Stream0)
  {
    /* DMAy_Streamx belongs to DMA1 */
    DMAy = DMA1;
  }
  else
  {
    /* DMAy_Streamx belongs to DMA2 */
    DMAy = DMA2;
  }

  /* Check if the interrupt enable bit is in the CR or FCR register */
  if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
  {
    /* Get the interrupt enable position mask in CR register */
    tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);

    /* Check the enable bit in CR register */
    enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
  }

/**
  * @brief  Clears the DMAy Streamx's pending flags.
  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
  *          to 7 to select the DMA Stream.
  * @param  DMA_FLAG: specifies the flag to clear.
  *          This parameter can be any combination of the following values:
  *            @arg DMA_FLAG_TCIFx:  Streamx transfer complete flag
  *            @arg DMA_FLAG_HTIFx:  Streamx half transfer complete flag
  *            @arg DMA_FLAG_TEIFx:  Streamx transfer error flag
  *            @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
  *            @arg DMA_FLAG_FEIFx:  Streamx FIFO error flag
  *         Where x can be 0 to 7 to select the DMA Stream.
  * @retval None
  */
void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
{
  DMA_TypeDef* DMAy;

  /* Check the parameters */
  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
  assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));

  /* Determine the DMA to which belongs the stream */
  if (DMAy_Streamx < DMA2_Stream0)
  {
    /* DMAy_Streamx belongs to DMA1 */
    DMAy = DMA1;
  }
  else
  {
    /* DMAy_Streamx belongs to DMA2 */
    DMAy = DMA2;
  }

  /* Check if LIFCR or HIFCR register is targeted */
  if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
  {
    /* Set DMAy HIFCR register clear flag bits */
    DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
  }
  else
  {
    /* Set DMAy LIFCR register clear flag bits */
    DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
  }
}

/**
  * @}
  */
void DMA_SetBuffer(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t BufAddr, uint16_t BufSize)
{
	assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
  	assert_param(IS_DMA_BUFFER_SIZE(BufSize));
	DMAy_Channelx->CMAR = BufAddr;
	DMAy_Channelx->CNDTR = BufSize;
}  

/**
  * @簡述  返回當前 DMA y 通道x 剩餘的待傳輸數據數目.
  * @參數  DMAy_Channelx: y 可以是1 或者2 ，DMA1 的x 可以是1 到7 和DMA2 的x 可以是1 到5 來選擇各通道.
  * @返回  當前 DMA y 通道x 傳輸中剩餘的數據單元的數量.
  */
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
{
  /* 檢查參數 */
  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
  /* 返回 DMA y 通道x 傳輸中剩餘的數據單元的數量 */
  return ((uint16_t)(DMAy_Channelx->CNDTR));
}

/**
  * @brief  Deinitializes the DMAy Channelx registers to their default reset
  *         values.
  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
  * @retval None
  */
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
{
	/* Check the parameters */
	assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));

	/* Disable the selected DMAy Channelx */
	DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);

	/* Reset DMAy Channelx control register */
	DMAy_Channelx->CCR  = 0;

	/* Reset DMAy Channelx remaining bytes register */
	DMAy_Channelx->CNDTR = 0;

	/* Reset DMAy Channelx peripheral address register */
	DMAy_Channelx->CPAR  = 0;

	/* Reset DMAy Channelx memory address register */
	DMAy_Channelx->CMAR = 0;

	if (DMAy_Channelx == DMA1_Channel1) {
		/* Reset interrupt pending bits for DMA1 Channel1 */
		DMA1->IFCR |= DMA1_Channel1_IT_Mask;
	} else if (DMAy_Channelx == DMA1_Channel2) {
		/* Reset interrupt pending bits for DMA1 Channel2 */
		DMA1->IFCR |= DMA1_Channel2_IT_Mask;
	} else if (DMAy_Channelx == DMA1_Channel3) {
		/* Reset interrupt pending bits for DMA1 Channel3 */
		DMA1->IFCR |= DMA1_Channel3_IT_Mask;
	} else if (DMAy_Channelx == DMA1_Channel4) {
		/* Reset interrupt pending bits for DMA1 Channel4 */
		DMA1->IFCR |= DMA1_Channel4_IT_Mask;
	} else if (DMAy_Channelx == DMA1_Channel5) {
		/* Reset interrupt pending bits for DMA1 Channel5 */
		DMA1->IFCR |= DMA1_Channel5_IT_Mask;
	} else if (DMAy_Channelx == DMA1_Channel6) {
		/* Reset interrupt pending bits for DMA1 Channel6 */
		DMA1->IFCR |= DMA1_Channel6_IT_Mask;
	} else if (DMAy_Channelx == DMA1_Channel7) {
		/* Reset interrupt pending bits for DMA1 Channel7 */
		DMA1->IFCR |= DMA1_Channel7_IT_Mask;
	} else if (DMAy_Channelx == DMA2_Channel1) {
		/* Reset interrupt pending bits for DMA2 Channel1 */
		DMA2->IFCR |= DMA2_Channel1_IT_Mask;
	} else if (DMAy_Channelx == DMA2_Channel2) {
		/* Reset interrupt pending bits for DMA2 Channel2 */
		DMA2->IFCR |= DMA2_Channel2_IT_Mask;
	} else if (DMAy_Channelx == DMA2_Channel3) {
		/* Reset interrupt pending bits for DMA2 Channel3 */
		DMA2->IFCR |= DMA2_Channel3_IT_Mask;
	} else if (DMAy_Channelx == DMA2_Channel4) {
		/* Reset interrupt pending bits for DMA2 Channel4 */
		DMA2->IFCR |= DMA2_Channel4_IT_Mask;
	} else {
		if (DMAy_Channelx == DMA2_Channel5) {
			/* Reset interrupt pending bits for DMA2 Channel5 */
			DMA2->IFCR |= DMA2_Channel5_IT_Mask;
		}
	}
}

/**
  * @brief  Returns the number of remaining data units in the current
  *         DMAy Channelx transfer.
  * @param  DMAy_Channelx: where y can be 1 to select the DMA and
  *         x can be 1 to 5 for DMA1 to select the DMA Channel.
  * @retval The number of remaining data units in the current DMAy Channelx
  *         transfer.
  */
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
{
    /* Check the parameters */
    assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
    /* Return the number of remaining data units for DMAy Channelx */
    return ((uint16_t)(DMAy_Channelx->CNDTR));
}

/**
  * @brief  Writes the number of data units to be transferred on the DMAy Streamx.
  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
  *          to 7 to select the DMA Stream.
  * @param  Counter: Number of data units to be transferred (from 0 to 65535)
  *          Number of data items depends only on the Peripheral data format.
  *
  * @note   If Peripheral data format is Bytes: number of data units is equal
  *         to total number of bytes to be transferred.
  *
  * @note   If Peripheral data format is Half-Word: number of data units is
  *         equal to total number of bytes to be transferred / 2.
  *
  * @note   If Peripheral data format is Word: number of data units is equal
  *         to total  number of bytes to be transferred / 4.
  *
  * @note   In Memory-to-Memory transfer mode, the memory buffer pointed by
  *         DMAy_SxPAR register is considered as Peripheral.
  *
  * @retval The number of remaining data units in the current DMAy Streamx transfer.
  */
void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter)
{
  /* Check the parameters */
  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));

  /* Write the number of data units to be transferred */
  DMAy_Streamx->NDTR = (uint16_t)Counter;
}

/**
  * @brief  Sets the number of data units in the current DMAy Channelx transfer.
  * @param  DMAy_Channelx: where y can be 1 to select the DMA and x can be
  *         1 to 5 for DMA1 to select the DMA Channel.
  * @param  DataNumber: The number of data units in the current DMAy Channelx
  *         transfer.
  * @note   This function can only be used when the DMAy_Channelx is disabled.
  * @retval None.
  */
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
{
    /* Check the parameters */
    assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));

    /*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
    /* Write to DMAy Channelx CNDTR */
    DMAy_Channelx->CNDTR = DataNumber;
}

/**
  * @brief  Initializes the DMAy Channelx according to the specified
  *         parameters in the DMA_InitStruct.
  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be 
  *         1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
  *         contains the configuration information for the specified DMA Channel.
  * @retval None
  */
void DMA_Init(DMA_Channel_TypeDef * DMAy_Channelx,
	      DMA_InitTypeDef * DMA_InitStruct)
{
	uint32_t tmpreg = 0;

	/* Check the parameters */
	assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
	assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
	assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
	assert_param(IS_DMA_PERIPHERAL_INC_STATE
		     (DMA_InitStruct->DMA_PeripheralInc));
	assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
	assert_param(IS_DMA_PERIPHERAL_DATA_SIZE
		     (DMA_InitStruct->DMA_PeripheralDataSize));
	assert_param(IS_DMA_MEMORY_DATA_SIZE
		     (DMA_InitStruct->DMA_MemoryDataSize));
	assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
	assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
	assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));

/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
	/* Get the DMAy_Channelx CCR value */
	tmpreg = DMAy_Channelx->CCR;
	/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
	tmpreg &= CCR_CLEAR_MASK;
	/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
	/* Set DIR bit according to DMA_DIR value */
	/* Set CIRC bit according to DMA_Mode value */
	/* Set PINC bit according to DMA_PeripheralInc value */
	/* Set MINC bit according to DMA_MemoryInc value */
	/* Set PSIZE bits according to DMA_PeripheralDataSize value */
	/* Set MSIZE bits according to DMA_MemoryDataSize value */
	/* Set PL bits according to DMA_Priority value */
	/* Set the MEM2MEM bit according to DMA_M2M value */
	tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
	    DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
	    DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->
	    DMA_MemoryDataSize | DMA_InitStruct->DMA_Priority | DMA_InitStruct->
	    DMA_M2M;

	/* Write to DMAy Channelx CCR */
	DMAy_Channelx->CCR = tmpreg;

/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
	/* Write to DMAy Channelx CNDTR */
	DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;

/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
	/* Write to DMAy Channelx CPAR */
	DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;

/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
	/* Write to DMAy Channelx CMAR */
	DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
}

/**
  * @brief  Returns the current DMAy Streamx FIFO filled level.
  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
  *         to 7 to select the DMA Stream.
  * @retval The FIFO filling state.
  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
  *                                               and not empty.
  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
  *           - DMA_FIFOStatus_Empty: when FIFO is empty
  *           - DMA_FIFOStatus_Full: when FIFO is full
  */
uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx)
{
  uint32_t tmpreg = 0;

  /* Check the parameters */
  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));

  /* Get the FIFO level bits */
  tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS));

  return tmpreg;
}

/**
  * @brief  Enables or disables the specified DMAy Channelx.
  * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
  *   DMA Channel.
  * @param NewState: new state of the DMAy Channelx.
  *   This parameter can be: ENABLE or DISABLE.
  * @retval : None
  */
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) {
	/* Check the parameters */
	assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
	assert_param(IS_FUNCTIONAL_STATE(NewState));
	if(NewState != DISABLE) {
		/* Enable the selected DMAy Channelx */
		DMAy_Channelx->CCR |= CCR_ENABLE_Set;
	} else {
		/* Disable the selected DMAy Channelx */
		DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
	}
}

/**
  * @brief  Checks whether the specified DMAy Streamx flag is set or not.
  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
  *          to 7 to select the DMA Stream.
  * @param  DMA_FLAG: specifies the flag to check.
  *          This parameter can be one of the following values:
  *            @arg DMA_FLAG_TCIFx:  Streamx transfer complete flag
  *            @arg DMA_FLAG_HTIFx:  Streamx half transfer complete flag
  *            @arg DMA_FLAG_TEIFx:  Streamx transfer error flag
  *            @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
  *            @arg DMA_FLAG_FEIFx:  Streamx FIFO error flag
  *         Where x can be 0 to 7 to select the DMA Stream.
  * @retval The new state of DMA_FLAG (SET or RESET).
  */
FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
{
  FlagStatus bitstatus = RESET;
  DMA_TypeDef* DMAy;
  uint32_t tmpreg = 0;

  /* Check the parameters */
  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
  assert_param(IS_DMA_GET_FLAG(DMA_FLAG));

  /* Determine the DMA to which belongs the stream */
  if (DMAy_Streamx < DMA2_Stream0)
  {
    /* DMAy_Streamx belongs to DMA1 */
    DMAy = DMA1;
  }
  else
  {
    /* DMAy_Streamx belongs to DMA2 */
    DMAy = DMA2;
  }

  /* Check if the flag is in HISR or LISR */
  if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
  {
    /* Get DMAy HISR register value */
    tmpreg = DMAy->HISR;
  }
  else
  {
    /* Get DMAy LISR register value */
    tmpreg = DMAy->LISR;
  }

  /* Mask the reserved bits */
  tmpreg &= (uint32_t)RESERVED_MASK;

  /* Check the status of the specified DMA flag */
  if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
  {
    /* DMA_FLAG is set */
    bitstatus = SET;
  }
  else
  {
    /* DMA_FLAG is reset */
    bitstatus = RESET;
  }

  /* Return the DMA_FLAG status */
  return  bitstatus;
}

/**
  * @brief  Enables or disables the specified DMAy Channelx interrupts.
  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
  * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
  *   or disabled.
  *   This parameter can be any combination of the following values:
  *     @arg DMA_IT_TC:  Transfer complete interrupt mask
  *     @arg DMA_IT_HT:  Half transfer interrupt mask
  *     @arg DMA_IT_TE:  Transfer error interrupt mask
  * @param  NewState: new state of the specified DMA interrupts.
  *   This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) {
    /* Check the parameters */
    assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
    assert_param(IS_DMA_CONFIG_IT(DMA_IT));
    assert_param(IS_FUNCTIONAL_STATE(NewState));
    if(NewState != DISABLE) {
        /* Enable the selected DMA interrupts */
        DMAy_Channelx->CCR |= DMA_IT;
    } else {
        /* Disable the selected DMA interrupts */
        DMAy_Channelx->CCR &= ~DMA_IT;
    }
}

/**
  * @簡述  使能或失能指定的 DMA y 通道 x 中斷.
  * @參數  DMAy_Channelx: y 可以是1 或者2 ，DMA1 的x 可以是1 到7 和DMA2 的x 可以是1 到5 來選擇各通道.
  * @參數  DMA_IT: 指定 DMA 的中斷. 
  *            這個參數可以是下面值的任意組合:
  *            DMA_IT_TC:  傳輸完成中斷屏蔽
  *            DMA_IT_HT:  傳輸過半中斷屏蔽
  *            DMA_IT_TE:  傳輸錯誤中斷屏蔽
  * @參數  NewState: 指定的 DMA 中斷的新狀態.
  *                  這個參數可以是: ENABLE 或 DISABLE.
  * @返回  沒有
  */
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
{
  /* 檢查參數 */
  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
  assert_param(IS_DMA_CONFIG_IT(DMA_IT));
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  if (NewState != DISABLE)
  {
    /* 使能指定的 DMA 中斷 */
    DMAy_Channelx->CCR |= DMA_IT;
  }
  else
  {
    /* 失能指定的 DMA 中斷 */
    DMAy_Channelx->CCR &= ~DMA_IT;
  }
}

/**
  * @簡述  使能或失能指定的 DMA y 通道 x.
  * @參數  DMAy_Channelx: y 可以是1 或者2 ，DMA1 的x 可以是1 到7 和DMA2 的x 可以是1 到5 來選擇各通道.
  * @參數  NewState: DMA y 通道x 的新狀態. 
  *                  這個參數可以是: ENABLE 或 DISABLE.
  * @返回  沒有
  */
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
{
  /* 檢查參數 */
  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  {
    /* 使能指定的 DMA y 通道 x */
    DMAy_Channelx->CCR |= CCR_ENABLE_Set;
  }
  else
  {
    /* 失能指定的 DMA y 通道 x */
    DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
  }
}