本文整理汇总了C++中IRQ_CONNECT函数的典型用法代码示例。如果您正苦于以下问题:C++ IRQ_CONNECT函数的具体用法?C++ IRQ_CONNECT怎么用?C++ IRQ_CONNECT使用的例子?那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了IRQ_CONNECT函数的15个代码示例,这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞,您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: spi_qmsi_init
static int spi_qmsi_init(struct device *dev)
{
struct spi_qmsi_config *spi_config = dev->config->config_info;
struct spi_qmsi_runtime *context = dev->driver_data;
dev->driver_api = &spi_qmsi_api;
switch (spi_config->spi) {
case QM_SPI_MST_0:
IRQ_CONNECT(CONFIG_SPI_QMSI_PORT_0_IRQ,
CONFIG_SPI_QMSI_PORT_0_PRI, qm_spi_master_0_isr,
0, IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(CONFIG_SPI_QMSI_PORT_0_IRQ);
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M0_REGISTER);
QM_SCSS_INT->int_spi_mst_0_mask &= ~BIT(0);
break;
case QM_SPI_MST_1:
IRQ_CONNECT(CONFIG_SPI_QMSI_PORT_1_IRQ,
CONFIG_SPI_QMSI_PORT_1_PRI, qm_spi_master_1_isr,
0, IOAPIC_LEVEL | IOAPIC_HIGH);
irq_enable(CONFIG_SPI_QMSI_PORT_1_IRQ);
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M1_REGISTER);
QM_SCSS_INT->int_spi_mst_1_mask &= ~BIT(0);
break;
default:
return DEV_FAIL;
}
context->gpio_cs = gpio_cs_init(spi_config);
device_sync_call_init(&context->sync);
return DEV_OK;
}
示例2: HwiP_create
HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, HwiP_Params *params)
{
HwiP_Handle handle = 0;
uint32_t priority = ~0;
uintptr_t arg = 0;
if (params) {
priority = params->priority;
arg = params->arg;
}
/*
* SimpleLink only uses the NWPIC, UDMA, UDMAERR and LSPI interrupts:
*/
__ASSERT(INT_NWPIC == interruptNum || INT_UDMA == interruptNum ||
INT_UDMAERR == interruptNum || INT_LSPI == interruptNum,
"Unexpected interruptNum: %d\r\n",
interruptNum);
/*
* Priority expected is either:
* INT_PRIORITY_LVL_1,
* or ~0 or 255 (meaning lowest priority)
* ~0 and 255 are meant to be the same as INT_PRIORITY_LVL_7.
* For ~0 or 255, we want 7; but Zephyr IRQ_CONNECT adds +1,
* so we pass 6 for those TI drivers passing prio = ~0.
*/
__ASSERT((INT_PRIORITY_LVL_1 == priority) ||
(0xff == (priority & 0xff)),
"Expected priority: 0x%x or 0x%x, got: 0x%x\r\n",
INT_PRIORITY_LVL_1, 0xff, priority);
switch(interruptNum) {
case INT_UDMA:
sl_UDMA_cb.cb = hwiFxn;
sl_UDMA_cb.arg = arg;
IRQ_CONNECT(EXCEPTION_UDMA, 6, sl_isr, &sl_UDMA_cb, 0);
break;
case INT_UDMAERR:
sl_UDMAERR_cb.cb = hwiFxn;
sl_UDMAERR_cb.arg = arg;
IRQ_CONNECT(EXCEPTION_UDMAERR, 6, sl_isr, &sl_UDMAERR_cb, 0);
break;
case INT_NWPIC:
sl_NWPIC_cb.cb = hwiFxn;
sl_NWPIC_cb.arg = arg;
IRQ_CONNECT(EXCEPTION_NWPIC, 1, sl_isr, &sl_NWPIC_cb, 0);
break;
case INT_LSPI:
sl_LSPI_cb.cb = hwiFxn;
sl_LSPI_cb.arg = arg;
IRQ_CONNECT(EXCEPTION_LSPI, 6, sl_isr, &sl_LSPI_cb, 0);
break;
default:
return(handle);
}
irq_enable(interruptNum - 16);
return (HwiP_Handle)interruptNum;
}
示例3: i2c_stm32_irq_config_func_4
static void i2c_stm32_irq_config_func_4(struct device *dev)
{
IRQ_CONNECT(DT_I2C_4_EVENT_IRQ, DT_I2C_4_EVENT_IRQ_PRI,
stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_4), 0);
irq_enable(DT_I2C_4_EVENT_IRQ);
IRQ_CONNECT(DT_I2C_4_ERROR_IRQ, DT_I2C_4_ERROR_IRQ_PRI,
stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_4), 0);
irq_enable(DT_I2C_4_ERROR_IRQ);
}
示例4: i2c_qmsi_init
static int i2c_qmsi_init(struct device *dev)
{
struct i2c_qmsi_driver_data *driver_data = GET_DRIVER_DATA(dev);
const struct i2c_qmsi_config_info *config = dev->config->config_info;
qm_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
u32_t bitrate_cfg;
int err;
k_sem_init(&driver_data->device_sync_sem, 0, UINT_MAX);
k_sem_init(&driver_data->sem, 1, UINT_MAX);
switch (instance) {
case QM_I2C_0:
/* Register interrupt handler, unmask IRQ and route it
* to Lakemont core.
*/
IRQ_CONNECT(CONFIG_I2C_0_IRQ,
CONFIG_I2C_0_IRQ_PRI, qm_i2c_0_irq_isr, NULL,
CONFIG_I2C_0_IRQ_FLAGS);
irq_enable(CONFIG_I2C_0_IRQ);
QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->i2c_master_0_int_mask);
break;
#ifdef CONFIG_I2C_1
case QM_I2C_1:
IRQ_CONNECT(CONFIG_I2C_1_IRQ,
CONFIG_I2C_1_IRQ_PRI, qm_i2c_1_irq_isr, NULL,
CONFIG_I2C_1_IRQ_FLAGS);
irq_enable(CONFIG_I2C_1_IRQ);
QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->i2c_master_1_int_mask);
break;
#endif /* CONFIG_I2C_1 */
default:
return -EIO;
}
clk_periph_enable(config->clock_gate);
bitrate_cfg = _i2c_map_dt_bitrate(config->bitrate);
err = i2c_qmsi_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (err < 0) {
return err;
}
dev->driver_api = &api;
i2c_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
return 0;
}
示例5: dma_qmsi_config
static void dma_qmsi_config(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_0), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_0, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_0));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_0_mask);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_1), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_1, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_1));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_1_mask);
#if (CONFIG_SOC_QUARK_SE_C1000)
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_2), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_2, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_2));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_2_mask);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_3), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_3, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_3));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_3_mask);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_4), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_4, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_4));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_4_mask);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_5), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_5, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_5));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_5_mask);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_6), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_6, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_6));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_6_mask);
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_7), CONFIG_DMA_0_IRQ_PRI,
qm_dma_0_isr_7, DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_INT_7));
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->dma_0_int_7_mask);
#endif /* CONFIG_SOC_QUARK_SE_C1000 */
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_DMA_0_ERROR_INT),
CONFIG_DMA_0_IRQ_PRI, qm_dma_0_error_isr,
DEVICE_GET(dma_qmsi), 0);
irq_enable(IRQ_GET_NUMBER(QM_IRQ_DMA_0_ERROR_INT));
#if (QM_LAKEMONT)
QM_INTERRUPT_ROUTER->dma_0_error_int_mask &= ~QM_IR_DMA_ERROR_HOST_MASK;
#elif (QM_SENSOR)
QM_INTERRUPT_ROUTER->dma_0_error_int_mask &= ~QM_IR_DMA_ERROR_SS_MASK;
#endif
}
示例6: usart_gecko_config_func_3
static void usart_gecko_config_func_3(struct device *dev)
{
IRQ_CONNECT(DT_SILABS_GECKO_USART_3_IRQ_RX,
DT_SILABS_GECKO_USART_3_IRQ_RX_PRIORITY,
uart_gecko_isr, DEVICE_GET(usart_3), 0);
IRQ_CONNECT(DT_SILABS_GECKO_USART_3_IRQ_TX,
DT_SILABS_GECKO_USART_3_IRQ_TX_PRIORITY,
uart_gecko_isr, DEVICE_GET(usart_3), 0);
irq_enable(DT_SILABS_GECKO_USART_3_IRQ_RX);
irq_enable(DT_SILABS_GECKO_USART_3_IRQ_TX);
}
示例7: mcux_igpio_5_init
static int mcux_igpio_5_init(struct device *dev)
{
IRQ_CONNECT(DT_MCUX_IGPIO_5_IRQ_0, DT_MCUX_IGPIO_5_IRQ_0_PRI,
mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_5), 0);
irq_enable(DT_MCUX_IGPIO_5_IRQ_0);
IRQ_CONNECT(DT_MCUX_IGPIO_5_IRQ_1, DT_MCUX_IGPIO_5_IRQ_1_PRI,
mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_5), 0);
irq_enable(DT_MCUX_IGPIO_5_IRQ_1);
return 0;
}
示例8: uart_mcux_config_func_5
static void uart_mcux_config_func_5(struct device *dev)
{
IRQ_CONNECT(CONFIG_UART_MCUX_5_IRQ_STATUS,
CONFIG_UART_MCUX_5_IRQ_STATUS_PRI,
uart_mcux_isr, DEVICE_GET(uart_5), 0);
irq_enable(CONFIG_UART_MCUX_5_IRQ_STATUS);
IRQ_CONNECT(CONFIG_UART_MCUX_5_IRQ_ERROR,
CONFIG_UART_MCUX_5_IRQ_ERROR_PRI,
uart_mcux_isr, DEVICE_GET(uart_5), 0);
irq_enable(CONFIG_UART_MCUX_5_IRQ_ERROR);
}
示例9: uart_mcux_config_func_5
static void uart_mcux_config_func_5(struct device *dev)
{
IRQ_CONNECT(IRQ_UART5_STATUS, CONFIG_UART_MCUX_5_IRQ_PRI,
uart_mcux_isr, DEVICE_GET(uart_5), 0);
irq_enable(IRQ_UART5_STATUS);
#ifdef IRQ_UART5_ERROR
IRQ_CONNECT(IRQ_UART5_ERROR, CONFIG_UART_MCUX_5_IRQ_PRI,
uart_mcux_isr, DEVICE_GET(uart_5), 0);
irq_enable(IRQ_UART5_ERROR);
#endif
}
示例10: mcux_igpio_4_init
static int mcux_igpio_4_init(struct device *dev)
{
IRQ_CONNECT(CONFIG_MCUX_IGPIO_4_IRQ_0, CONFIG_MCUX_IGPIO_4_IRQ_0_PRI,
mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_4), 0);
irq_enable(CONFIG_MCUX_IGPIO_4_IRQ_0);
IRQ_CONNECT(CONFIG_MCUX_IGPIO_4_IRQ_1, CONFIG_MCUX_IGPIO_4_IRQ_1_PRI,
mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_4), 0);
irq_enable(CONFIG_MCUX_IGPIO_4_IRQ_1);
return 0;
}
示例11: timer_cmsdk_apb_config_1
static void timer_cmsdk_apb_config_1(struct device *dev)
{
IRQ_CONNECT(CMSDK_APB_TIMER_1_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_1_IRQ_PRI,
timer_tmr_cmsdk_apb_isr,
DEVICE_GET(timer_tmr_cmsdk_apb_0), 0);
irq_enable(CMSDK_APB_TIMER_1_IRQ);
}
示例12: nrf5_config
static void nrf5_config(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(NRF5_IRQ_RADIO_IRQn, 0, nrf5_radio_irq, NULL, 0);
irq_enable(NRF5_IRQ_RADIO_IRQn);
}
示例13: i2c_mcux_config_func_1
static void i2c_mcux_config_func_1(struct device *dev)
{
IRQ_CONNECT(CONFIG_I2C_MCUX_1_IRQ, CONFIG_I2C_MCUX_1_IRQ_PRI,
i2c_mcux_isr, DEVICE_GET(i2c_mcux_1), 0);
irq_enable(CONFIG_I2C_MCUX_1_IRQ);
}
示例14: mcux_adc16_config_func_1
static void mcux_adc16_config_func_1(struct device *dev)
{
IRQ_CONNECT(CONFIG_ADC_1_IRQ, CONFIG_ADC_1_IRQ_PRI,
mcux_adc16_isr, DEVICE_GET(mcux_adc16_1), 0);
irq_enable(CONFIG_ADC_1_IRQ);
}
示例15: z_clock_driver_init
int z_clock_driver_init(struct device *device)
{
extern int z_clock_hw_cycles_per_sec;
u32_t hz;
IRQ_CONNECT(CONFIG_HPET_TIMER_IRQ, CONFIG_HPET_TIMER_IRQ_PRIORITY,
hpet_isr, 0, 0);
set_timer0_irq(CONFIG_HPET_TIMER_IRQ);
irq_enable(CONFIG_HPET_TIMER_IRQ);
/* CLK_PERIOD_REG is in femtoseconds (1e-15 sec) */
hz = (u32_t)(1000000000000000ull / CLK_PERIOD_REG);
z_clock_hw_cycles_per_sec = hz;
cyc_per_tick = hz / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
/* Note: we set the legacy routing bit, because otherwise
* nothing in Zephyr disables the PIT which then fires
* interrupts into the same IRQ. But that means we're then
* forced to use IRQ2 contra the way the kconfig IRQ selection
* is supposed to work. Should fix this.
*/
GENERAL_CONF_REG |= GCONF_LR | GCONF_ENABLE;
TIMER0_CONF_REG &= ~TCONF_PERIODIC;
TIMER0_CONF_REG |= TCONF_MODE32;
max_ticks = (0x7fffffff - cyc_per_tick) / cyc_per_tick;
last_count = MAIN_COUNTER_REG;
TIMER0_CONF_REG |= TCONF_INT_ENABLE;
TIMER0_COMPARATOR_REG = MAIN_COUNTER_REG + cyc_per_tick;
return 0;
}