本文整理汇总了C++中HAL_WRITE_UINT32函数的典型用法代码示例。如果您正苦于以下问题：C++ HAL_WRITE_UINT32函数的具体用法？C++ HAL_WRITE_UINT32怎么用？C++ HAL_WRITE_UINT32使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。
在下文中一共展示了HAL_WRITE_UINT32函数的15个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于系统推荐出更棒的C++代码示例。
示例1: qspi_xc7z_fill_tx_fifo
/**
*
* QSPI bus fill TX FIFO function.
*
* @param qspi_bus - QSPI bus handle
*
* @return none
*
*****************************************************************************/
static void
qspi_xc7z_fill_tx_fifo(cyg_qspi_xc7z_bus_t *qspi_bus, int max)
{
entry_debug();
cyg_uint32 data = 0;
cyg_uint32 val = 0;
int count = 0;
HAL_READ_UINT32(qspi_bus->base + XQSPIPS_SR_OFFSET, val);
while ((!(val & XQSPIPS_IXR_TXFULL_MASK)) && (qspi_bus->us_tx_bytes > 0) && (count < max)) {
count++;
if (qspi_bus->us_tx_bytes < 4) {
int tp = qspi_bus->us_tx_bytes;
qspi_xc7z_copy_write_data(qspi_bus, &data, qspi_bus->us_tx_bytes);
if (tp == 1) {
HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_TXD_01_OFFSET, data);
} else if (tp == 2) {
HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_TXD_10_OFFSET, data);
} else {
HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_TXD_11_OFFSET, data);
}
} else {
qspi_xc7z_copy_write_data(qspi_bus, &data, 4);
HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_TXD_00_OFFSET, data);
}
HAL_READ_UINT32(qspi_bus->base + XQSPIPS_SR_OFFSET, val);
}
}示例2: mpc5xxx_i2c_isr
cyg_uint32
mpc5xxx_i2c_isr(cyg_vector_t vector, cyg_addrword_t data)
{
cyg_uint32 dr;
HAL_WRITE_UINT32(I2C_0_STATUS_REG, 0x00000000); // Clear the status register of all interrupts
if (CYG_MPC5XXX_I2C_XFER_MODE_STARTRX == global_i2c_mode) // Sent the address and now read the dummy byte
{
HAL_WRITE_UINT32(I2C_0_CONTROL_REG, I2C_BEGIN_RX);
HAL_READ_UINT32(I2C_0_DATA_REG,dr); // Read the dummy byte to initiate next transfer
global_i2c_mode = CYG_MPC5XXX_I2C_XFER_MODE_RX1; // Change transfer mode to receive first byte
resetHigh(); // Set reset pin to High that drains the capacitor to 0V, IS THIS where it goes?
}
else if (CYG_MPC5XXX_I2C_XFER_MODE_RX1 == global_i2c_mode) // Transmit mode to read first data byte
{
HAL_WRITE_UINT32(I2C_0_CONTROL_REG, I2C_SEND_TXAK);
HAL_READ_UINT32(I2C_0_DATA_REG, byte0);
byte0 >>= 16;
global_i2c_mode = CYG_MPC5XXX_I2C_XFER_MODE_RX2; // Change transfer mode to receive second byte
resetLow();
}示例3: hasp_mpc5xxx_i2c_init
void
hasp_mpc5xxx_i2c_init()
{
initReset(); // initialise the reset pin
resetHigh();
cyg_drv_mutex_init(&i2c_lock);
cyg_drv_cond_init(&i2c_wait, &i2c_lock);
cyg_drv_interrupt_create(i2c_intr_vector,
0,
(cyg_addrword_t) 0,
&mpc5xxx_i2c_isr,
&mpc5xxx_i2c_dsr,
&(i2c_interrupt_handle),
&(i2c_interrupt_data));
cyg_drv_interrupt_attach(i2c_interrupt_handle);
HAL_WRITE_UINT32(I2C_0_FDR_REG, 0x89000000); // Set clock to 100MHz / 352
HAL_WRITE_UINT32(I2C_0_ADDRESS_REG, 0x00000000); // Set MPC5xxx slave address, not useful to us
HAL_WRITE_UINT32(I2C_0_CONTROL_REG, I2C_ENABLE); // Enable the I2C device but do not start any transfers and leave interrupts disabled.
HAL_WRITE_UINT32(I2C_0_STATUS_REG, 0x00000000); // Clear any pending conditions including interrupts.
HAL_INTERRUPT_UNMASK(i2c_intr_vector); // Interrupts can now be safely unmasked
i2c_flag = 0;
resetLow();
}示例4: smdk2410_serial_config_port
// Internal function to actually configure the hardware to desired baud rate, etc.
static bool
smdk2410_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
{
smdk2410_serial_info *smdk2410_chan = (smdk2410_serial_info *)chan->dev_priv;
CYG_ADDRWORD base = smdk2410_chan->base;
unsigned short baud_divisor = select_baud[new_config->baud];
cyg_uint32 _lcr;
if (baud_divisor == 0) return false;
if (init) {
//UART FIFO control register
HAL_WRITE_UINT32(base+OFS_UFCON, (3<<6) | (3<<4) | (1<<2) | (1<<1) | (1<<0));
//UART modem control register
HAL_WRITE_UINT32(base+OFS_UMCON, 0);
}
_lcr = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
select_stop_bits[new_config->stop] |
select_parity[new_config->parity];
HAL_WRITE_UINT32(base+OFS_ULCON, _lcr);
//UART control register, Enable Rx Timeout Int
HAL_WRITE_UINT32(base+OFS_UCON, 0x085);
if (new_config != &chan->config) {
chan->config = *new_config;
}
return true;
}示例5: hal_delay_us
void hal_delay_us(cyg_int32 usecs)
{
CYG_ADDRESS pit_base = MAC7100_PIT_BASE;
cyg_uint32 pit_en;
// Clear flag
HAL_WRITE_UINT32(MAC7100_PIT_FLG(pit_base),
MAC7100_PIT_FLAG_TIF(CYGNUM_PIT_CHAN_US));
// Set timer
HAL_WRITE_UINT32(MAC7100_PIT_TLVAL(pit_base, CYGNUM_PIT_CHAN_US),
usecs*CYGNUM_1_US-1);
HAL_READ_UINT32(MAC7100_PIT_EN(pit_base), pit_en);
pit_en |= MAC7100_PIT_EN_PEN(CYGNUM_PIT_CHAN_US);
HAL_WRITE_UINT32(MAC7100_PIT_EN(pit_base), pit_en);
do {
HAL_READ_UINT32(MAC7100_PIT_FLG(pit_base), pit_en);
} while (!(pit_en & MAC7100_PIT_FLAG_TIF(CYGNUM_PIT_CHAN_US)));
// Disable counter
HAL_READ_UINT32(MAC7100_PIT_EN(pit_base), pit_en);
pit_en &= ~MAC7100_PIT_EN_PEN(CYGNUM_PIT_CHAN_US);
HAL_WRITE_UINT32(MAC7100_PIT_EN(pit_base), pit_en);
}示例6: hal_clock_initialize
void hal_clock_initialize(cyg_uint32 period)
{
CYG_ADDRESS pit_base = MAC7100_PIT_BASE;
cyg_uint32 pit_en;
CYG_ASSERT(period < 0x10000, "Invalid clock period");
// Disable counter
HAL_READ_UINT32(MAC7100_PIT_EN(pit_base), pit_en);
pit_en &= ~MAC7100_PIT_EN_PEN(CYGNUM_PIT_CHAN_CLOCK);
HAL_WRITE_UINT32(MAC7100_PIT_EN(pit_base), pit_en);
// Set registers
_period=period;
HAL_WRITE_UINT32(MAC7100_PIT_TLVAL(pit_base, CYGNUM_PIT_CHAN_CLOCK),
period);
// Start timer
pit_en |= MAC7100_PIT_EN_PEN(CYGNUM_PIT_CHAN_CLOCK);
HAL_WRITE_UINT32(MAC7100_PIT_EN(pit_base), pit_en);
// Enable timer interrupt
HAL_READ_UINT32(MAC7100_PIT_INTEN(pit_base), pit_en);
pit_en |= MAC7100_PIT_EN_PEN(CYGNUM_PIT_CHAN_CLOCK);
HAL_WRITE_UINT32(MAC7100_PIT_INTEN(pit_base), pit_en);
HAL_READ_UINT32(MAC7100_PIT_INTSEL(pit_base), pit_en);
pit_en |= MAC7100_PIT_EN_PEN(CYGNUM_PIT_CHAN_CLOCK);
HAL_WRITE_UINT32(MAC7100_PIT_INTSEL(pit_base), pit_en);
}示例7: init_timer
void init_timer( cyg_uint32 base, cyg_uint32 interval )
{
cyg_uint32 period = hal_stm32_pclk1;
if( base == CYGHWR_HAL_STM32_TIM1 || base == CYGHWR_HAL_STM32_TIM8 )
{
period = hal_stm32_pclk2;
if( CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV != 1 )
period *= 2;
}
else
{
if( CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV != 1 )
period *= 2;
}
period = period / 1000000;
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_PSC, period-1 );
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_CR2, 0 );
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_DIER, CYGHWR_HAL_STM32_TIM_DIER_UIE );
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_ARR, interval );
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_CR1, CYGHWR_HAL_STM32_TIM_CR1_CEN);
}示例8: hal_clock_initialize
void hal_clock_initialize(cyg_uint32 period)
{
cyg_uint32 tmod;
// Disable timer 0
HAL_READ_UINT32(E7T_TMOD, tmod);
tmod &= ~(E7T_TMOD_TE0);
HAL_WRITE_UINT32(E7T_TMOD, 0);
tmod &= ~(E7T_TMOD_TMD0 | E7T_TMOD_TCLR0);
tmod |= E7T_TMOD_TE0;
// Set counter
HAL_WRITE_UINT32(E7T_TDATA0, period);
// And enable timer
HAL_WRITE_UINT32(E7T_TMOD, tmod);
_period = period;
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_EXT0,
99, // Priority
0, // Data item passed to interrupt handler
e7t_abort_isr,
0,
&abort_interrupt_handle,
&abort_interrupt);
cyg_drv_interrupt_attach(abort_interrupt_handle);
cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT0);
#endif
}示例9: phy_read_register
static cyg_uint32 phy_read_register(cyg_uint32 address, cyg_uint8 reg)
{
cyg_uint32 retVal;
cyg_uint32 miimcom, miimind;
int i;
HAL_WRITE_UINT32( CYGARC_IMM_BASE + CYGARC_REG_IMM_TSEC1_MIIMADD , ((((cyg_uint32)address) << 8) | reg));
HAL_READ_UINT32( CYGARC_IMM_BASE + CYGARC_REG_IMM_TSEC1_MIIMCOM , miimcom);
miimcom &= ~MIIMCOM_READ;
HAL_WRITE_UINT32( CYGARC_IMM_BASE + CYGARC_REG_IMM_TSEC1_MIIMCOM , miimcom);
miimcom |= MIIMCOM_READ;
HAL_WRITE_UINT32( CYGARC_IMM_BASE + CYGARC_REG_IMM_TSEC1_MIIMCOM , miimcom);
HAL_READ_UINT32( CYGARC_IMM_BASE + CYGARC_REG_IMM_TSEC1_MIIMIND , miimind);
i = 0;
while ((miimind & MIIMIND_BUSY) == MIIMIND_BUSY && i++ < 500)
{
// os_printf(".");
HAL_DELAY_US(10000);
HAL_READ_UINT32( CYGARC_IMM_BASE + CYGARC_REG_IMM_TSEC1_MIIMIND , miimind);
}
//status register
HAL_READ_UINT32( CYGARC_IMM_BASE + CYGARC_REG_IMM_TSEC1_MIIMSTAT , retVal);
// phy_state = qi->regs->miimstat;
HAL_READ_UINT32( CYGARC_IMM_BASE + CYGARC_REG_IMM_TSEC1_MIIMCOM , miimcom);
miimcom &= ~MIIMCOM_READ;
HAL_WRITE_UINT32( CYGARC_IMM_BASE + CYGARC_REG_IMM_TSEC1_MIIMCOM , miimcom);
return retVal;
}示例10: _mb93091_pci_cfg_write_uint32
externC void
_mb93091_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val)
{
cyg_uint32 cfg_addr, addr, status;
if (!_mb93091_has_vdk)
return;
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
// PCI bridge
addr = _MB93091_PCI_CONFIG + (offset << 1);
} else {
cfg_addr = _cfg_addr(bus, devfn, offset);
HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, cfg_addr);
addr = _MB93091_PCI_CONFIG_DATA;
}
HAL_WRITE_UINT32(addr, cfg_val);
HAL_READ_UINT16(_MB93091_PCI_STAT_CMD, status);
if (status & _MB93091_PCI_STAT_ERROR_MASK) {
// Cycle failed - clean up and get out
HAL_WRITE_UINT16(_MB93091_PCI_STAT_CMD, status & _MB93091_PCI_STAT_ERROR_MASK);
}
HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, 0);
}示例11: _mb93091_pci_cfg_read_uint16
externC cyg_uint16
_mb93091_pci_cfg_read_uint16(int bus, int devfn, int offset)
{
cyg_uint32 cfg_addr, addr, status;
cyg_uint16 cfg_val = (cyg_uint16)0xFFFF;
if (!_mb93091_has_vdk)
return cfg_val;
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
#endif // CYGPKG_IO_PCI_DEBUG
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
// PCI bridge
addr = _MB93091_PCI_CONFIG + ((offset << 1) ^ 0x02);
} else {
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x02);
HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, cfg_addr);
addr = _MB93091_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x02);
}
HAL_READ_UINT16(addr, cfg_val);
HAL_READ_UINT16(_MB93091_PCI_STAT_CMD, status);
if (status & _MB93091_PCI_STAT_ERROR_MASK) {
// Cycle failed - clean up and get out
cfg_val = (cyg_uint16)0xFFFF;
HAL_WRITE_UINT16(_MB93091_PCI_STAT_CMD, status & _MB93091_PCI_STAT_ERROR_MASK);
}
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%x\n", cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, 0);
return cfg_val;
}示例12: hal_diag_led
void hal_diag_led(int x)
{
HAL_WRITE_UINT32(HAL_DISPLAY_LEDBAR, x);
#if !defined(CYG_KERNEL_DIAG_LCD)
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIWORD, x);
#endif
}示例13: hal_stm32_serial_init_channel
static void
hal_stm32_serial_init_channel(void* __ch_data)
{
channel_data_t *chan = (channel_data_t*)__ch_data;
CYG_ADDRESS base = chan->base;
cyg_uint32 cr1, cr2;
// Enable the PIO lines for the serial channel
CYGHWR_HAL_STM32_GPIO_SET( chan->rxpin );
CYGHWR_HAL_STM32_GPIO_SET( chan->txpin );
cr2 = CYGHWR_HAL_STM32_UART_CR2_STOP_1;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR2, cr2 );
cr1 = CYGHWR_HAL_STM32_UART_CR1_M_8;
cr1 |= CYGHWR_HAL_STM32_UART_CR1_TE | CYGHWR_HAL_STM32_UART_CR1_RE;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 );
//while(1)HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_GPIOC+CYGHWR_HAL_STM32_GPIO_BSRR,0x000040);
// Set up Baud rate
chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD;
// while(1)HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_GPIOC+CYGHWR_HAL_STM32_GPIO_BSRR,0x000040);
hal_stm32_uart_setbaud( base, chan->baud_rate );
// Enable the uart
cr1 |= CYGHWR_HAL_STM32_UART_CR1_UE;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 );
}示例14: at91_adc_enable
//==========================================================================
// This function is called from the generic ADC package to enable the
// channel in response to a CYG_IO_SET_CONFIG_ADC_ENABLE config operation.
// It should take any steps needed to start the channel generating samples
//==========================================================================
static void at91_adc_enable(cyg_adc_channel *chan)
{
at91_adc_info *info = chan->device->dev_priv;
// Enable the channel
HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CHER), \
AT91_ADC_CHER_CHx(chan->channel));
//
// Unmask interrupt as soon as 1 channel is enable
//
if (!info->chan_mask)
{
cyg_drv_interrupt_unmask(info->timer_vector);
// Enable timer interrupt
HAL_WRITE_UINT32(info->tc_base+AT91_TC_IER, AT91_TC_IER_CPC);
// Enable the clock
HAL_WRITE_UINT32(info->tc_base+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
// Start timer
HAL_WRITE_UINT32(info->tc_base+AT91_TC_CCR, AT91_TC_CCR_TRIG);
// Start ADC sampling
HAL_WRITE_UINT32((info->adc_base + AT91_ADC_CR), AT91_ADC_CR_START);
}
info->chan_mask |= AT91_ADC_CHER_CHx(chan->channel);
}示例15: usbs_state_notify
// There has been a change in state. Update the end point.
static void
usbs_state_notify (usbs_control_endpoint * pcep)
{
static int old_state = USBS_STATE_CHANGE_POWERED;
int state = pcep->state & USBS_STATE_MASK;
if (pcep->state != old_state) {
usbs_end_all_transfers (-EPIPE);
switch (state) {
case USBS_STATE_DETACHED:
case USBS_STATE_ATTACHED:
case USBS_STATE_POWERED:
// Nothing to do
break;
case USBS_STATE_DEFAULT:
HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_GLB_STATE, 0);
break;
case USBS_STATE_ADDRESSED:
HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_GLB_STATE, AT91_UDP_GLB_FADDEN);
break;
case USBS_STATE_CONFIGURED:
HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_GLB_STATE, AT91_UDP_GLB_CONFG);
break;
default:
CYG_FAIL("Unknown endpoint state");
}
if (pcep->state_change_fn) {
(*pcep->state_change_fn) (pcep, 0, pcep->state, old_state);
}
old_state = pcep->state;
}
}