C++ HAL_READ_UINT8函数代码示例

static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, 
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
    int res = 0;
    cyg_uint8 eir, c;
    channel_data_t* chan = (channel_data_t*)__ch_data;
    CYGARC_HAL_SAVE_GP();

    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);

    HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_EIR, eir);

    *__ctrlc = 0;
    if( (eir & CYG_DEVICE_BK0_EIR_mask) == CYG_DEVICE_BK0_EIR_IRQ_RX ) {

        HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_RXD, c);
    
        if( cyg_hal_is_break( &c , 1 ) )
            *__ctrlc = 1;

        res = CYG_ISR_HANDLED;
    }

    CYGARC_HAL_RESTORE_GP();
    return res;
}

static int
cyg_hal_plf_sci_isr(void *__ch_data, int* __ctrlc, 
                    CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
    cyg_uint8 c, sr;
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    int res = 0;
    CYGARC_HAL_SAVE_GP();

    *__ctrlc = 0;
    HAL_READ_UINT8(base+_REG_SCSSR, sr);
    if (sr & CYGARC_REG_SCI_SCSSR_ORER) {
        // Serial RX overrun. Clear error and hope protocol recovers.
        HAL_WRITE_UINT8(base+_REG_SCSSR, 
                        CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_ORER);
        res = CYG_ISR_HANDLED;
    } else if (sr & CYGARC_REG_SCI_SCSSR_RDRF) {
        // Received character
        HAL_READ_UINT8(base+_REG_SCRDR, c);

        // Clear buffer full flag.
        HAL_WRITE_UINT8(base+_REG_SCSSR, 
                        CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_RDRF);

        if( cyg_hal_is_break( &c , 1 ) )
            *__ctrlc = 1;

        res = CYG_ISR_HANDLED;
    }

    CYGARC_HAL_RESTORE_GP();
    return res;
}

static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
    cyg_uint8* port;
    cyg_uint8 _status;

    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    // Go ahead and assume it is channels[0].
    if (__ch_data == 0)
      __ch_data = (void*)&channels[0];

    port = ((channel_data_t*)__ch_data)->base;

    HAL_READ_UINT8(port + _SERIAL_SR, _status);
    if ((_status & SIO_LSTAT_RRDY) == 0)
        return false;

    HAL_READ_UINT8(port + _SERIAL_RXR, *ch);

    // We must ack the interrupt caused by that read to avoid
    // confusing the GDB stub ROM.
    HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_SERIAL_0_RX );    

    return true;
}

//static 
cyg_bool
cyg_hal_plf_scif_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    cyg_uint16 fdr, sr;
    cyg_bool res = false;

    HAL_READ_UINT16(base+_REG_SCSSR, sr);
    if (sr & CYGARC_REG_SCIF_SCSSR_ER) {
        cyg_uint8 ssr2;
        HAL_WRITE_UINT16(base+_REG_SCFER, 0);
        HAL_READ_UINT8(base+_REG_SC2SSR, ssr2);
        ssr2 &= ~CYGARC_REG_SCIF_SC2SSR_ORER;
        HAL_WRITE_UINT8(base+_REG_SC2SSR, ssr2);
        HAL_WRITE_UINT16(base+_REG_SCSSR,
                         CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_BRK | CYGARC_REG_SCIF_SCSSR_FER | CYGARC_REG_SCIF_SCSSR_PER));
    }


    HAL_READ_UINT16(base+_REG_SCFDR, fdr);
    if (0 != (fdr & CYGARC_REG_SCIF_SCFDR_RCOUNT_MASK)) {

        HAL_READ_UINT8(base+_REG_SCFRDR, *ch);

        // Clear DR/RDF flags
        HAL_READ_UINT16(base+_REG_SCSSR, sr);
        HAL_WRITE_UINT16(base+_REG_SCSSR,
                         CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF | CYGARC_REG_SCIF_SCSSR_DR));

        res = true;
    }

    return res;
}

static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{

    channel_data_t* chan = (channel_data_t*)__ch_data;
    CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base;
    cyg_uint8 uart_s1;
    int res = 0;
    cyg_uint8 ch_in;
    CYGARC_HAL_SAVE_GP();

    *__ctrlc = 0;

    HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1);
    if (uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF) {
        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in);
        if( cyg_hal_is_break( (char *) &ch_in , 1 ) )
            *__ctrlc = 1;

        res = CYG_ISR_HANDLED;
    }

    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);

    CYGARC_HAL_RESTORE_GP();
    return res;
}

// Sending out a command. The controller command, if any, gets sent here.
// This is followed by the first byte for the keyboard or mouse. The
// remaining bytes and any retransmits will be handled by the interrupt
// handler.
static void
ps2_send_command(int controller_command, unsigned char* command, int length, int mouse)
{
    int     status;
    
    CYG_PRECONDITION(NULL == ps2_command, "Only one send command is allowed at a time");
    CYG_PRECONDITION((KC_CONTROL_NULL != controller_command) || (NULL != command), "no-op");
    CYG_PRECONDITION(!mouse || (KC_CONTROL_NULL == controller_command), "cannot combine controller and mouse commands");
    
    ps2_command         = command;
    ps2_command_index   = 0;
    ps2_command_length  = length;
    ps2_command_mouse   = 0;
    ps2_command_ack     = 0;

    if (KC_CONTROL_NULL != controller_command) {
        do {
            HAL_READ_UINT8(KC_STATUS, status);
        } while (status & KC_STATUS_INPB);
        HAL_WRITE_UINT8(KC_CONTROL, controller_command);
    }

    if (length > 0) {
        if (mouse) {
            do {
                HAL_READ_UINT8(KC_STATUS, status);
            } while (status & KC_STATUS_INPB);
            HAL_WRITE_UINT8(KC_CONTROL, KC_CONTROL_WRITE_AUX);
        }
        do {
            HAL_READ_UINT8(KC_STATUS, status);
        } while (status & KC_STATUS_INPB);
        HAL_WRITE_UINT8(KC_INPUT, command[0]);
    }
}

static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, 
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
    int res = 0;
    channel_data_t* chan = (channel_data_t*)__ch_data;
    char c;
    cyg_uint8 lsr;
    CYGARC_HAL_SAVE_GP();

    cyg_drv_interrupt_acknowledge(chan->isr_vector);

    *__ctrlc = 0;
    HAL_READ_UINT8(chan->base+CYG_DEV_LSR, lsr);
    if ( (lsr & SIO_LSR_DR) != 0 ) {

        HAL_READ_UINT8(chan->base+CYG_DEV_RBR, c);
        if( cyg_hal_is_break( &c , 1 ) )
            *__ctrlc = 1;

        res = CYG_ISR_HANDLED;
    }

    CYGARC_HAL_RESTORE_GP();
    return res;
}

static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, 
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
    channel_data_t* chan = (channel_data_t*)__ch_data;
    cyg_uint8 iir;
    int res = 0;
    CYGARC_HAL_SAVE_GP();

    HAL_READ_UINT8(chan->base+PXA2X0_UART_IIR, iir);
    iir &= PXA2X0_UART_IIR_ID_MASK;

    *__ctrlc = 0;
    if ( iir == 0x04 ) {
        cyg_uint8 c, lsr;
        HAL_READ_UINT8(chan->base+PXA2X0_UART_LSR, lsr);
        if (lsr & PXA2X0_UART_LSR_DR) {

            HAL_READ_UINT8(chan->base+PXA2X0_UART_RBR, c);

            if( cyg_hal_is_break( &c , 1 ) )
                *__ctrlc = 1;
        }

        // Acknowledge the interrupt
        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
        res = CYG_ISR_HANDLED;
    }

    CYGARC_HAL_RESTORE_GP();
    return res;
}

void
cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c)
{
    channel_data_t* chan = (channel_data_t*)__ch_data;
    cyg_uint8* base = chan->base;
    cyg_uint16 fdr, sr;
    cyg_uint8 scscr = 0;
    CYGARC_HAL_SAVE_GP();

    HAL_READ_UINT8(base+_REG_SCSCR, scscr);
    if (chan->irda_mode) {
        HAL_WRITE_UINT8(base+_REG_SCSCR, scscr|CYGARC_REG_SCIF_SCSCR_TE);
    }
#ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
    if (chan->async_rxtx_mode) {
        HAL_WRITE_UINT8(base+_REG_SCSCR, (scscr|CYGARC_REG_SCIF_SCSCR_TE)&~CYGARC_REG_SCIF_SCSCR_RE);
    }
#endif

    do {
        HAL_READ_UINT16(base+_REG_SCFDR, fdr);
    } while (((fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) >> CYGARC_REG_SCIF_SCFDR_TCOUNT_shift) == 16);

    HAL_WRITE_UINT8(base+_REG_SCFTDR, c);

    // Clear FIFO-empty/transmit end flags (read back SR first)
    HAL_READ_UINT16(base+_REG_SCSSR, sr);
    HAL_WRITE_UINT16(base+_REG_SCSSR, CYGARC_REG_SCIF_SCSSR_CLEARMASK   
                     & ~(CYGARC_REG_SCIF_SCSSR_TDFE | CYGARC_REG_SCIF_SCSSR_TEND ));

    // Hang around until all characters have been safely sent.
    do {
        HAL_READ_UINT16(base+_REG_SCSSR, sr);
    } while ((sr & CYGARC_REG_SCIF_SCSSR_TEND) == 0);


    if (chan->irda_mode) {
#ifdef CYGHWR_HAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION
        // In IrDA mode there will be generated spurious RX events when
        // the TX unit is switched on. Eat that character.
        cyg_uint8 _junk;
        HAL_READ_UINT8(base+_REG_SCFRDR, _junk);

        // Clear buffer full flag (read back first)
        HAL_READ_UINT16(base+_REG_SCSSR, sr);
        HAL_WRITE_UINT16(base+_REG_SCSSR, 
                         CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF|CYGARC_REG_SCIF_SCSSR_DR));
#endif // CYGHWR_HAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION
        // Disable transmitter again
        HAL_WRITE_UINT8(base+_REG_SCSCR, scscr);
    }
#ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
    if (chan->async_rxtx_mode) {
        // Disable transmitter, enable receiver
        HAL_WRITE_UINT8(base+_REG_SCSCR, scscr);
    }
#endif // CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX

    CYGARC_HAL_RESTORE_GP();
}

static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
    int res = 0;
    cyg_uint8 _iir, c;
    channel_data_t* chan;
    CYGARC_HAL_SAVE_GP();

    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    // Go ahead and assume it is channels[0].
    if (__ch_data == 0)
        __ch_data = (void*)&channels[0];

    chan = (channel_data_t*)__ch_data;

    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);

    HAL_READ_UINT8(chan->base + SER_16550_IIR, _iir);
    _iir &= SIO_IIR_ID_MASK;

    *__ctrlc = 0;
    if ((_iir == ISR_Rx_Avail) || (_iir == ISR_Rx_Char_Timeout)) {

        HAL_READ_UINT8(chan->base + SER_16550_RBR, c);

        if( cyg_hal_is_break( &c , 1 ) )
            *__ctrlc = 1;

        res = CYG_ISR_HANDLED;
    }

    CYGARC_HAL_RESTORE_GP();
    return res;
}

void
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch)
{
    cyg_uint8* port;
    cyg_uint8 _lsr;

    // Some of the diagnostic print code calls through here with no idea what the ch_data is.
    // Go ahead and assume it is channels[0].
    if (__ch_data == 0)
      __ch_data = (void*)&channels[0];

    port = ((channel_data_t*)__ch_data)->base;

    CYGARC_HAL_SAVE_GP();

    do {
        HAL_READ_UINT8(port+SER_16550_LSR, _lsr);
    } while ((_lsr & SIO_LSR_THRE) == 0);

    // Now, the transmit buffer is empty
    HAL_WRITE_UINT8(port+SER_16550_THR, __ch);

    // Hang around until the character has been safely sent.
    do {
        HAL_READ_UINT8(port+SER_16550_LSR, _lsr);
    } while ((_lsr & SIO_LSR_THRE) == 0);

    CYGARC_HAL_RESTORE_GP();
}

void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
    cyg_uint8 port;
    cyg_uint8 value;

    port = ((channel_data_t*)__ch_data)->base;

    // set the port direction and function registers to serial
    switch (port){
        case CYG_HAL_FR30_MB91301_SER0_BASE:
            HAL_READ_UINT8(CYG_HAL_FR30_MB91301_DDRJ, value);
            value |= 0x6;
            value &= ~0x1;
            HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_DDRJ, value);
            HAL_READ_UINT8(CYG_HAL_FR30_MB91301_PFRJ, value);
            HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_PFRJ, value | 0x7);
            if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT == 0){
                cyg_hal_plf_serial_set_baudrate_internal(port, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD);
            } else {
                cyg_hal_plf_serial_set_baudrate_internal(port, CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD);
            }
            break;

        case CYG_HAL_FR30_MB91301_SER1_BASE:
            HAL_READ_UINT8(CYG_HAL_FR30_MB91301_DDRJ, value);
            value |= 0x30;
            value &= ~0x8;
            HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_DDRJ, value);
            HAL_READ_UINT8(CYG_HAL_FR30_MB91301_PFRJ, value);
            HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_PFRJ, value | 0x38);
            if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT == 1){
                cyg_hal_plf_serial_set_baudrate_internal(port, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD);
            } else {
                cyg_hal_plf_serial_set_baudrate_internal(port, CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD);
            }
            break;
/*
        case CYG_HAL_FR30_MB91301_SER2_BASE:
            HAL_READ_UINT8(CYG_HAL_FR30_MB91301_DDRG, value);
            HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_DDRG, value | 0x40);
            HAL_READ_UINT8(CYG_HAL_FR30_MB91301_PFRG, value);
            HAL_WRITE_UINT8(CYG_HAL_FR30_MB91301_PFRG, value | 0x60);
            break;
*/
    }

    // set up U-Timer
/*    HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_UTIMC_OFFSET, 0x02);
    // 115200 bps
    HAL_WRITE_UINT16(port + CYG_HAL_FR30_MB91301_UTIMR_OFFSET, 0x7);

    cyg_hal_plf_serial_set_baudrate_internal(port, baudrate);
*/
    // setup UART
    HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_SCR_OFFSET, 0x13);
    HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_SMR_OFFSET, 0x30);
}

static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
    channel_data_t* chan = (channel_data_t*)__ch_data;
    CYG_ADDRESS uart_p = ((channel_data_t*)__ch_data)->base;
    cyg_uint8 ser_port_reg;
    int ret = 0;
    va_list ap;

    CYGARC_HAL_SAVE_GP();
    va_start(ap, __func);

    switch (__func) {
    case __COMMCTL_IRQ_ENABLE:
        chan->irq_state = 1;
        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
        HAL_INTERRUPT_UNMASK(chan->isr_vector);

        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
        ser_port_reg |= CYGHWR_DEV_FREESCALE_UART_C2_RIE;
        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);

        break;
    case __COMMCTL_IRQ_DISABLE:
        ret = chan->irq_state;
        chan->irq_state = 0;
        HAL_INTERRUPT_MASK(chan->isr_vector);

        HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
        ser_port_reg &= ~(cyg_uint8)CYGHWR_DEV_FREESCALE_UART_C2_RIE;
        HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
        break;
    case __COMMCTL_DBG_ISR_VECTOR:
        ret = chan->isr_vector;
        break;
    case __COMMCTL_SET_TIMEOUT:
        ret = chan->msec_timeout;
        chan->msec_timeout = va_arg(ap, cyg_uint32);
    case __COMMCTL_GETBAUD:
        ret = chan->baud_rate;
        break;
    case __COMMCTL_SETBAUD:
        chan->baud_rate = va_arg(ap, cyg_int32);
        // Should we verify this value here?
        cyg_hal_plf_serial_init_channel(chan);
        ret = 0;
        break;
    default:
        break;
    }

    va_end(ap);
    CYGARC_HAL_RESTORE_GP();
    return ret;
}

externC bool
hal_ppc405_i2c_put_bytes(int addr, cyg_uint8 *val, int len)
{
    cyg_uint8 stat, extstat, xfrcnt, cmd, size;
    int i, j;

    // The hardware can only move up to 4 bytes in a single operation
    // This code breaks the request down into chunks of up to 4 bytes
    // and checks the status after each chunk.
    // Note: the actual device may impose additional size restrictions,
    // e.g. some EEPROM devices may limit a single write to 32 bytes.
    for (i = 0;  i < len;  i += size) {
        HAL_WRITE_UINT8(IIC0_STS, (IIC0_STS_SCMP|IIC0_STS_IRQA));
        HAL_WRITE_UINT8(IIC0_EXTSTS, (IIC0_EXTSTS_IRQP|IIC0_EXTSTS_IRQD));
        HAL_WRITE_UINT8(IIC0_MDCNTL, (IIC0_MDCNTL_FSDB|IIC0_MDCNTL_FMDB));
        cmd = IIC0_CNTL_RW_WRITE|IIC0_CNTL_PT;
        size = (len - i);
        if (size > 4) {
            size = 4;
            cmd |= IIC0_CNTL_CHT;
        }
        cmd |= ((size-1)<<IIC0_CNTL_TCT_SHIFT);
        for (j = 0;  j < size;  j++) {
            HAL_WRITE_UINT8(IIC0_MDBUF, val[i+j]);
        }
        HAL_WRITE_UINT8(IIC0_LMADR, addr);
        HAL_WRITE_UINT8(IIC0_CNTL, cmd);
        while (true) {
            CYGACC_CALL_IF_DELAY_US(10);   // 10us
            HAL_READ_UINT8(IIC0_STS, stat);
            if ((stat & IIC0_STS_PT) == 0) {
                if ((stat & IIC0_STS_ERR) != 0) {
                    // Some sort of error
                    HAL_READ_UINT8(IIC0_EXTSTS, extstat);
                    HAL_READ_UINT8(IIC0_XFRCNT, xfrcnt);
                    HAL_WRITE_UINT8(IIC0_EXTSTS, extstat);
                    HAL_WRITE_UINT8(IIC0_MDCNTL, (IIC0_MDCNTL_FSDB|IIC0_MDCNTL_FMDB));
                    HAL_WRITE_UINT8(IIC0_STS, (IIC0_STS_SCMP|IIC0_STS_IRQA));
                    diag_printf("%s addr: %x, len: %d, err: %x/%x, count: %d, cmd: %x\n",
                                __FUNCTION__, addr, len, stat, extstat, xfrcnt, cmd);
                    diag_printf("buf: ");
                    for (j = 0;  j < size;  j++) {
                        diag_printf("0x%02x ", val[i+j]);
                    }
                    diag_printf("\n");
                    return false;
                }
                break;
            }
        }
    }
    return true;
}

static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
    static int irq_state = 0;
    channel_data_t* chan = (channel_data_t*)__ch_data;
    int ret = -1;
    cyg_uint8 ier;
	va_list ap;

    CYGARC_HAL_SAVE_GP();
    va_start(ap, __func);

    switch (__func) {
    case __COMMCTL_GETBAUD:
        ret = chan->baud_rate;
        break;
    case __COMMCTL_SETBAUD:
        chan->baud_rate = va_arg(ap, cyg_int32);
        // Should we verify this value here?
        init_channel(chan);
        ret = 0;
        break;
    case __COMMCTL_IRQ_ENABLE:
        HAL_INTERRUPT_UNMASK(chan->isr_vector);
        HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
        HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier);
        ier |= PXA2X0_UART_IER_RAVIE;
        HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier);
        irq_state = 1;
        break;
    case __COMMCTL_IRQ_DISABLE:
        ret = irq_state;
        irq_state = 0;
        HAL_INTERRUPT_MASK(chan->isr_vector);
        HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier);
        ier &= ~PXA2X0_UART_IER_RAVIE;
        HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier);
        break;
    case __COMMCTL_DBG_ISR_VECTOR:
        ret = chan->isr_vector;
        break;
    case __COMMCTL_SET_TIMEOUT:
        ret = chan->msec_timeout;
        chan->msec_timeout = va_arg(ap, cyg_uint32);
        break;
    default:
        break;
    }
    va_end(ap);
    CYGARC_HAL_RESTORE_GP();
    return ret;
}